v850.md (cbranchsf4): New pattern.
* config/v850/v850.md (cbranchsf4): New pattern. (cstoresf4): New pattern. (cbranchdf4): New pattern. (cstoredf4): New pattern. (movsicc): Disallow floating point comparisons. (cmpsf_le_insn): Fix order of operators. (cmpsf_lt_insn): Likewise. (cmpsf_eq_insn): Likewise. (cmpdf_le_insn): Likewise. (cmpdf_lt_insn): Likewise. (cmpdf_eq_insn): Likewise. (cmpsf_ge_insn): Use LE comparison. (cmpdf_ge_insn): Likewise. (cmpsf_gt_insn): Use LT comparison. (cmpdf_gt_insn): Likewise. (cmpsf_ne_insn): Delete pattern. (cmpdf_ne_insn): Delete pattern. * config/v850/v850.c (v850_gen_float_compare): Use gen_cmpdf_eq_insn for NE comparison. (v850_float_z_comparison_operator) (v850_float_nz_comparison_operator): Move from here ... * config/v850/predicates.md: ... to here. Move GT and GE comparisons into v850_float_z_comparison_operator. * config/v850/v850-protos.h (v850_float_z_comparison_operator): Delete prototype. (v850_float_nz_comparison_operator): Likewise. From-SVN: r195053
This commit is contained in:
Nguyen Duy Dat
Nick Clifton
parent
458752def1
commit
3cd232b5aa
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@ -1,3 +1,33 @@
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2013-01-09 Nguyen Duy Dat
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Nick Clifton <nickc@redhat.com>
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* config/v850/v850.md (cbranchsf4): New pattern.
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(cstoresf4): New pattern.
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(cbranchdf4): New pattern.
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(cstoredf4): New pattern.
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(movsicc): Disallow floating point comparisons.
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(cmpsf_le_insn): Fix order of operators.
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(cmpsf_lt_insn): Likewise.
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(cmpsf_eq_insn): Likewise.
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(cmpdf_le_insn): Likewise.
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(cmpdf_lt_insn): Likewise.
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(cmpdf_eq_insn): Likewise.
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(cmpsf_ge_insn): Use LE comparison.
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(cmpdf_ge_insn): Likewise.
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(cmpsf_gt_insn): Use LT comparison.
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(cmpdf_gt_insn): Likewise.
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(cmpsf_ne_insn): Delete pattern.
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(cmpdf_ne_insn): Delete pattern.
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* config/v850/v850.c (v850_gen_float_compare): Use
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gen_cmpdf_eq_insn for NE comparison.
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(v850_float_z_comparison_operator)
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(v850_float_nz_comparison_operator): Move from here ...
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* config/v850/predicates.md: ... to here. Move GT and GE
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comparisons into v850_float_z_comparison_operator.
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* config/v850/v850-protos.h (v850_float_z_comparison_operator):
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Delete prototype.
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(v850_float_nz_comparison_operator): Likewise.
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2013-01-09 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
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* config/pa/pa.c (pa_emit_move_sequence): Replace calls to gen_insv
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@ -497,3 +497,68 @@
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return op == CONST0_RTX(mode);
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})
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;; Return true if the floating point comparison operation
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;; given produces a canonical answer.
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(define_predicate "v850_float_z_comparison_operator"
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(match_code "lt,le,eq,gt,ge")
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{
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enum rtx_code code = GET_CODE (op);
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if (GET_RTX_CLASS (code) != RTX_COMPARE
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&& GET_RTX_CLASS (code) != RTX_COMM_COMPARE)
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return 0;
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if (mode != GET_MODE (op) && mode != VOIDmode)
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return 0;
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if ((GET_CODE (XEXP (op, 0)) != REG
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|| REGNO (XEXP (op, 0)) != CC_REGNUM)
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|| XEXP (op, 1) != const0_rtx)
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return 0;
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if (GET_MODE (XEXP (op, 0)) == CC_FPU_LTmode)
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return code == LT;
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if (GET_MODE (XEXP (op, 0)) == CC_FPU_LEmode)
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return code == LE;
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if (GET_MODE (XEXP (op, 0)) == CC_FPU_EQmode)
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return code == EQ;
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if (GET_MODE (XEXP (op, 0)) == CC_FPU_GTmode)
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return code == GT;
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if (GET_MODE (XEXP (op, 0)) == CC_FPU_GEmode)
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return code == GE;
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/* Note we do not accept CC_FPU_NEmode here. See
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v850_float_nz_comparison for the reason why. */
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return 0;
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})
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;; Return true if the floating point comparison operation
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;; given produces an inverted answer.
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(define_predicate "v850_float_nz_comparison_operator"
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(match_code "ne")
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{
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enum rtx_code code = GET_CODE (op);
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/* The V850E2V3 does not have a floating point NZ comparison operator.
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Instead it is implemented as an EQ comparison and this function ensures
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that the branch_nz_normal and set_nz_insn patterns are used to examine
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(and invert) the result of the floating point comparison. */
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if (GET_RTX_CLASS (code) != RTX_COMPARE
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&& GET_RTX_CLASS (code) != RTX_COMM_COMPARE)
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return 0;
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if (mode != GET_MODE (op) && mode != VOIDmode)
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return 0;
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if ((GET_CODE (XEXP (op, 0)) != REG
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|| REGNO (XEXP (op, 0)) != CC_REGNUM)
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|| XEXP (op, 1) != const0_rtx)
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return 0;
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if (GET_MODE (XEXP (op, 0)) == CC_FPU_NEmode)
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return code == NE;
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return 0;
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})
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@ -40,8 +40,6 @@ extern char * construct_restore_jr (rtx);
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extern char * construct_dispose_instruction (rtx);
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extern char * construct_prepare_instruction (rtx);
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extern int ep_memory_operand (rtx, enum machine_mode, int);
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extern int v850_float_z_comparison_operator (rtx, enum machine_mode);
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extern int v850_float_nz_comparison_operator (rtx, enum machine_mode);
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extern rtx v850_gen_compare (enum rtx_code, enum machine_mode,
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rtx, rtx);
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extern enum machine_mode v850_gen_float_compare (enum rtx_code,
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@ -898,61 +898,6 @@ output_move_single (rtx * operands)
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return "";
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}
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/* Generate comparison code. */
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int
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v850_float_z_comparison_operator (rtx op, enum machine_mode mode)
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{
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enum rtx_code code = GET_CODE (op);
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if (GET_RTX_CLASS (code) != RTX_COMPARE
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&& GET_RTX_CLASS (code) != RTX_COMM_COMPARE)
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return 0;
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if (mode != GET_MODE (op) && mode != VOIDmode)
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return 0;
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if ((GET_CODE (XEXP (op, 0)) != REG
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|| REGNO (XEXP (op, 0)) != CC_REGNUM)
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|| XEXP (op, 1) != const0_rtx)
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return 0;
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if (GET_MODE (XEXP (op, 0)) == CC_FPU_LTmode)
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return code == LT;
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if (GET_MODE (XEXP (op, 0)) == CC_FPU_LEmode)
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return code == LE;
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if (GET_MODE (XEXP (op, 0)) == CC_FPU_EQmode)
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return code == EQ;
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return 0;
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}
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int
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v850_float_nz_comparison_operator (rtx op, enum machine_mode mode)
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{
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enum rtx_code code = GET_CODE (op);
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if (GET_RTX_CLASS (code) != RTX_COMPARE
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&& GET_RTX_CLASS (code) != RTX_COMM_COMPARE)
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return 0;
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if (mode != GET_MODE (op) && mode != VOIDmode)
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return 0;
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if ((GET_CODE (XEXP (op, 0)) != REG
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|| REGNO (XEXP (op, 0)) != CC_REGNUM)
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|| XEXP (op, 1) != const0_rtx)
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return 0;
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if (GET_MODE (XEXP (op, 0)) == CC_FPU_GTmode)
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return code == GT;
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if (GET_MODE (XEXP (op, 0)) == CC_FPU_GEmode)
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return code == GE;
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if (GET_MODE (XEXP (op, 0)) == CC_FPU_NEmode)
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return code == NE;
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return code == GT || code == GE || code == NE;
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}
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enum machine_mode
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v850_select_cc_mode (enum rtx_code cond, rtx op0, rtx op1 ATTRIBUTE_UNUSED)
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{
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@ -973,7 +918,7 @@ v850_select_cc_mode (enum rtx_code cond, rtx op0, rtx op1 ATTRIBUTE_UNUSED)
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case NE:
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return CC_FPU_NEmode;
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default:
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abort ();
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gcc_unreachable ();
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}
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}
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return CCmode;
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@ -982,7 +927,7 @@ v850_select_cc_mode (enum rtx_code cond, rtx op0, rtx op1 ATTRIBUTE_UNUSED)
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enum machine_mode
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v850_gen_float_compare (enum rtx_code cond, enum machine_mode mode ATTRIBUTE_UNUSED, rtx op0, rtx op1)
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{
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if (GET_MODE(op0) == DFmode)
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if (GET_MODE (op0) == DFmode)
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{
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switch (cond)
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{
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@ -998,17 +943,18 @@ v850_gen_float_compare (enum rtx_code cond, enum machine_mode mode ATTRIBUTE_UNU
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case GT:
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emit_insn (gen_cmpdf_gt_insn (op0, op1));
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break;
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case NE:
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/* Note: There is no NE comparison operator. So we
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perform an EQ comparison and invert the branch.
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See v850_float_nz_comparison for how this is done. */
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case EQ:
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emit_insn (gen_cmpdf_eq_insn (op0, op1));
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break;
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case NE:
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emit_insn (gen_cmpdf_ne_insn (op0, op1));
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break;
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default:
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abort ();
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gcc_unreachable ();
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}
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}
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else if (GET_MODE(v850_compare_op0) == SFmode)
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else if (GET_MODE (v850_compare_op0) == SFmode)
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{
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switch (cond)
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{
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@ -1024,20 +970,19 @@ v850_gen_float_compare (enum rtx_code cond, enum machine_mode mode ATTRIBUTE_UNU
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case GT:
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emit_insn (gen_cmpsf_gt_insn(op0, op1));
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break;
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case NE:
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/* Note: There is no NE comparison operator. So we
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perform an EQ comparison and invert the branch.
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See v850_float_nz_comparison for how this is done. */
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case EQ:
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emit_insn (gen_cmpsf_eq_insn(op0, op1));
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break;
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case NE:
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emit_insn (gen_cmpsf_ne_insn(op0, op1));
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break;
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default:
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abort ();
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gcc_unreachable ();
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}
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}
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else
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{
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abort ();
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}
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gcc_unreachable ();
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return v850_select_cc_mode (cond, op0, op1);
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}
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@ -405,6 +405,114 @@
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[(set_attr "length" "2,2")
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(set_attr "cc" "compare")])
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(define_expand "cbranchsf4"
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[(set (pc)
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(if_then_else (match_operator 0 "ordered_comparison_operator"
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[(match_operand:SF 1 "register_operand")
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(match_operand:SF 2 "register_operand")])
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(label_ref (match_operand 3 ""))
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(pc)))
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(clobber (cc0))]
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"TARGET_V850E2V3"
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{
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v850_compare_op0 = operands[1];
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v850_compare_op1 = operands[2];
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enum rtx_code cond = GET_CODE(operands[0]);
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enum machine_mode mode;
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rtx fcc_reg;
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rtx cc_reg;
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rtx tmp;
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if (GET_MODE_CLASS (GET_MODE (v850_compare_op0)) != MODE_FLOAT)
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FAIL;
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mode = v850_gen_float_compare (cond, VOIDmode, v850_compare_op0, v850_compare_op1);
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fcc_reg = gen_rtx_REG (mode, FCC_REGNUM);
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cc_reg = gen_rtx_REG (mode, CC_REGNUM);
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emit_insn(gen_rtx_SET (mode, cc_reg, fcc_reg));
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tmp = gen_rtx_fmt_ee (cond, mode, cc_reg, const0_rtx);
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tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
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gen_rtx_LABEL_REF (VOIDmode, operands[3]), pc_rtx);
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emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
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DONE;
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})
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(define_insn "cstoresf4"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(match_operator:SI 1 "ordered_comparison_operator"
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[(match_operand:SF 2 "register_operand" "r")
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(match_operand:SF 3 "register_operand" "r")]))]
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"TARGET_V850E2V3"
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{
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if (GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
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return "cmpf.s %c1, %z2, %z3 ; trfsr ; setf nz, %0";
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if (GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE)
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return "cmpf.s %c1, %z2, %z3 ; trfsr ; setf z, %0";
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if (GET_CODE (operands[1]) == EQ)
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return "cmpf.s eq, %z2, %z3 ; trfsr ; setf z, %0";
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if (GET_CODE (operands[1]) == NE)
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return "cmpf.s neq, %z2, %z3 ; trfsr ; setf nz, %0";
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gcc_unreachable ();
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}
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[(set_attr "length" "12")
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(set_attr "type" "fpu")]
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)
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(define_expand "cbranchdf4"
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[(set (pc)
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(if_then_else (match_operator 0 "ordered_comparison_operator"
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[(match_operand:DF 1 "even_reg_operand")
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(match_operand:DF 2 "even_reg_operand")])
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(label_ref (match_operand 3 ""))
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(pc)))
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(clobber (cc0))]
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"TARGET_V850E2V3"
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{
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v850_compare_op0 = operands[1];
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v850_compare_op1 = operands[2];
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enum rtx_code cond = GET_CODE(operands[0]);
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enum machine_mode mode;
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rtx fcc_reg;
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rtx cc_reg;
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rtx tmp;
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if (GET_MODE_CLASS (GET_MODE (v850_compare_op0)) != MODE_FLOAT)
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FAIL;
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mode = v850_gen_float_compare (cond, VOIDmode, v850_compare_op0, v850_compare_op1);
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fcc_reg = gen_rtx_REG (mode, FCC_REGNUM);
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cc_reg = gen_rtx_REG (mode, CC_REGNUM);
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emit_insn(gen_rtx_SET (mode, cc_reg, fcc_reg));
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tmp = gen_rtx_fmt_ee (cond, mode, cc_reg, const0_rtx);
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tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
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gen_rtx_LABEL_REF (VOIDmode, operands[3]), pc_rtx);
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emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
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DONE;
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})
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(define_insn "cstoredf4"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(match_operator:SI 1 "ordered_comparison_operator"
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[(match_operand:DF 2 "even_reg_operand" "r")
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(match_operand:DF 3 "even_reg_operand" "r")]))]
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"TARGET_V850E2V3"
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{
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if (GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
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return "cmpf.d %c1, %z2, %z3 ; trfsr ; setf nz, %0";
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if (GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE)
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return "cmpf.d %c1, %z2, %z3 ; trfsr ; setf z, %0";
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if (GET_CODE (operands[1]) == EQ)
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return "cmpf.d eq, %z2, %z3 ; trfsr ; setf z ,%0";
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if (GET_CODE (operands[1]) == NE)
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return "cmpf.d neq, %z2, %z3 ; trfsr ; setf nz, %0";
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gcc_unreachable ();
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}
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[(set_attr "length" "12")
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(set_attr "type" "fpu")]
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)
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(define_expand "cmpsf"
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[(set (reg:CC CC_REGNUM)
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(compare (match_operand:SF 0 "register_operand" "r")
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@ -940,6 +1048,11 @@
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(match_operand:SI 3 "reg_or_const_operand" "rI")))]
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"(TARGET_V850E || TARGET_V850E2_ALL)"
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{
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/* Make sure that we have an integer comparison... */
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if (GET_MODE (XEXP (operands[1], 0)) != CCmode
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&& GET_MODE (XEXP (operands[1], 0)) != SImode)
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FAIL;
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if ((GET_CODE (operands[2]) == CONST_INT
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&& GET_CODE (operands[3]) == CONST_INT))
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{
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@ -2210,7 +2323,7 @@
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(compare:CC_FPU_LE (match_operand:SF 0 "register_operand" "r")
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(match_operand:SF 1 "register_operand" "r")))]
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"TARGET_USE_FPU"
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"cmpf.s le,%z1,%z0"
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"cmpf.s le, %z0, %z1"
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[(set_attr "length" "4")
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(set_attr "cc" "none_0hit")
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(set_attr "type" "fpu")])
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@ -2220,7 +2333,7 @@
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(compare:CC_FPU_LT (match_operand:SF 0 "register_operand" "r")
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(match_operand:SF 1 "register_operand" "r")))]
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"TARGET_USE_FPU"
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"cmpf.s lt,%z1,%z0"
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"cmpf.s lt, %z0, %z1"
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[(set_attr "length" "4")
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(set_attr "cc" "none_0hit")
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(set_attr "type" "fpu")])
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@ -2230,7 +2343,7 @@
|
|||
(compare:CC_FPU_GE (match_operand:SF 0 "register_operand" "r")
|
||||
(match_operand:SF 1 "register_operand" "r")))]
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.s ge,%z1,%z0"
|
||||
"cmpf.s le, %z1, %z0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
|
@ -2240,7 +2353,7 @@
|
|||
(compare:CC_FPU_GT (match_operand:SF 0 "register_operand" "r")
|
||||
(match_operand:SF 1 "register_operand" "r")))]
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.s gt,%z1,%z0"
|
||||
"cmpf.s lt, %z1, %z0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
|
@ -2250,17 +2363,7 @@
|
|||
(compare:CC_FPU_EQ (match_operand:SF 0 "register_operand" "r")
|
||||
(match_operand:SF 1 "register_operand" "r")))]
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.s eq,%z1,%z0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
||||
(define_insn "cmpsf_ne_insn"
|
||||
[(set (reg:CC_FPU_NE FCC_REGNUM)
|
||||
(compare:CC_FPU_NE (match_operand:SF 0 "register_operand" "r")
|
||||
(match_operand:SF 1 "register_operand" "r")))]
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.s neq,%z1,%z0"
|
||||
"cmpf.s eq, %z0, %z1"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
|
@ -2272,7 +2375,7 @@
|
|||
(compare:CC_FPU_LE (match_operand:DF 0 "even_reg_operand" "r")
|
||||
(match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.d le,%z1,%z0"
|
||||
"cmpf.d le, %z0, %z1"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
|
@ -2282,7 +2385,7 @@
|
|||
(compare:CC_FPU_LT (match_operand:DF 0 "even_reg_operand" "r")
|
||||
(match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.d lt,%z1,%z0"
|
||||
"cmpf.d lt, %z0, %z1"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
|
@ -2292,7 +2395,7 @@
|
|||
(compare:CC_FPU_GE (match_operand:DF 0 "even_reg_operand" "r")
|
||||
(match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.d ge,%z1,%z0"
|
||||
"cmpf.d le, %z1, %z0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
|
@ -2300,9 +2403,9 @@
|
|||
(define_insn "cmpdf_gt_insn"
|
||||
[(set (reg:CC_FPU_GT FCC_REGNUM)
|
||||
(compare:CC_FPU_GT (match_operand:DF 0 "even_reg_operand" "r")
|
||||
(match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
(match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.d gt,%z1,%z0"
|
||||
"cmpf.d lt, %z1, %z0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
|
@ -2312,22 +2415,11 @@
|
|||
(compare:CC_FPU_EQ (match_operand:DF 0 "even_reg_operand" "r")
|
||||
(match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.d eq,%z1,%z0"
|
||||
"cmpf.d eq, %z0, %z1"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
||||
(define_insn "cmpdf_ne_insn"
|
||||
[(set (reg:CC_FPU_NE FCC_REGNUM)
|
||||
(compare:CC_FPU_NE (match_operand:DF 0 "even_reg_operand" "r")
|
||||
(match_operand:DF 1 "even_reg_operand" "r")))]
|
||||
"TARGET_USE_FPU"
|
||||
"cmpf.d neq,%z1,%z0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")
|
||||
(set_attr "type" "fpu")])
|
||||
|
||||
|
||||
;;
|
||||
;; Transfer a v850e2v3 fcc to the Z bit of CC0 (this is necessary to do a
|
||||
;; conditional branch based on a floating-point compare)
|
||||
|
|
|
|||
Loading…
Reference in New Issue