i386.md (unnamed peephole2): Do not force memory operands of arith or logical instructions into registers...
* config/i386/i386.md (unnamed peephole2): Do not force memory operands of arith or logical instructions into registers for non-TARGET_READ_MODIFY targets. (ffs_cmove): Change operand 0 predicate to register_operand. Change operand 1 predicate to nonimmediate_operand. (ffsdi2): Ditto. (*ffs_no_cmove): Change operand 0 predicate to register_operand. From-SVN: r141213
This commit is contained in:
Uros Bizjak
parent
73a5f1995f
commit
3cdf0c6237
@ -220,8 +220,8 @@ auto-vectorizer Dorit Nuzman dorit@il.ibm.com
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loop infrastructure Zdenek Dvorak ook@ucw.cz
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OpenMP Jakub Jelinek jakub@redhat.com
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Note that individuals who maintain parts of the compiler need approval to check
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in changes outside of the parts of the compiler they maintain.
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Note that individuals who maintain parts of the compiler need approval to
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check in changes outside of the parts of the compiler they maintain.
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Non-Algorithmic Maintainers
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137
gcc/ChangeLog
137
gcc/ChangeLog
@ -1,3 +1,14 @@
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2008-10-18 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (unnamed peephole2): Do not force memory
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operands of arith or logical instructions into registers for
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non-TARGET_READ_MODIFY targets.
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(ffs_cmove): Change operand 0 predicate to register_operand.
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Change operand 1 predicate to nonimmediate_operand.
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(ffsdi2): Ditto.
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(*ffs_no_cmove): Change operand 0 predicate to register_operand.
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2008-10-18 Richard Guenther <rguenther@suse.de>
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* tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Guard
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@ -69,8 +80,7 @@
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mark_hard_reg_early_clobbers): New functions.
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(process_bb_node_lives): Call
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make_early_clobber_and_input_conflicts and
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mark_hard_reg_early_clobbers. Make hard register inputs live
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again.
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mark_hard_reg_early_clobbers. Make hard register inputs live again.
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* doc/rtl.texi (clobber): Change descriotion of RA behaviour for
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early clobbers of pseudo-registers.
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@ -107,7 +117,7 @@
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* config/mn10300/constraints.md (S): Allow UNSPEC_GOTSYM_OFF.
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2008-10-15 Jan Sjodin <jan.sjodin@amd.com>
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Harsha Jagasia <harsha.jagasia@amd.com>
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Harsha Jagasia <harsha.jagasia@amd.com>
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PR tree-optimization/37485
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* graphite.c (gmp_cst_to_tree): Moved.
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@ -143,7 +153,7 @@
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(limit_scops): Same.
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2008-10-15 Sebastian Pop <sebastian.pop@amd.com>
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Harsha Jagasia <harsha.jagasia@amd.com>
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Harsha Jagasia <harsha.jagasia@amd.com>
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PR tree-optimization/37828
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* graphite.c (graphite_trans_loop_block): Do not loop block
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@ -215,12 +225,12 @@
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2008-10-14 Douglas Gregor <doug.gregor@gmail.com>
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PR c++/37553
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* tree.c (build_type_attribute_qual_variant): Hash on the
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unqualified type, and don't overwrite an existing
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(type_hash_eq): Make the TYPE_NAME of the types significant, to
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allow distinguishing between wchar_t and its underlying type. This
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also means that we'll retain a little more typedef information.
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PR c++/37553
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* tree.c (build_type_attribute_qual_variant): Hash on the
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unqualified type, and don't overwrite an existing
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(type_hash_eq): Make the TYPE_NAME of the types significant, to
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allow distinguishing between wchar_t and its underlying type. This
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also means that we'll retain a little more typedef information.
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2008-10-14 Andrey Belevantsev <abel@ispras.ru>
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Dmitry Melnik <dm@ispras.ru>
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@ -238,67 +248,67 @@
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(ia64_gen_spec_insn): Removed.
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(get_spec_check_gen_function, insn_can_be_in_speculative_p,
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ia64_gen_spec_check): New static functions.
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(ia64_alloc_sched_context, ia64_init_sched_context,
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ia64_set_sched_context, ia64_clear_sched_context,
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ia64_free_sched_context, ia64_get_insn_spec_ds,
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(ia64_alloc_sched_context, ia64_init_sched_context,
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ia64_set_sched_context, ia64_clear_sched_context,
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ia64_free_sched_context, ia64_get_insn_spec_ds,
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ia64_get_insn_checked_ds, ia64_skip_rtx_p): Declare functions.
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(ia64_needs_block_p): Change prototype.
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(ia64_gen_check): Rename to ia64_gen_spec_check.
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(ia64_adjust_cost): Rename to ia64_adjust_cost_2. Add new parameter
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(ia64_adjust_cost): Rename to ia64_adjust_cost_2. Add new parameter
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into declaration, add special memory dependencies handling.
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(TARGET_SCHED_ALLOC_SCHED_CONTEXT, TARGET_SCHED_INIT_SCHED_CONTEXT,
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TARGET_SCHED_SET_SCHED_CONTEXT, TARGET_SCHED_CLEAR_SCHED_CONTEXT,
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TARGET_SCHED_FREE_SCHED_CONTEXT, TARGET_SCHED_GET_INSN_SPEC_DS,
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TARGET_SCHED_GET_INSN_CHECKED_DS, TARGET_SCHED_SKIP_RTX_P):
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TARGET_SCHED_GET_INSN_CHECKED_DS, TARGET_SCHED_SKIP_RTX_P):
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Define new target hooks.
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(TARGET_SCHED_GEN_CHECK): Rename to TARGET_SCHED_GEN_SPEC_CHECK.
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(ia64_optimization_options): Turn on selective scheduling with -O3,
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(ia64_optimization_options): Turn on selective scheduling with -O3,
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disable -fauto-inc-dec. Set mflag_sched_control_spec to true by default
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with selective scheduling.
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(ia64_override_options): Initialize align_loops and align_functions
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to 32 and 64, respectively. Set global selective scheduling flags
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(ia64_override_options): Initialize align_loops and align_functions
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to 32 and 64, respectively. Set global selective scheduling flags
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according to target-dependent flags.
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(rtx_needs_barrier): Support UNSPEC_LDS_A.
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(group_barrier_needed): Use new mstop-bit-before-check flag.
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(group_barrier_needed): Use new mstop-bit-before-check flag.
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Add heuristic.
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(dfa_state_size): Make global.
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(spec_check_no, max_uid): Remove.
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(mem_ops_in_group, current_cycle): New variables.
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(mem_ops_in_group, current_cycle): New variables.
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(ia64_sched_init): Disable checks for !SCHED_GROUP_P after reload.
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Initialize new variables.
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(is_load_p, record_memory_reference): New functions.
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(ia64_dfa_sched_reorder): Lower priority of loads when limit is
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reached.
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(ia64_variable_issue): Change use of current_sched_info to
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Initialize new variables.
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(is_load_p, record_memory_reference): New functions.
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(ia64_dfa_sched_reorder): Lower priority of loads when limit is
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reached.
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(ia64_variable_issue): Change use of current_sched_info to
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sched_deps_info. Update comment. Note if a load or a store is issued.
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(ia64_first_cycle_multipass_dfa_lookahead_guard_spec): Require a cycle
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advance if maximal number of loads or stores was issued on current
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cycle.
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(ia64_first_cycle_multipass_dfa_lookahead_guard_spec): Require a cycle
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advance if maximal number of loads or stores was issued on current
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cycle.
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(scheduled_good_insn): New static helper function.
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(ia64_dfa_new_cycle): Assert that last_scheduled_insn is set when
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a group barrier is needed. Fix vertical spacing. Guard the code
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doing state transition with last_scheduled_insn check.
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Mark that a stop bit should be before current insn if there was a
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cycle advance. Update current_cycle and mem_ops_in_group.
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(ia64_dfa_new_cycle): Assert that last_scheduled_insn is set when
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a group barrier is needed. Fix vertical spacing. Guard the code
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doing state transition with last_scheduled_insn check.
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Mark that a stop bit should be before current insn if there was a
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cycle advance. Update current_cycle and mem_ops_in_group.
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(ia64_h_i_d_extended): Change use of current_sched_info to
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sched_deps_info. Reallocate stops_p by larger chunks.
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sched_deps_info. Reallocate stops_p by larger chunks.
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(struct _ia64_sched_context): New structure.
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(ia64_sched_context_t): New typedef.
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(ia64_alloc_sched_context, ia64_init_sched_context,
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(ia64_alloc_sched_context, ia64_init_sched_context,
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ia64_set_sched_context, ia64_clear_sched_context,
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ia64_free_sched_context): New static functions.
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(gen_func_t): New typedef.
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(get_spec_load_gen_function): New function.
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(SPEC_GEN_EXTEND_OFFSET): Declare.
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(ia64_set_sched_flags): Check common_sched_info instead of *flags.
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(get_mode_no_for_insn): Change the condition that prevents use of
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(get_mode_no_for_insn): Change the condition that prevents use of
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special hardware registers so it can now handle pseudos.
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(get_spec_unspec_code): New function.
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(ia64_skip_rtx_p, get_insn_spec_code, ia64_get_insn_spec_ds,
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ia64_get_insn_checked_ds, ia64_gen_spec_load): New static functions.
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(ia64_speculate_insn, ia64_needs_block_p): Support branchy checks
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during selective scheduling.
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(ia64_speculate_insn): Use ds_get_speculation_types when
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(ia64_speculate_insn): Use ds_get_speculation_types when
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determining whether we need to change the pattern.
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(SPEC_GEN_LD_MAP, SPEC_GEN_CHECK_OFFSET): Declare.
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(ia64_spec_check_src_p): Support new speculation/check codes.
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@ -307,38 +317,39 @@
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(insert_bundle_state): Minimize mid-bundle stop bits.
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(important_for_bundling_p): New function.
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(get_next_important_insn): Use important_for_bundling_p.
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(bundling): When shifting TImode from unimportant insns, ignore
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also group barriers. Assert that best state is found before
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the backward bundling pass. Print number of mid-bundle stop bits.
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Minimize mid-bundle stop bits. Check correct calculation of
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(bundling): When shifting TImode from unimportant insns, ignore
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also group barriers. Assert that best state is found before
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the backward bundling pass. Print number of mid-bundle stop bits.
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Minimize mid-bundle stop bits. Check correct calculation of
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mid-bundle stop bits.
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(ia64_sched_finish, final_emit_insn_group_barriers): Fix formatting.
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(final_emit_insn_group_barriers): Emit stop bits before insns starting
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a new cycle.
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(sel2_run): New variable.
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(ia64_reorg): When flag_selective_scheduling2 is set, run the selective
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scheduling pass instead of schedule_ebbs.
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(ia64_reorg): When flag_selective_scheduling2 is set, run the selective
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scheduling pass instead of schedule_ebbs.
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* config/ia64/ia64.md (speculable1, speculable2): New attributes.
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(UNSPEC_LDS_A): New UNSPEC.
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(movqi_internal, movhi_internal, movsi_internal, movdi_internal,
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movti_internal, movsf_internal, movdf_internal,
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(movqi_internal, movhi_internal, movsi_internal, movdi_internal,
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movti_internal, movsf_internal, movdf_internal,
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movxf_internal): Make visible. Add speculable* attributes.
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(output_c_nc): New mode attribute.
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(mov<mode>_speculative_a, zero_extend<mode>di2_speculative_a,
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mov<mode>_nc, zero_extend<mode>di2_nc,
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mov<mode>_nc, zero_extend<mode>di2_nc,
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advanced_load_check_nc_<mode>): New insns.
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(zero_extend*): Add speculable* attributes.
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* config/ia64/ia64.opt (msched_fp_mem_deps_zero_cost): New option.
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(msched-stop-bits-after-every-cycle): Likewise.
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(msched-max-memory-insns,
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msched-max-memory-insns-hard-limit): Likewise.
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(msched-max-memory-insns, msched-max-memory-insns-hard-limit):
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Likewise.
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(msched-spec-verbose): Remove.
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(msched-prefer-non-data-spec-insns,
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msched-prefer-non-control-spec-insns, msched-count-spec-in-critical-path,
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msel-sched-dont-check-control-spec): Use Target
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Report Var instead of Common Report Var.
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msched-prefer-non-control-spec-insns,
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msched-count-spec-in-critical-path,
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msel-sched-dont-check-control-spec): Use Target Report Var
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instead of Common Report Var.
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* config/ia64/itanium2.md: Remove incorrect bypass.
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@ -365,15 +376,16 @@
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for hppa64-linux-gnu targets.
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2008-10-13 Andrew Pinski <andrew_pinski@playstation.sony.com>
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Kaushal Kantawala <Kaushal_Kantawala@playstation.sony.com>
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Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
|
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Grace Cao <grace_cao@playstation.sony.com>
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Kaushal Kantawala <Kaushal_Kantawala@playstation.sony.com>
|
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Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
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Grace Cao <grace_cao@playstation.sony.com>
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* doc/invoke.texi (-mgen-cell-microcode): Document.
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(-mwarn-cell-microcode): Document.
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* cfglayout.c (locator_location): Export.
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* rtl.h (locator_location): Define prototype.
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* config/rs6000/predicates.md (cc_reg_not_micro_cr0_operand): New predicate.
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* config/rs6000/predicates.md (cc_reg_not_micro_cr0_operand):
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New predicate.
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* rs6000/rs6000-protos.h (rs6000_final_prescan_insn): Define prototype.
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* config/rs6000/rs6000.opt (mgen-cell-microcode): New option.
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(mwarn-cell-microcode): New option.
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@ -386,9 +398,10 @@
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* config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Define.
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* config/rs6000/rs6000.md
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Replace cc_reg_not_cr0_operand with cc_reg_not_micro_cr0_operand if
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the instruction would have been microcoded on the Cell.
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Set cell_micro to always on unnamed patterns for the string instructions.
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(cell_micro): Update definition, remove load/store conditional microcoded.
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the instruction would have been microcoded on the Cell. Set cell_micro
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to always on unnamed patterns for the string instructions.
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(cell_micro): Update definition, remove load/store conditional
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microcoded.
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(sign_extend:DI): Define new pattern for non microcoded version.
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(sign_extend:SI): Likewise.
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(compare (div:P)): Set cell_micro to not.
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@ -522,9 +535,8 @@
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DF_REF_CLASS, DF_REF_TYPE, DF_REF_CHAIN, DF_REF_ID, DF_REF_FLAGS,
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DF_REF_ORDER, DF_REF_IS_ARTIFICIAL, DF_REF_NEXT_REG,
|
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DF_REF_PREV_REG, DF_REF_EXTRACT_WIDTH, DF_REF_EXTRACT_OFFSET,
|
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DF_REF_EXTRACT_MODE): Replaced definition to access union
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df_ref_d.
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(DF_MWS_REG_DEF_P, DF_MWS_REG_USE_P, DF_MWS_TYPE): New macros.
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DF_REF_EXTRACT_MODE): Replaced definition to access union df_ref_d.
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(DF_MWS_REG_DEF_P, DF_MWS_REG_USE_P, DF_MWS_TYPE): New macros.
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(df_scan_bb_info, df_bb_regno_first_def_find,
|
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df_bb_regno_last_def_find, df_find_def, df_find_use,
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df_refs_chain_dump, df_regs_chain_dump, df_ref_debug,
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@ -548,8 +560,7 @@
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df_ref * with df_ref.
|
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(df_ref_record, df_uses_record, df_ref_create_structure): Added
|
||||
df_ref_class parameter.
|
||||
(df_scan_problem_data): Added new pools for different types of
|
||||
refs.
|
||||
(df_scan_problem_data): Added new pools for different types of refs.
|
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(df_scan_free_internal, df_scan_alloc, df_free_ref,
|
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df_ref_create_structure): Processed new ref pools.
|
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(df_scan_start_dump): Added counts of refs and insns.
|
||||
|
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@ -15366,9 +15366,9 @@
|
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(define_expand "ffs_cmove"
|
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[(set (match_dup 2) (const_int -1))
|
||||
(parallel [(set (reg:CCZ FLAGS_REG)
|
||||
(compare:CCZ (match_operand:SI 1 "register_operand" "")
|
||||
(compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "")
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "nonimmediate_operand" "")
|
||||
(set (match_operand:SI 0 "register_operand" "")
|
||||
(ctz:SI (match_dup 1)))])
|
||||
(set (match_dup 0) (if_then_else:SI
|
||||
(eq (reg:CCZ FLAGS_REG) (const_int 0))
|
||||
@ -15380,7 +15380,7 @@
|
||||
"operands[2] = gen_reg_rtx (SImode);")
|
||||
|
||||
(define_insn_and_split "*ffs_no_cmove"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
|
||||
(clobber (match_scratch:SI 2 "=&q"))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
@ -15416,9 +15416,9 @@
|
||||
(define_expand "ffsdi2"
|
||||
[(set (match_dup 2) (const_int -1))
|
||||
(parallel [(set (reg:CCZ FLAGS_REG)
|
||||
(compare:CCZ (match_operand:DI 1 "register_operand" "")
|
||||
(compare:CCZ (match_operand:DI 1 "nonimmediate_operand" "")
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "nonimmediate_operand" "")
|
||||
(set (match_operand:DI 0 "register_operand" "")
|
||||
(ctz:DI (match_dup 1)))])
|
||||
(set (match_dup 0) (if_then_else:DI
|
||||
(eq (reg:CCZ FLAGS_REG) (const_int 0))
|
||||
@ -20684,7 +20684,7 @@
|
||||
[(match_dup 0)
|
||||
(match_operand:SI 1 "memory_operand" "")]))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"optimize_insn_for_speed_p ()"
|
||||
"optimize_insn_for_speed_p () && ! TARGET_READ_MODIFY"
|
||||
[(set (match_dup 2) (match_dup 1))
|
||||
(parallel [(set (match_dup 0)
|
||||
(match_op_dup 3 [(match_dup 0) (match_dup 2)]))
|
||||
|
||||
@ -42,13 +42,13 @@
|
||||
* gfortran.dg/reshape_order_4.f90: Likewise.
|
||||
|
||||
2008-10-15 Jan Sjodin <jan.sjodin@amd.com>
|
||||
Harsha Jagasia <harsha.jagasia@amd.com>
|
||||
Harsha Jagasia <harsha.jagasia@amd.com>
|
||||
|
||||
PR tree-optimization/37485
|
||||
* gcc.dg/graphite/pr37485.c: New.
|
||||
|
||||
2008-10-15 Sebastian Pop <sebastian.pop@amd.com>
|
||||
Harsha Jagasia <harsha.jagasia@amd.com>
|
||||
Harsha Jagasia <harsha.jagasia@amd.com>
|
||||
|
||||
PR tree-optimization/37828
|
||||
* testsuite/gcc.dg/graphite/pr37828.c: New.
|
||||
@ -75,8 +75,8 @@
|
||||
|
||||
2008-10-14 Douglas Gregor <doug.gregor@gmail.com>
|
||||
|
||||
PR c++/37553
|
||||
* g++.dg/ext/alias-canon2.C: New.
|
||||
PR c++/37553
|
||||
* g++.dg/ext/alias-canon2.C: New.
|
||||
|
||||
2008-10-13 Jerry DeLisle <jvdelisle@gcc.gnu.org
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user