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target-insns.def (atomic_test_and_set): New targetm instruction pattern. 

gcc/
	* target-insns.def (atomic_test_and_set): New targetm instruction
	pattern.
	* optabs.c (maybe_emit_atomic_test_and_set): Use it instead of
	HAVE_*/gen_* interface.

From-SVN: r226325
This commit is contained in:
Richard Sandiford 2015-07-28 20:03:22 +00:00 committed by Richard Sandiford
parent 2a870875df
commit 3d00045080
3 changed files with 13 additions and 10 deletions
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7
gcc/ChangeLog
View File

@ -1,3 +1,10 @@
2015-07-28 Richard Sandiford <richard.sandiford@arm.com>
* target-insns.def (atomic_test_and_set): New targetm instruction
pattern.
* optabs.c (maybe_emit_atomic_test_and_set): Use it instead of
HAVE_*/gen_* interface.
2015-07-28 Richard Sandiford <richard.sandiford@arm.com>
* target-insns.def (can_extend, ptr_extend): New targetm instruction

15
gcc/optabs.c
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@ -7258,35 +7258,30 @@ maybe_emit_compare_and_swap_exchange_loop (rtx target, rtx mem, rtx val)
using the atomic_test_and_set instruction pattern. A boolean value
is returned from the operation, using TARGET if possible. */
#ifndef HAVE_atomic_test_and_set
#define HAVE_atomic_test_and_set 0
#define CODE_FOR_atomic_test_and_set CODE_FOR_nothing
#endif
static rtx
maybe_emit_atomic_test_and_set (rtx target, rtx mem, enum memmodel model)
{
machine_mode pat_bool_mode;
struct expand_operand ops[3];
if (!HAVE_atomic_test_and_set)
if (!targetm.have_atomic_test_and_set ())
return NULL_RTX;
/* While we always get QImode from __atomic_test_and_set, we get
other memory modes from __sync_lock_test_and_set. Note that we
use no endian adjustment here. This matches the 4.6 behavior
in the Sparc backend. */
gcc_checking_assert
(insn_data[CODE_FOR_atomic_test_and_set].operand[1].mode == QImode);
enum insn_code icode = targetm.code_for_atomic_test_and_set;
gcc_checking_assert (insn_data[icode].operand[1].mode == QImode);
if (GET_MODE (mem) != QImode)
mem = adjust_address_nv (mem, QImode, 0);
pat_bool_mode = insn_data[CODE_FOR_atomic_test_and_set].operand[0].mode;
pat_bool_mode = insn_data[icode].operand[0].mode;
create_output_operand (&ops[0], target, pat_bool_mode);
create_fixed_operand (&ops[1], mem);
create_integer_operand (&ops[2], model);
if (maybe_expand_insn (CODE_FOR_atomic_test_and_set, 3, ops))
if (maybe_expand_insn (icode, 3, ops))
return ops[0].value;
return NULL_RTX;
}

1
gcc/target-insns.def
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@ -31,6 +31,7 @@
Instructions should be documented in md.texi rather than here. */
DEF_TARGET_INSN (allocate_stack, (rtx x0, rtx x1))
DEF_TARGET_INSN (atomic_test_and_set, (rtx x0, rtx x1, rtx x2))
DEF_TARGET_INSN (builtin_longjmp, (rtx x0))
DEF_TARGET_INSN (builtin_setjmp_receiver, (rtx x0))
DEF_TARGET_INSN (builtin_setjmp_setup, (rtx x0))