mips.c (mips_split_64bit_move): Use gen_rtx_REG_offset rather than gen_lowpart to change a register from DImode...
gcc/ * config/mips/mips.c (mips_split_64bit_move): Use gen_rtx_REG_offset rather than gen_lowpart to change a register from DImode to DFmode. (mips_cannot_change_mode_class): Only allow FPRs to change mode if both FROM and TO are integer modes that are no bigger than 4 bytes. (mips_mode_ok_for_mov_fmt_p): New function. (mips_preferred_reload_class): Use it instead of FLOAT_MODE_P. (mips_secondary_reload_class): Tweak formatting and comments. Use reg_class_subset_p instead of direct comparisons with classes. Only allow direct FPR<->FPR moves for modes that satisfy mips_mode_ok_for_mov_fmt_p. Only allow loads and stores for 4- and 8-byte types. Handle reloads in which X is an FPR. * config/mips/mips.md (*movdi_gp32_fp64): Remove f<-f alternative. (*movdi_64bit): Likewise. (*movsi_internal): Likewise. (*movhi_internal): Likewise. (*movqi_internal): Likewise. From-SVN: r128894
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
a45db20b75
commit
3d30741b2b
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@ -1,3 +1,22 @@
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2007-09-30 Richard Sandiford <rsandifo@nildram.co.uk>
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* config/mips/mips.c (mips_split_64bit_move): Use gen_rtx_REG_offset
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rather than gen_lowpart to change a register from DImode to DFmode.
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(mips_cannot_change_mode_class): Only allow FPRs to change mode if
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both FROM and TO are integer modes that are no bigger than 4 bytes.
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(mips_mode_ok_for_mov_fmt_p): New function.
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(mips_preferred_reload_class): Use it instead of FLOAT_MODE_P.
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(mips_secondary_reload_class): Tweak formatting and comments.
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Use reg_class_subset_p instead of direct comparisons with
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classes. Only allow direct FPR<->FPR moves for modes that
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satisfy mips_mode_ok_for_mov_fmt_p. Only allow loads and stores
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for 4- and 8-byte types. Handle reloads in which X is an FPR.
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* config/mips/mips.md (*movdi_gp32_fp64): Remove f<-f alternative.
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(*movdi_64bit): Likewise.
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(*movsi_internal): Likewise.
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(*movhi_internal): Likewise.
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(*movqi_internal): Likewise.
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2007-09-30 Diego Novillo <dnovillo@google.com>
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PR 33593
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@ -3547,7 +3547,8 @@ mips_split_64bit_move (rtx dest, rtx src)
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/* Loading an FPR from memory or from GPRs. */
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if (ISA_HAS_MXHC1)
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{
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dest = gen_lowpart (DFmode, dest);
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if (GET_MODE (dest) != DFmode)
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dest = gen_rtx_REG_offset (dest, DFmode, REGNO (dest), 0);
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emit_insn (gen_load_df_low (dest, mips_subword (src, 0)));
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emit_insn (gen_mthc1 (dest, mips_subword (src, 1),
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copy_rtx (dest)));
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@ -3565,7 +3566,8 @@ mips_split_64bit_move (rtx dest, rtx src)
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/* Storing an FPR into memory or GPRs. */
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if (ISA_HAS_MXHC1)
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{
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src = gen_lowpart (DFmode, src);
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if (GET_MODE (src) != DFmode)
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src = gen_rtx_REG_offset (src, DFmode, REGNO (src), 0);
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mips_emit_move (mips_subword (dest, 0), mips_subword (src, 0));
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emit_insn (gen_mfhc1 (mips_subword (dest, 1), src));
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}
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@ -9314,44 +9316,38 @@ mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
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to mode TO. */
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bool
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mips_cannot_change_mode_class (enum machine_mode from,
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enum machine_mode to, enum reg_class class)
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mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
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enum machine_mode to ATTRIBUTE_UNUSED,
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enum reg_class class)
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{
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if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
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&& MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
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{
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if (TARGET_BIG_ENDIAN)
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{
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/* When a multi-word value is stored in paired floating-point
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registers, the first register always holds the low word.
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We therefore can't allow FPRs to change between single-word
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and multi-word modes. */
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if (MAX_FPRS_PER_FMT > 1 && reg_classes_intersect_p (FP_REGS, class))
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return true;
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}
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}
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/* There are several problems with changing the modes of values
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in floating-point registers:
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/* gcc assumes that each word of a multiword register can be accessed
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individually using SUBREGs. This is not true for floating-point
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registers if they are bigger than a word. */
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if (UNITS_PER_FPREG > UNITS_PER_WORD
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&& GET_MODE_SIZE (from) > UNITS_PER_WORD
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&& GET_MODE_SIZE (to) < UNITS_PER_FPREG
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&& reg_classes_intersect_p (FP_REGS, class))
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return true;
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- When a multi-word value is stored in paired floating-point
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registers, the first register always holds the low word.
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We therefore can't allow FPRs to change between single-word
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and multi-word modes on big-endian targets.
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/* Loading a 32-bit value into a 64-bit floating-point register
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will not sign-extend the value, despite what LOAD_EXTEND_OP says.
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We can't allow 64-bit float registers to change from SImode to
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to a wider mode. */
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if (TARGET_64BIT
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&& TARGET_FLOAT64
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&& from == SImode
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&& GET_MODE_SIZE (to) >= UNITS_PER_WORD
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&& reg_classes_intersect_p (FP_REGS, class))
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return true;
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- GCC assumes that each word of a multiword register can be accessed
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individually using SUBREGs. This is not true for floating-point
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registers if they are bigger than a word.
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return false;
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- Loading a 32-bit value into a 64-bit floating-point register
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will not sign-extend the value, despite what LOAD_EXTEND_OP says.
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We can't allow FPRs to change from SImode to to a wider mode on
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64-bit targets.
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- If the FPU has already interpreted a value in one format, we must
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not ask it to treat the value as having a different format.
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We therefore only allow changes between 4-byte and smaller integer
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values, all of which have the "W" format as far as the FPU is
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concerned. */
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return (reg_classes_intersect_p (FP_REGS, class)
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&& (GET_MODE_CLASS (from) != MODE_INT
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|| GET_MODE_CLASS (to) != MODE_INT
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|| GET_MODE_SIZE (from) > 4
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|| GET_MODE_SIZE (to) > 4));
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}
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/* Return true if X should not be moved directly into register $25.
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@ -9367,6 +9363,27 @@ mips_dangerous_for_la25_p (rtx x)
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&& mips_global_symbol_p (x));
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}
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/* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
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static bool
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mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
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{
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switch (mode)
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{
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case SFmode:
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return TARGET_HARD_FLOAT;
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case DFmode:
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return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
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case V2SFmode:
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return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
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default:
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return false;
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}
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}
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/* Implement PREFERRED_RELOAD_CLASS. */
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enum reg_class
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@ -9375,9 +9392,8 @@ mips_preferred_reload_class (rtx x, enum reg_class class)
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if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
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return LEA_REGS;
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if (TARGET_HARD_FLOAT
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&& FLOAT_MODE_P (GET_MODE (x))
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&& reg_class_subset_p (FP_REGS, class))
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if (reg_class_subset_p (FP_REGS, class)
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&& mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
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return FP_REGS;
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if (reg_class_subset_p (GR_REGS, class))
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@ -9399,110 +9415,81 @@ enum reg_class
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mips_secondary_reload_class (enum reg_class class,
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enum machine_mode mode, rtx x, int in_p)
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{
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enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
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int regno = -1;
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int gp_reg_p;
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if (REG_P (x)|| GET_CODE (x) == SUBREG)
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regno = true_regnum (x);
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gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
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int regno;
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/* If X is a constant that cannot be loaded into $25, it must be loaded
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into some other GPR. No other register class allows a direct move. */
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if (mips_dangerous_for_la25_p (x))
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return reg_class_subset_p (class, LEA_REGS) ? NO_REGS : LEA_REGS;
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regno = true_regnum (x);
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if (TARGET_MIPS16)
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{
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gr_regs = LEA_REGS;
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if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
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return gr_regs;
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/* In MIPS16 mode, every move must involve a member of M16_REGS. */
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if (!reg_class_subset_p (class, M16_REGS) && !M16_REG_P (regno))
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return M16_REGS;
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/* We can't really copy to HI or LO at all in MIPS16 mode. */
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if (in_p ? reg_classes_intersect_p (class, ACC_REGS) : ACC_REG_P (regno))
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return M16_REGS;
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return NO_REGS;
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}
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/* Copying from HI or LO to anywhere other than a general register
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requires a general register.
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This rule applies to both the original HI/LO pair and the new
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DSP accumulators. */
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/* Copying from accumulator registers to anywhere other than a general
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register requires a temporary general register. */
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if (reg_class_subset_p (class, ACC_REGS))
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{
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if (TARGET_MIPS16 && in_p)
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{
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/* We can't really copy to HI or LO at all in mips16 mode. */
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return M16_REGS;
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}
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return gp_reg_p ? NO_REGS : gr_regs;
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}
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return GP_REG_P (regno) ? NO_REGS : GR_REGS;
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if (ACC_REG_P (regno))
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{
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if (TARGET_MIPS16 && ! in_p)
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{
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/* We can't really copy to HI or LO at all in mips16 mode. */
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return M16_REGS;
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}
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return class == gr_regs ? NO_REGS : gr_regs;
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}
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return reg_class_subset_p (class, GR_REGS) ? NO_REGS : GR_REGS;
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/* We can only copy a value to a condition code register from a
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floating point register, and even then we require a scratch
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floating point register. We can only copy a value out of a
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condition code register into a general register. */
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if (class == ST_REGS)
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if (reg_class_subset_p (class, ST_REGS))
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{
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if (in_p)
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return FP_REGS;
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return gp_reg_p ? NO_REGS : gr_regs;
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return GP_REG_P (regno) ? NO_REGS : GR_REGS;
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}
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if (ST_REG_P (regno))
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{
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if (! in_p)
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if (!in_p)
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return FP_REGS;
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return class == gr_regs ? NO_REGS : gr_regs;
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return reg_class_subset_p (class, GR_REGS) ? NO_REGS : GR_REGS;
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}
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if (class == FP_REGS)
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if (reg_class_subset_p (class, FP_REGS))
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{
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if (MEM_P (x))
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{
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/* In this case we can use lwc1, swc1, ldc1 or sdc1. */
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return NO_REGS;
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}
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else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
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{
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/* We can use the l.s and l.d macros to load floating-point
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constants. ??? For l.s, we could probably get better
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code by returning GR_REGS here. */
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return NO_REGS;
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}
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else if (gp_reg_p || x == CONST0_RTX (mode))
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{
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/* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
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return NO_REGS;
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}
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else if (FP_REG_P (regno))
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{
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/* In this case we can use mov.s or mov.d. */
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return NO_REGS;
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}
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else
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{
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/* Otherwise, we need to reload through an integer register. */
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return gr_regs;
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}
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}
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if (MEM_P (x)
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&& (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
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/* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
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pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
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return NO_REGS;
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/* In mips16 mode, going between memory and anything but M16_REGS
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requires an M16_REG. */
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if (TARGET_MIPS16)
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{
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if (class != M16_REGS && class != M16_NA_REGS)
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if (GP_REG_P (regno) || x == CONST0_RTX (mode))
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/* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
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return NO_REGS;
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if (mips_mode_ok_for_mov_fmt_p (mode))
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{
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if (gp_reg_p)
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if (CONSTANT_P (x))
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/* We can force the constants to memory and use lwc1
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and ldc1. As above, we will use pairs of lwc1s if
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ldc1 is not supported. */
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return NO_REGS;
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return M16_REGS;
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}
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if (! gp_reg_p)
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{
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if (class == M16_REGS || class == M16_NA_REGS)
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if (FP_REG_P (regno))
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/* In this case we can use mov.fmt. */
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return NO_REGS;
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return M16_REGS;
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}
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/* Otherwise, we need to reload through an integer register. */
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return GR_REGS;
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}
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if (FP_REG_P (regno))
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return reg_class_subset_p (class, GR_REGS) ? NO_REGS : GR_REGS;
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return NO_REGS;
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}
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@ -3399,15 +3399,15 @@
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(set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
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(define_insn "*movdi_gp32_fp64"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*f,*d,*m")
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(match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*f,*J*d,*m,*f,*f"))]
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[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*d,*m")
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(match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*J*d,*m,*f,*f"))]
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"!TARGET_64BIT && TARGET_FLOAT64 && !TARGET_MIPS16
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&& (register_operand (operands[0], DImode)
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|| reg_or_0_operand (operands[1], DImode))"
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{ return mips_output_move (operands[0], operands[1]); }
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[(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,fmove,mtc,fpload,mfc,fpstore")
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[(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
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(set_attr "mode" "DI")
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(set_attr "length" "8,16,*,*,8,8,4,8,*,8,*")])
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(set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
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(define_insn "*movdi_32bit_mips16"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
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@ -3421,15 +3421,15 @@
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(set_attr "length" "8,8,8,8,12,*,*,8")])
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(define_insn "*movdi_64bit"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m")
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(match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))]
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[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m")
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(match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))]
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"TARGET_64BIT && !TARGET_MIPS16
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&& (register_operand (operands[0], DImode)
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|| reg_or_0_operand (operands[1], DImode))"
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{ return mips_output_move (operands[0], operands[1]); }
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[(set_attr "type" "move,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mthilo,mtc,load,mfc,store")
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[(set_attr "type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mtc,load,mfc,store")
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(set_attr "mode" "DI")
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(set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,8,*,8,*")])
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(set_attr "length" "4,*,*,*,*,4,*,4,*,4,8,*,8,*")])
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(define_insn "*movdi_64bit_mips16"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m")
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@ -3518,15 +3518,15 @@
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;; in FP registers (off by default, use -mdebugh to enable).
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(define_insn "*movsi_internal"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
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(match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))]
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
|
||||
(match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))]
|
||||
"!TARGET_MIPS16
|
||||
&& (register_operand (operands[0], SImode)
|
||||
|| reg_or_0_operand (operands[1], SImode))"
|
||||
{ return mips_output_move (operands[0], operands[1]); }
|
||||
[(set_attr "type" "move,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,load,mfc,store")
|
||||
[(set_attr "type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,load,mfc,store")
|
||||
(set_attr "mode" "SI")
|
||||
(set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,4,*,4,*")])
|
||||
(set_attr "length" "4,*,*,*,*,4,*,4,*,4,4,4,4,4,*,4,*")])
|
||||
|
||||
(define_insn "*movsi_mips16"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m")
|
||||
|
|
@ -3727,8 +3727,8 @@
|
|||
})
|
||||
|
||||
(define_insn "*movhi_internal"
|
||||
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
|
||||
(match_operand:HI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
|
||||
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*x")
|
||||
(match_operand:HI 1 "move_operand" "d,I,m,dJ,*f,*d,*d"))]
|
||||
"!TARGET_MIPS16
|
||||
&& (register_operand (operands[0], HImode)
|
||||
|| reg_or_0_operand (operands[1], HImode))"
|
||||
|
|
@ -3739,11 +3739,10 @@
|
|||
sh\t%z1,%0
|
||||
mfc1\t%0,%1
|
||||
mtc1\t%1,%0
|
||||
mov.s\t%0,%1
|
||||
mt%0\t%1"
|
||||
[(set_attr "type" "move,arith,load,store,mfc,mtc,fmove,mthilo")
|
||||
[(set_attr "type" "move,arith,load,store,mfc,mtc,mthilo")
|
||||
(set_attr "mode" "HI")
|
||||
(set_attr "length" "4,4,*,*,4,4,4,4")])
|
||||
(set_attr "length" "4,4,*,*,4,4,4")])
|
||||
|
||||
(define_insn "*movhi_mips16"
|
||||
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
|
||||
|
|
@ -3834,8 +3833,8 @@
|
|||
})
|
||||
|
||||
(define_insn "*movqi_internal"
|
||||
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
|
||||
(match_operand:QI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
|
||||
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*x")
|
||||
(match_operand:QI 1 "move_operand" "d,I,m,dJ,*f,*d,*d"))]
|
||||
"!TARGET_MIPS16
|
||||
&& (register_operand (operands[0], QImode)
|
||||
|| reg_or_0_operand (operands[1], QImode))"
|
||||
|
|
@ -3846,11 +3845,10 @@
|
|||
sb\t%z1,%0
|
||||
mfc1\t%0,%1
|
||||
mtc1\t%1,%0
|
||||
mov.s\t%0,%1
|
||||
mt%0\t%1"
|
||||
[(set_attr "type" "move,arith,load,store,mfc,mtc,fmove,mthilo")
|
||||
[(set_attr "type" "move,arith,load,store,mfc,mtc,mthilo")
|
||||
(set_attr "mode" "QI")
|
||||
(set_attr "length" "4,4,*,*,4,4,4,4")])
|
||||
(set_attr "length" "4,4,*,*,4,4,4")])
|
||||
|
||||
(define_insn "*movqi_mips16"
|
||||
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
|
||||
|
|
|
|||
Loading…
Reference in New Issue