re PR rtl-optimization/13260 (Incorrect optimisation of loop termination condition)
PR optimization/13260 * sh-protos.h (sh_expand_t_scc): Declare. * sh.h (PREDICATE_CODES): Add cmpsi_operand. * sh.c (cmpsi_operand, sh_expand_t_scc): New functions. * sh.md (cmpsi): Use cmpsi_operand. If T_REG is compared to something that is not a CONST_INT, copy it into a pseudo register. (subc): Fix description of new T value. (slt, sgt, sge, sgtu): Don't clobber T after rtl generation is over. (sltu, sleu, sgeu): Likewise. (seq, sne): Likewise. Use sh_expand_t_scc. From-SVN: r74294
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@ -1,3 +1,16 @@
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2003-12-04 J"orn Rennecke <joern.rennecke@superh.com>
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PR optimization/13260
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* sh-protos.h (sh_expand_t_scc): Declare.
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* sh.h (PREDICATE_CODES): Add cmpsi_operand.
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* sh.c (cmpsi_operand, sh_expand_t_scc): New functions.
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* sh.md (cmpsi): Use cmpsi_operand. If T_REG is compared to
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something that is not a CONST_INT, copy it into a pseudo register.
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(subc): Fix description of new T value.
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(slt, sgt, sge, sgtu): Don't clobber T after rtl generation is over.
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(sltu, sleu, sgeu): Likewise.
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(seq, sne): Likewise. Use sh_expand_t_scc.
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2003-12-04 Nathanael Nerode <neroden@gcc.gnu.org>
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* configure.in: Generalize the CONFIG_HEADERS pattern under which
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@ -97,6 +97,7 @@ extern int sh_insn_length_adjustment (rtx);
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extern int sh_can_redirect_branch (rtx, rtx);
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extern void sh_expand_unop_v2sf (enum rtx_code, rtx, rtx);
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extern void sh_expand_binop_v2sf (enum rtx_code, rtx, rtx, rtx);
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extern int sh_expand_t_scc (enum rtx_code code, rtx target);
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#ifdef TREE_CODE
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extern void sh_va_start (tree, rtx);
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extern rtx sh_va_arg (tree, tree);
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@ -8898,6 +8898,15 @@ sh_register_operand (rtx op, enum machine_mode mode)
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return register_operand (op, mode);
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}
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int
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cmpsi_operand (rtx op, enum machine_mode mode)
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{
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if (GET_CODE (op) == REG && REGNO (op) == T_REG
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&& GET_MODE (op) == SImode)
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return 1;
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return arith_operand (op, mode);
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}
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static rtx emit_load_ptr (rtx, rtx);
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static rtx
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@ -9129,4 +9138,33 @@ sh_get_pr_initial_val (void)
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return val;
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}
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int
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sh_expand_t_scc (enum rtx_code code, rtx target)
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{
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rtx result = target;
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HOST_WIDE_INT val;
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if (GET_CODE (sh_compare_op0) != REG || REGNO (sh_compare_op0) != T_REG
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|| GET_CODE (sh_compare_op1) != CONST_INT)
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return 0;
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if (GET_CODE (result) != REG)
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result = gen_reg_rtx (SImode);
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val = INTVAL (sh_compare_op1);
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if ((code == EQ && val == 1) || (code == NE && val == 0))
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emit_insn (gen_movt (result));
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else if ((code == EQ && val == 0) || (code == NE && val == 1))
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{
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emit_insn (gen_rtx_CLOBBER (VOIDmode, result));
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emit_insn (gen_subc (result, result, result));
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emit_insn (gen_addsi3 (result, result, GEN_INT (1)));
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}
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else if (code == EQ || code == NE)
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emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
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else
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return 0;
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if (result != target)
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emit_move_insn (target, result);
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return 1;
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}
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#include "gt-sh.h"
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@ -3145,6 +3145,7 @@ extern int rtx_equal_function_value_matters;
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{"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_VECTOR}}, \
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{"binary_float_operator", {PLUS, MINUS, MULT, DIV}}, \
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{"binary_logical_operator", {AND, IOR, XOR}}, \
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{"cmpsi_operand", {SUBREG, REG, CONST_INT}}, \
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{"commutative_float_operator", {PLUS, MULT}}, \
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{"equality_comparison_operator", {EQ,NE}}, \
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{"extend_reg_operand", {SUBREG, REG, TRUNCATE}}, \
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@ -705,11 +705,14 @@
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(define_expand "cmpsi"
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[(set (reg:SI T_REG)
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(compare (match_operand:SI 0 "arith_operand" "")
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(compare (match_operand:SI 0 "cmpsi_operand" "")
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(match_operand:SI 1 "arith_operand" "")))]
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"TARGET_SH1"
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"
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{
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if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == T_REG
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&& GET_CODE (operands[1]) != CONST_INT)
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operands[0] = copy_to_mode_reg (SImode, operands[0]);
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sh_compare_op0 = operands[0];
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sh_compare_op1 = operands[1];
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DONE;
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@ -1167,7 +1170,9 @@
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(match_operand:SI 2 "arith_reg_operand" "r"))
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(reg:SI T_REG)))
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(set (reg:SI T_REG)
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(gtu:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
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(gtu:SI (minus:SI (minus:SI (match_dup 1) (match_dup 2))
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(reg:SI T_REG))
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(match_dup 1)))]
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"TARGET_SH1"
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"subc %2,%0"
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[(set_attr "type" "arith")])
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@ -7446,6 +7451,10 @@ mov.l\\t1f,r0\\n\\
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}
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DONE;
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}
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if (sh_expand_t_scc (EQ, operands[0]))
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DONE;
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if (! rtx_equal_function_value_matters)
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FAIL;
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operands[1] = prepare_scc_operands (EQ);
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}")
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@ -7492,6 +7501,8 @@ mov.l\\t1f,r0\\n\\
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}
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DONE;
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}
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if (! rtx_equal_function_value_matters)
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FAIL;
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operands[1] = prepare_scc_operands (LT);
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}")
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@ -7594,6 +7605,8 @@ mov.l\\t1f,r0\\n\\
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}
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DONE;
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}
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if (! rtx_equal_function_value_matters)
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FAIL;
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operands[1] = prepare_scc_operands (GT);
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}")
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@ -7646,6 +7659,8 @@ mov.l\\t1f,r0\\n\\
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DONE;
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}
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if (! rtx_equal_function_value_matters)
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FAIL;
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if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
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{
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if (TARGET_IEEE)
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@ -7685,6 +7700,8 @@ mov.l\\t1f,r0\\n\\
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sh_compare_op0, sh_compare_op1));
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DONE;
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}
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if (! rtx_equal_function_value_matters)
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FAIL;
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operands[1] = prepare_scc_operands (GTU);
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}")
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@ -7709,6 +7726,8 @@ mov.l\\t1f,r0\\n\\
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sh_compare_op1, sh_compare_op0));
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DONE;
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}
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if (! rtx_equal_function_value_matters)
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FAIL;
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operands[1] = prepare_scc_operands (LTU);
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}")
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@ -7738,6 +7757,8 @@ mov.l\\t1f,r0\\n\\
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DONE;
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}
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if (! rtx_equal_function_value_matters)
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FAIL;
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operands[1] = prepare_scc_operands (LEU);
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}")
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@ -7768,6 +7789,8 @@ mov.l\\t1f,r0\\n\\
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DONE;
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}
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if (! rtx_equal_function_value_matters)
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FAIL;
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operands[1] = prepare_scc_operands (GEU);
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}")
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DONE;
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}
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operands[1] = prepare_scc_operands (EQ);
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operands[2] = gen_reg_rtx (SImode);
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if (sh_expand_t_scc (NE, operands[0]))
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DONE;
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if (! rtx_equal_function_value_matters)
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FAIL;
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operands[1] = prepare_scc_operands (EQ);
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operands[2] = gen_reg_rtx (SImode);
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}")
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(define_expand "sunordered"
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