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[AArch64] Make <perm_insn> the complete mnemonic

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The Advanced SIMD and SVE permute patterns both split the permute
operation into a base name and a hilo suffix.  That works well, but it
means that for "@" patterns, we need to pass the permute code twice,
once for the base name and once for the suffix.

Having a unified name avoids that and also makes the definitions
slightly simpler.

2019-08-13  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/iterators.md (perm_insn): Include the "1"/"2" suffix.
	(perm_hilo): Remove UNSPEC_ZIP*, UNSEPC_TRN* and UNSPEC_UZP*.
	* config/aarch64/aarch64-simd.md
	(aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>): Rename to..
	(aarch64_<PERMUTE:perm_insn><mode>): ...this and remove perm_hilo
	from the asm template.
	* config/aarch64/aarch64-sve.md
	(aarch64_<perm_insn><perm_hilo><PRED_ALL:mode>): Rename to..
	(aarch64_<perm_insn><PRED_ALL:mode>): ...this and remove perm_hilo
	from the asm template.
	(aarch64_<perm_insn><perm_hilo><SVE_ALL:mode>): Rename to..
	(aarch64_<perm_insn><SVE_ALL:mode>): ...this and remove perm_hilo
	from the asm template.
	* config/aarch64/aarch64-simd-builtins.def: Update comment.

From-SVN: r274366
This commit is contained in:
Richard Sandiford 2019-08-13 09:38:39 +00:00 committed by Richard Sandiford
parent f77d27597d
commit 3e2751ce55
5 changed files with 28 additions and 14 deletions
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17
gcc/ChangeLog
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@ -1,3 +1,20 @@
2019-08-13 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/iterators.md (perm_insn): Include the "1"/"2" suffix.
(perm_hilo): Remove UNSPEC_ZIP*, UNSEPC_TRN* and UNSPEC_UZP*.
* config/aarch64/aarch64-simd.md
(aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>): Rename to..
(aarch64_<PERMUTE:perm_insn><mode>): ...this and remove perm_hilo
from the asm template.
* config/aarch64/aarch64-sve.md
(aarch64_<perm_insn><perm_hilo><PRED_ALL:mode>): Rename to..
(aarch64_<perm_insn><PRED_ALL:mode>): ...this and remove perm_hilo
from the asm template.
(aarch64_<perm_insn><perm_hilo><SVE_ALL:mode>): Rename to..
(aarch64_<perm_insn><SVE_ALL:mode>): ...this and remove perm_hilo
from the asm template.
* config/aarch64/aarch64-simd-builtins.def: Update comment.
2019-08-13 Martin Liska <mliska@suse.cz> 2019-08-13 Martin Liska <mliska@suse.cz>
* value-prof.c (gimple_ic_transform): Add new line. * value-prof.c (gimple_ic_transform): Add new line.

2
gcc/config/aarch64/aarch64-simd-builtins.def
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@ -424,7 +424,7 @@
BUILTIN_VB (UNOP, rbit, 0) BUILTIN_VB (UNOP, rbit, 0)
/* Implemented by /* Implemented by
aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>. */ aarch64_<PERMUTE:perm_insn><mode>. */
BUILTIN_VALL (BINOP, zip1, 0) BUILTIN_VALL (BINOP, zip1, 0)
BUILTIN_VALL (BINOP, zip2, 0) BUILTIN_VALL (BINOP, zip2, 0)
BUILTIN_VALL (BINOP, uzp1, 0) BUILTIN_VALL (BINOP, uzp1, 0)

4
gcc/config/aarch64/aarch64-simd.md
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@ -5781,13 +5781,13 @@
;; This instruction's pattern is generated directly by ;; This instruction's pattern is generated directly by
;; aarch64_expand_vec_perm_const, so any changes to the pattern would ;; aarch64_expand_vec_perm_const, so any changes to the pattern would
;; need corresponding changes there. ;; need corresponding changes there.
(define_insn "aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>" (define_insn "aarch64_<PERMUTE:perm_insn><mode>"
[(set (match_operand:VALL_F16 0 "register_operand" "=w") [(set (match_operand:VALL_F16 0 "register_operand" "=w")
(unspec:VALL_F16 [(match_operand:VALL_F16 1 "register_operand" "w") (unspec:VALL_F16 [(match_operand:VALL_F16 1 "register_operand" "w")
(match_operand:VALL_F16 2 "register_operand" "w")] (match_operand:VALL_F16 2 "register_operand" "w")]
PERMUTE))] PERMUTE))]
"TARGET_SIMD" "TARGET_SIMD"
"<PERMUTE:perm_insn><PERMUTE:perm_hilo>\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>" "<PERMUTE:perm_insn>\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "type" "neon_permute<q>")] [(set_attr "type" "neon_permute<q>")]
) )

8
gcc/config/aarch64/aarch64-sve.md
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@ -3356,13 +3356,13 @@
;; Permutes that take half the elements from one vector and half the ;; Permutes that take half the elements from one vector and half the
;; elements from the other. ;; elements from the other.
(define_insn "aarch64_sve_<perm_insn><perm_hilo><mode>" (define_insn "aarch64_sve_<perm_insn><mode>"
[(set (match_operand:SVE_ALL 0 "register_operand" "=w") [(set (match_operand:SVE_ALL 0 "register_operand" "=w")
(unspec:SVE_ALL [(match_operand:SVE_ALL 1 "register_operand" "w") (unspec:SVE_ALL [(match_operand:SVE_ALL 1 "register_operand" "w")
(match_operand:SVE_ALL 2 "register_operand" "w")] (match_operand:SVE_ALL 2 "register_operand" "w")]
PERMUTE))] PERMUTE))]
"TARGET_SVE" "TARGET_SVE"
"<perm_insn><perm_hilo>\t%0.<Vetype>, %1.<Vetype>, %2.<Vetype>" "<perm_insn>\t%0.<Vetype>, %1.<Vetype>, %2.<Vetype>"
) )
;; Concatenate two vectors and extract a subvector. Note that the ;; Concatenate two vectors and extract a subvector. Note that the
@ -3395,13 +3395,13 @@
;; Permutes that take half the elements from one vector and half the ;; Permutes that take half the elements from one vector and half the
;; elements from the other. ;; elements from the other.
(define_insn "*aarch64_sve_<perm_insn><perm_hilo><mode>" (define_insn "*aarch64_sve_<perm_insn><mode>"
[(set (match_operand:PRED_ALL 0 "register_operand" "=Upa") [(set (match_operand:PRED_ALL 0 "register_operand" "=Upa")
(unspec:PRED_ALL [(match_operand:PRED_ALL 1 "register_operand" "Upa") (unspec:PRED_ALL [(match_operand:PRED_ALL 1 "register_operand" "Upa")
(match_operand:PRED_ALL 2 "register_operand" "Upa")] (match_operand:PRED_ALL 2 "register_operand" "Upa")]
PERMUTE))] PERMUTE))]
"TARGET_SVE" "TARGET_SVE"
"<perm_insn><perm_hilo>\t%0.<Vetype>, %1.<Vetype>, %2.<Vetype>" "<perm_insn>\t%0.<Vetype>, %1.<Vetype>, %2.<Vetype>"
) )
;; ========================================================================= ;; =========================================================================

11
gcc/config/aarch64/iterators.md
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@ -1888,18 +1888,15 @@
(UNSPEC_AUTIA1716 "12") (UNSPEC_AUTIA1716 "12")
(UNSPEC_AUTIB1716 "14")]) (UNSPEC_AUTIB1716 "14")])
(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip") (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip1") (UNSPEC_ZIP2 "zip2")
(UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn") (UNSPEC_TRN1 "trn1") (UNSPEC_TRN2 "trn2")
(UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")]) (UNSPEC_UZP1 "uzp1") (UNSPEC_UZP2 "uzp2")])
; op code for REV instructions (size within which elements are reversed). ; op code for REV instructions (size within which elements are reversed).
(define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32") (define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
(UNSPEC_REV16 "16")]) (UNSPEC_REV16 "16")])
(define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2") (define_int_attr perm_hilo [(UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi")
(UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2")
(UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")
(UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi")
(UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")]) (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")])
;; Return true if the associated optab refers to the high-numbered lanes, ;; Return true if the associated optab refers to the high-numbered lanes,