md.texi (Blackfin family constraints): Document PA and PB.
* doc/md.texi (Blackfin family constraints): Document PA and PB. * config/bfin/bfin.h (CONST_OK_FOR_P): Handle PA and PB. (MACFLAGS_MATCH_P): New macro. * config/bfin/bfin.c (print_operand): Handle MACFLAG_IS_M. (bfin_secondary_reload): Treat EVEN_AREGS and ODD_AREGS like AREGS. * config/bfin/bfin.md (MACFLAG_IS_M): New constant. Renumber some of the other MACFLAG constants. (sum_of_accumulators, lshrpdi3, ashrpdi3): New patterns. (flag_machi): Tighten constraints. Renumber some of the operands. (flag_machi_acconly): Tighten constraints. Correct operand numbers in output template. (flag_machi_parts_acconly): New pattern. (flag_macinithi): Tighten constraints. Allow any accumulator to be used. (flag_macinit1hi): Tighten constraints. (flag_mul_macv2hi_parts_acconly): New pattern. From-SVN: r123745
This commit is contained in:
Bernd Schmidt
Bernd Schmidt
parent
f4de8ba686
commit
3efd5670ca
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@ -1,3 +1,22 @@
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2007-04-12 Bernd Schmidt <bernd.schmidt@analog.com>
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* doc/md.texi (Blackfin family constraints): Document PA and PB.
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* config/bfin/bfin.h (CONST_OK_FOR_P): Handle PA and PB.
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(MACFLAGS_MATCH_P): New macro.
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* config/bfin/bfin.c (print_operand): Handle MACFLAG_IS_M.
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(bfin_secondary_reload): Treat EVEN_AREGS and ODD_AREGS like AREGS.
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* config/bfin/bfin.md (MACFLAG_IS_M): New constant. Renumber some of
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the other MACFLAG constants.
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(sum_of_accumulators, lshrpdi3, ashrpdi3): New patterns.
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(flag_machi): Tighten constraints. Renumber some of the operands.
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(flag_machi_acconly): Tighten constraints. Correct operand numbers in
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output template.
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(flag_machi_parts_acconly): New pattern.
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(flag_macinithi): Tighten constraints. Allow any accumulator to be
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used.
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(flag_macinit1hi): Tighten constraints.
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(flag_mul_macv2hi_parts_acconly): New pattern.
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2007-04-12 Richard Sandiford <richard@codesourcery.com>
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* config.gcc (*-*-vxworks*): Don't add to tm_files in this stanza.
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@ -1356,6 +1356,9 @@ print_operand (FILE *file, rtx x, char code)
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case MACFLAG_M:
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fputs ("(M)", file);
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break;
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case MACFLAG_IS_M:
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fputs ("(IS,M)", file);
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break;
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case MACFLAG_ISS2:
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fputs ("(ISS2)", file);
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break;
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@ -2014,10 +2017,12 @@ bfin_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x, enum reg_class class,
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/* Data can usually be moved freely between registers of most classes.
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AREGS are an exception; they can only move to or from another register
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in AREGS or one in DREGS. They can also be assigned the constant 0. */
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if (x_class == AREGS)
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return class == DREGS || class == AREGS ? NO_REGS : DREGS;
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if (x_class == AREGS || x_class == EVEN_AREGS || x_class == ODD_AREGS)
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return (class == DREGS || class == AREGS || class == EVEN_AREGS
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|| class == ODD_AREGS
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? NO_REGS : DREGS);
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if (class == AREGS)
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if (class == AREGS || class == EVEN_AREGS || class == ODD_AREGS)
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{
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if (x != const0_rtx && x_class != DREGS)
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return DREGS;
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@ -1084,6 +1084,8 @@ do { \
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: (STR)[1] == '2' ? (VALUE) == 2 \
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: (STR)[1] == '3' ? (VALUE) == 3 \
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: (STR)[1] == '4' ? (VALUE) == 4 \
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: (STR)[1] == 'A' ? (VALUE) != MACFLAG_M && (VALUE) != MACFLAG_IS_M \
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: (STR)[1] == 'B' ? (VALUE) == MACFLAG_M || (VALUE) == MACFLAG_IS_M \
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: 0)
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#define CONST_OK_FOR_K(VALUE, STR) \
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@ -1143,6 +1145,17 @@ do { \
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#define EXTRA_CONSTRAINT(VALUE, D) \
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((D) == 'Q' ? GET_CODE (VALUE) == SYMBOL_REF : 0)
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/* Evaluates to true if A and B are mac flags that can be used
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together in a single multiply insn. That is the case if they are
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both the same flag not involving M, or if one is a combination of
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the other with M. */
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#define MACFLAGS_MATCH_P(A, B) \
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((A) == (B) \
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|| ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \
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|| ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \
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|| ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \
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|| ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS))
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/* Switch into a generic section. */
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#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
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@ -154,9 +154,10 @@
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(MACFLAG_IU 5)
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(MACFLAG_W32 6)
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(MACFLAG_M 7)
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(MACFLAG_S2RND 8)
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(MACFLAG_ISS2 9)
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(MACFLAG_IH 10)])
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(MACFLAG_IS_M 8)
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(MACFLAG_S2RND 9)
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(MACFLAG_ISS2 10)
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(MACFLAG_IH 11)])
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(define_attr "type"
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"move,movcc,mvi,mcld,mcst,dsp32,mult,alu0,shft,brcc,br,call,misc,sync,compare,dummy"
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@ -1226,6 +1227,19 @@
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"%0 = %1 - %2 (S)%!"
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[(set_attr "type" "dsp32")])
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;; Accumulator addition
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(define_insn "sum_of_accumulators"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(ss_truncate:SI
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(ss_plus:PDI (match_operand:PDI 2 "register_operand" "1")
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(match_operand:PDI 3 "register_operand" "B"))))
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(set (match_operand:PDI 1 "register_operand" "=A")
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(ss_plus:PDI (match_dup 2) (match_dup 3)))]
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""
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"%0 = (A0 += A1)%!"
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[(set_attr "type" "dsp32")])
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;; Bit test instructions
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(define_insn "*not_bittst"
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@ -1643,6 +1657,22 @@
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%0 = %1 >> %2;"
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[(set_attr "type" "shft,dsp32,shft")])
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(define_insn "lshrpdi3"
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[(set (match_operand:PDI 0 "register_operand" "=e")
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(lshiftrt:PDI (match_operand:PDI 1 "register_operand" "0")
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(match_operand:SI 2 "nonmemory_operand" "Ku5")))]
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""
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"%0 = %1 >> %2%!"
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[(set_attr "type" "dsp32")])
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(define_insn "ashrpdi3"
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[(set (match_operand:PDI 0 "register_operand" "=e")
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(ashiftrt:PDI (match_operand:PDI 1 "register_operand" "0")
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(match_operand:SI 2 "nonmemory_operand" "Ku5")))]
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""
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"%0 = %1 >>> %2%!"
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[(set_attr "type" "dsp32")])
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;; A pattern to reload the equivalent of
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;; (set (Dreg) (plus (FP) (large_constant)))
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;; or
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@ -3031,52 +3061,83 @@
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}
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[(set_attr "type" "dsp32")])
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;; Three alternatives here to cover all possible allocations:
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;; 0. mac flag is usable only for accumulator 1 - use A1 and odd DREG
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;; 1. mac flag is usable for accumulator 0 - use A0 and even DREG
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;; 2. mac flag is usable in any accumulator - use A1 and odd DREG
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;; Other patterns which don't have a DREG destination can collapse cases
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;; 1 and 2 into one.
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(define_insn "flag_machi"
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[(set (match_operand:HI 0 "register_operand" "=d")
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(unspec:HI [(match_operand:HI 1 "register_operand" "d")
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(match_operand:HI 2 "register_operand" "d")
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(match_operand 3 "register_operand" "A")
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(match_operand 4 "const01_operand" "P0P1")
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(match_operand 5 "const_int_operand" "n")]
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[(set (match_operand:HI 0 "register_operand" "=W,D,W")
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(unspec:HI [(match_operand:HI 2 "register_operand" "d,d,d")
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(match_operand:HI 3 "register_operand" "d,d,d")
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(match_operand 4 "register_operand" "1,1,1")
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(match_operand 5 "const01_operand" "P0P1,P0P1,P0P1")
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(match_operand 6 "const_int_operand" "PB,PA,PA")]
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UNSPEC_MAC_WITH_FLAG))
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(set (match_operand:PDI 6 "register_operand" "=A")
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(set (match_operand:PDI 1 "register_operand" "=B,A,B")
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(unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3)
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(match_dup 4) (match_dup 5)]
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UNSPEC_MAC_WITH_FLAG))]
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""
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"%h0 = (A0 %b4 %h1 * %h2) %M6%!"
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"%h0 = (%1 %b5 %h2 * %h3) %M6%!"
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[(set_attr "type" "dsp32")])
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(define_insn "flag_machi_acconly"
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[(set (match_operand:PDI 0 "register_operand" "=e")
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(unspec:PDI [(match_operand:HI 1 "register_operand" "d")
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(match_operand:HI 2 "register_operand" "d")
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(match_operand 3 "register_operand" "A")
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(match_operand 4 "const01_operand" "P0P1")
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(match_operand 5 "const_int_operand" "n")]
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[(set (match_operand:PDI 0 "register_operand" "=B,e")
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(unspec:PDI [(match_operand:HI 1 "register_operand" "d,d")
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(match_operand:HI 2 "register_operand" "d,d")
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(match_operand 3 "register_operand" "0,0")
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(match_operand 4 "const01_operand" "P0P1,P0P1")
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(match_operand 5 "const_int_operand" "PB,PA")]
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UNSPEC_MAC_WITH_FLAG))]
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""
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"%0 %b4 %h1 * %h2 %M6%!"
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"%0 %b4 %h1 * %h2 %M5%!"
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[(set_attr "type" "dsp32")])
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(define_insn "flag_machi_parts_acconly"
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[(set (match_operand:PDI 0 "register_operand" "=B,e")
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(unspec:PDI [(vec_select:HI
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(match_operand:V2HI 1 "register_operand" "d,d")
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(parallel [(match_operand 3 "const01_operand" "P0P1,P0P1")]))
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(vec_select:HI
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(match_operand:V2HI 2 "register_operand" "d,d")
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(parallel [(match_operand 4 "const01_operand" "P0P1,P0P1")]))
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(match_operand:PDI 5 "register_operand" "0,0")
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(match_operand 6 "const01_operand" "P0P1,P0P1")
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(match_operand 7 "const_int_operand" "PB,PA")]
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UNSPEC_MAC_WITH_FLAG))]
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""
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{
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const char *templates[] = {
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"%0 %b6 %h1 * %h2 %M7%!",
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"%0 %b6 %d1 * %h2 %M7%!",
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"%0 %b6 %h1 * %d2 %M7%!",
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"%0 %b6 %d1 * %d2 %M7%!"
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};
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int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
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return templates[alt];
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}
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[(set_attr "type" "dsp32")])
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(define_insn "flag_macinithi"
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[(set (match_operand:HI 0 "register_operand" "=d")
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(unspec:HI [(match_operand:HI 1 "register_operand" "d")
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(match_operand:HI 2 "register_operand" "d")
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(match_operand 3 "const_int_operand" "n")]
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[(set (match_operand:HI 0 "register_operand" "=W,D,W")
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(unspec:HI [(match_operand:HI 1 "register_operand" "d,d,d")
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(match_operand:HI 2 "register_operand" "d,d,d")
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(match_operand 3 "const_int_operand" "PB,PA,PA")]
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UNSPEC_MAC_WITH_FLAG))
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(set (match_operand:PDI 4 "register_operand" "=A")
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(set (match_operand:PDI 4 "register_operand" "=B,A,B")
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(unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3)]
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UNSPEC_MAC_WITH_FLAG))]
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""
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"%h0 = (A0 = %h1 * %h2) %M3%!"
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"%h0 = (%4 = %h1 * %h2) %M3%!"
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[(set_attr "type" "dsp32")])
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(define_insn "flag_macinit1hi"
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[(set (match_operand:PDI 0 "register_operand" "=e")
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(unspec:PDI [(match_operand:HI 1 "register_operand" "d")
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(match_operand:HI 2 "register_operand" "d")
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(match_operand 3 "const_int_operand" "n")]
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[(set (match_operand:PDI 0 "register_operand" "=B,e")
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(unspec:PDI [(match_operand:HI 1 "register_operand" "d,d")
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(match_operand:HI 2 "register_operand" "d,d")
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(match_operand 3 "const_int_operand" "PB,PA")]
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UNSPEC_MAC_WITH_FLAG))]
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""
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"%0 = %h1 * %h2 %M3%!"
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@ -3338,6 +3399,63 @@
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}
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[(set_attr "type" "dsp32")])
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;; A mixture of multiply and multiply-accumulate for when we only want to
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;; initialize one part.
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(define_insn "flag_mul_macv2hi_parts_acconly"
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[(set (match_operand:PDI 0 "register_operand" "=B,e,e")
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(unspec:PDI [(vec_select:HI
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(match_operand:V2HI 2 "register_operand" "d,d,d")
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(parallel [(match_operand 4 "const01_operand" "P0P1,P0P1,P0P1")]))
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(vec_select:HI
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(match_operand:V2HI 3 "register_operand" "d,d,d")
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(parallel [(match_operand 6 "const01_operand" "P0P1,P0P1,P0P1")]))
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(match_operand 10 "const_int_operand" "PB,PA,PA")]
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UNSPEC_MUL_WITH_FLAG))
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(set (match_operand:PDI 1 "register_operand" "=B,e,e")
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(unspec:PDI [(vec_select:HI
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(match_dup 2)
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(parallel [(match_operand 5 "const01_operand" "P0P1,P0P1,P0P1")]))
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(vec_select:HI
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(match_dup 3)
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(parallel [(match_operand 7 "const01_operand" "P0P1,P0P1,P0P1")]))
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(match_operand:PDI 8 "register_operand" "1,1,1")
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(match_operand 9 "const01_operand" "P0P1,P0P1,P0P1")
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(match_operand 11 "const_int_operand" "PA,PB,PA")]
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UNSPEC_MAC_WITH_FLAG))]
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"MACFLAGS_MATCH_P (INTVAL (operands[10]), INTVAL (operands[11]))"
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{
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rtx xops[6];
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const char *templates[] = {
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"%0 = %h2 * %h3, %1 %b4 %h2 * %h3 %M5%!",
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"%0 = %d2 * %h3, %1 %b4 %h2 * %h3 %M5%!",
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"%0 = %h2 * %h3, %1 %b4 %d2 * %h3 %M5%!",
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"%0 = %d2 * %h3, %1 %b4 %d2 * %h3 %M5%!",
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"%0 = %h2 * %d3, %1 %b4 %h2 * %h3 %M5%!",
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"%0 = %d2 * %d3, %1 %b4 %h2 * %h3 %M5%!",
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"%0 = %h2 * %d3, %1 %b4 %d2 * %h3 %M5%!",
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"%0 = %d2 * %d3, %1 %b4 %d2 * %h3 %M5%!",
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"%0 = %h2 * %h3, %1 %b4 %h2 * %d3 %M5%!",
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"%0 = %d2 * %h3, %1 %b4 %h2 * %d3 %M5%!",
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"%0 = %h2 * %h3, %1 %b4 %d2 * %d3 %M5%!",
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"%0 = %d2 * %h3, %1 %b4 %d2 * %d3 %M5%!",
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"%0 = %h2 * %d3, %1 %b4 %h2 * %d3 %M5%!",
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"%0 = %d2 * %d3, %1 %b4 %h2 * %d3 %M5%!",
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"%0 = %h2 * %d3, %1 %b4 %d2 * %d3 %M5%!",
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"%0 = %d2 * %d3, %1 %b4 %d2 * %d3 %M5%!" };
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int alt = (INTVAL (operands[4]) + (INTVAL (operands[5]) << 1)
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+ (INTVAL (operands[6]) << 2) + (INTVAL (operands[7]) << 3));
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xops[0] = operands[0];
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xops[1] = operands[1];
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xops[2] = operands[2];
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xops[3] = operands[3];
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xops[4] = operands[9];
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xops[5] = which_alternative == 0 ? operands[10] : operands[11];
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output_asm_insn (templates[alt], xops);
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return "";
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}
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[(set_attr "type" "dsp32")])
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(define_code_macro s_or_u [sign_extend zero_extend])
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(define_code_attr su_optab [(sign_extend "mul")
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(zero_extend "umul")])
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|
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@ -2249,6 +2249,14 @@ Unsigned 3 bit integer (in the range 0 to 7)
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@item P@var{n}
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Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
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@item PA
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An integer equal to one of the MACFLAG_XXX constants that is suitable for
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use with either accumulator.
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@item PB
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An integer equal to one of the MACFLAG_XXX constants that is suitable for
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use only with accumulator A1.
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@item M1
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Constant 255.
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|
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