From 3f07249e98a147a94675a5427f73ca0b0ce3ef9b Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Sun, 29 Oct 2006 18:20:45 +0000 Subject: [PATCH] mips.md (mul3): Check ISA_HAS_MUL3 rather than GENERATE_MULT3_. gcc/ * config/mips/mips.md (mul3): Check ISA_HAS_MUL3 rather than GENERATE_MULT3_. Restrict the test to SImode. Use ISA_HAS_MUL3 rather than GENERATE_MULT3_SI in the various define_peephole2s. (mulsi3_mult3): Depend on ISA_HAS_MUL3 rather than GENERATE_MULT3_SI. Use an inclusive test for "mult" rather than "mul". (rotr3): Depend on ISA_HAS_ROR. * config/mips/mips.h (GENERATE_MULT3_SI): Delete in favor of ISA_HAS_MUL3. (GENERATE_MULT3_DI): Delete. (ISA_HAS_64BIT_REGS): Use consistent formatting. (ISA_HAS_MUL3): New macro. (ISA_HAS_CONDMOVE, ISA_HAS_8CC): Use consistent formatting. (ISA_HAS_FP4, ISA_HAS_MADD_MSUB, ISA_HAS_NMADD_NMSUB): Likewise. (ISA_HAS_CLZ_CLO): Likewise. (ISA_HAS_DCLZ_DCLO): Delete. (ISA_HAS_MULHI, ISA_HAS_MULS, ISA_HAS_MSAC): Require !TARGET_MIPS16. (ISA_HAS_MACC): Require !TARGET_MIPS16 for all ISAs, not just the VR4120 and VR4130. (ISA_HAS_MACCHI): Use consistent formatting. (ISA_HAS_ROTR_SI, ISA_HAS_ROTR_DI): Delete in favor of... (ISA_HAS_ROR): ...this new macro. (ISA_HAS_PREFETCH, ISA_HAS_PREFETCHX): Use consistent formatting. (ISA_HAS_SEB_SEH, ISA_HAS_EXT_INS): Likewise. (ISA_HAS_LOAD_DELAY): Use ISA_MIPS1. From-SVN: r118153 --- gcc/ChangeLog | 27 +++++++ gcc/config/mips/mips.h | 157 ++++++++++++++++++---------------------- gcc/config/mips/mips.md | 38 +++------- 3 files changed, 106 insertions(+), 116 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fbdec1aff07..920d31da62b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,30 @@ +2006-10-29 Richard Sandiford + + * config/mips/mips.md (mul3): Check ISA_HAS_MUL3 rather than + GENERATE_MULT3_. Restrict the test to SImode. Use ISA_HAS_MUL3 + rather than GENERATE_MULT3_SI in the various define_peephole2s. + (mulsi3_mult3): Depend on ISA_HAS_MUL3 rather than GENERATE_MULT3_SI. + Use an inclusive test for "mult" rather than "mul". + (rotr3): Depend on ISA_HAS_ROR. + * config/mips/mips.h (GENERATE_MULT3_SI): Delete in favor of + ISA_HAS_MUL3. + (GENERATE_MULT3_DI): Delete. + (ISA_HAS_64BIT_REGS): Use consistent formatting. + (ISA_HAS_MUL3): New macro. + (ISA_HAS_CONDMOVE, ISA_HAS_8CC): Use consistent formatting. + (ISA_HAS_FP4, ISA_HAS_MADD_MSUB, ISA_HAS_NMADD_NMSUB): Likewise. + (ISA_HAS_CLZ_CLO): Likewise. + (ISA_HAS_DCLZ_DCLO): Delete. + (ISA_HAS_MULHI, ISA_HAS_MULS, ISA_HAS_MSAC): Require !TARGET_MIPS16. + (ISA_HAS_MACC): Require !TARGET_MIPS16 for all ISAs, not just + the VR4120 and VR4130. + (ISA_HAS_MACCHI): Use consistent formatting. + (ISA_HAS_ROTR_SI, ISA_HAS_ROTR_DI): Delete in favor of... + (ISA_HAS_ROR): ...this new macro. + (ISA_HAS_PREFETCH, ISA_HAS_PREFETCHX): Use consistent formatting. + (ISA_HAS_SEB_SEH, ISA_HAS_EXT_INS): Likewise. + (ISA_HAS_LOAD_DELAY): Use ISA_MIPS1. + 2006-10-29 Roger Sayle PR tree-optimization/15458 diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index ba77d8636af..9e2542f552b 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -553,22 +553,6 @@ extern const struct mips_rtx_cost_data *mips_cost; && !TARGET_SR71K \ && !TARGET_MIPS16) -/* Generate three-operand multiply instructions for SImode. */ -#define GENERATE_MULT3_SI ((TARGET_MIPS3900 \ - || TARGET_MIPS5400 \ - || TARGET_MIPS5500 \ - || TARGET_MIPS7000 \ - || TARGET_MIPS9000 \ - || TARGET_MAD \ - || ISA_MIPS32 \ - || ISA_MIPS32R2 \ - || ISA_MIPS64) \ - && !TARGET_MIPS16) - -/* Generate three-operand multiply instructions for DImode. */ -#define GENERATE_MULT3_DI ((TARGET_MIPS3900) \ - && !TARGET_MIPS16) - /* True if the ABI can only work with 64-bit integer registers. We generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but otherwise floating-point registers must also be 64-bit. */ @@ -584,126 +568,125 @@ extern const struct mips_rtx_cost_data *mips_cost; /* ISA has instructions for managing 64 bit fp and gp regs (e.g. mips3). */ #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \ || ISA_MIPS4 \ - || ISA_MIPS64) + || ISA_MIPS64) /* ISA has branch likely instructions (e.g. mips2). */ /* Disable branchlikely for tx39 until compare rewrite. They haven't been generated up to this point. */ #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1) -/* ISA has the conditional move instructions introduced in mips4. */ -#define ISA_HAS_CONDMOVE ((ISA_MIPS4 \ - || ISA_MIPS32 \ - || ISA_MIPS32R2 \ +/* ISA has a three-operand multiplcation instruction (usually spelt "mul"). */ +#define ISA_HAS_MUL3 ((TARGET_MIPS3900 \ + || TARGET_MIPS5400 \ + || TARGET_MIPS5500 \ + || TARGET_MIPS7000 \ + || TARGET_MIPS9000 \ + || TARGET_MAD \ + || ISA_MIPS32 \ + || ISA_MIPS32R2 \ || ISA_MIPS64) \ - && !TARGET_MIPS5500 \ + && !TARGET_MIPS16) + +/* ISA has the conditional move instructions introduced in mips4. */ +#define ISA_HAS_CONDMOVE ((ISA_MIPS4 \ + || ISA_MIPS32 \ + || ISA_MIPS32R2 \ + || ISA_MIPS64) \ + && !TARGET_MIPS5500 \ && !TARGET_MIPS16) /* ISA has the mips4 FP condition code instructions: FP-compare to CC, branch on CC, and move (both FP and non-FP) on CC. */ #define ISA_HAS_8CC (ISA_MIPS4 \ - || ISA_MIPS32 \ - || ISA_MIPS32R2 \ + || ISA_MIPS32 \ + || ISA_MIPS32R2 \ || ISA_MIPS64) /* This is a catch all for other mips4 instructions: indexed load, the FP madd and msub instructions, and the FP recip and recip sqrt instructions. */ -#define ISA_HAS_FP4 ((ISA_MIPS4 \ - || ISA_MIPS64) \ - && !TARGET_MIPS16) +#define ISA_HAS_FP4 ((ISA_MIPS4 \ + || ISA_MIPS64) \ + && !TARGET_MIPS16) /* ISA has conditional trap instructions. */ #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \ && !TARGET_MIPS16) /* ISA has integer multiply-accumulate instructions, madd and msub. */ -#define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \ +#define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \ || ISA_MIPS32R2 \ - || ISA_MIPS64 \ - ) && !TARGET_MIPS16) + || ISA_MIPS64) \ + && !TARGET_MIPS16) /* ISA has floating-point nmadd and nmsub instructions. */ #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \ - || ISA_MIPS64) \ - && (!TARGET_MIPS5400 || TARGET_MAD) \ - && ! TARGET_MIPS16) + || ISA_MIPS64) \ + && (!TARGET_MIPS5400 || TARGET_MAD) \ + && !TARGET_MIPS16) /* ISA has count leading zeroes/ones instruction (not implemented). */ -#define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \ - || ISA_MIPS32R2 \ - || ISA_MIPS64 \ - ) && !TARGET_MIPS16) - -/* ISA has double-word count leading zeroes/ones instruction (not - implemented). */ -#define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \ +#define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \ + || ISA_MIPS32R2 \ + || ISA_MIPS64) \ && !TARGET_MIPS16) /* ISA has three operand multiply instructions that put the high part in an accumulator: mulhi or mulhiu. */ -#define ISA_HAS_MULHI (TARGET_MIPS5400 \ - || TARGET_MIPS5500 \ - || TARGET_SR71K \ - ) +#define ISA_HAS_MULHI ((TARGET_MIPS5400 \ + || TARGET_MIPS5500 \ + || TARGET_SR71K) \ + && !TARGET_MIPS16) /* ISA has three operand multiply instructions that negates the result and puts the result in an accumulator. */ -#define ISA_HAS_MULS (TARGET_MIPS5400 \ - || TARGET_MIPS5500 \ - || TARGET_SR71K \ - ) +#define ISA_HAS_MULS ((TARGET_MIPS5400 \ + || TARGET_MIPS5500 \ + || TARGET_SR71K) \ + && !TARGET_MIPS16) /* ISA has three operand multiply instructions that subtracts the result from a 4th operand and puts the result in an accumulator. */ -#define ISA_HAS_MSAC (TARGET_MIPS5400 \ - || TARGET_MIPS5500 \ - || TARGET_SR71K \ - ) +#define ISA_HAS_MSAC ((TARGET_MIPS5400 \ + || TARGET_MIPS5500 \ + || TARGET_SR71K) \ + && !TARGET_MIPS16) + /* ISA has three operand multiply instructions that the result from a 4th operand and puts the result in an accumulator. */ -#define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \ - || (TARGET_MIPS4130 && !TARGET_MIPS16) \ - || TARGET_MIPS5400 \ - || TARGET_MIPS5500 \ - || TARGET_SR71K \ - ) +#define ISA_HAS_MACC ((TARGET_MIPS4120 \ + || TARGET_MIPS4130 \ + || TARGET_MIPS5400 \ + || TARGET_MIPS5500 \ + || TARGET_SR71K) \ + && !TARGET_MIPS16) /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */ -#define ISA_HAS_MACCHI (!TARGET_MIPS16 \ - && (TARGET_MIPS4120 \ - || TARGET_MIPS4130)) +#define ISA_HAS_MACCHI ((TARGET_MIPS4120 \ + || TARGET_MIPS4130) \ + && !TARGET_MIPS16) -/* ISA has 32-bit rotate right instruction. */ -#define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \ - && (ISA_MIPS32R2 \ - || TARGET_MIPS5400 \ - || TARGET_MIPS5500 \ - || TARGET_SR71K \ - )) - -/* ISA has 64-bit rotate right instruction. */ -#define ISA_HAS_ROTR_DI (TARGET_64BIT \ - && !TARGET_MIPS16 \ - && (TARGET_MIPS5400 \ - || TARGET_MIPS5500 \ - || TARGET_SR71K \ - )) +/* ISA has the "ror" (rotate right) instructions. */ +#define ISA_HAS_ROR ((ISA_MIPS32R2 \ + || TARGET_MIPS5400 \ + || TARGET_MIPS5500 \ + || TARGET_SR71K) \ + && !TARGET_MIPS16) /* ISA has data prefetch instructions. This controls use of 'pref'. */ #define ISA_HAS_PREFETCH ((ISA_MIPS4 \ || ISA_MIPS32 \ || ISA_MIPS32R2 \ - || ISA_MIPS64) \ + || ISA_MIPS64) \ && !TARGET_MIPS16) /* ISA has data indexed prefetch instructions. This controls use of 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. (prefx is a cop1x instruction, so can only be used if FP is enabled.) */ -#define ISA_HAS_PREFETCHX ((ISA_MIPS4 \ - || ISA_MIPS64) \ - && !TARGET_MIPS16) +#define ISA_HAS_PREFETCHX ((ISA_MIPS4 \ + || ISA_MIPS64) \ + && !TARGET_MIPS16) /* True if trunc.w.s and trunc.w.d are real (not synthetic) instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d @@ -711,19 +694,17 @@ extern const struct mips_rtx_cost_data *mips_cost; #define ISA_HAS_TRUNC_W (!ISA_MIPS1) /* ISA includes the MIPS32r2 seb and seh instructions. */ -#define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \ - && (ISA_MIPS32R2 \ - )) +#define ISA_HAS_SEB_SEH (ISA_MIPS32R2 \ + && !TARGET_MIPS16) /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */ -#define ISA_HAS_EXT_INS (!TARGET_MIPS16 \ - && (ISA_MIPS32R2 \ - )) +#define ISA_HAS_EXT_INS (ISA_MIPS32R2 \ + && !TARGET_MIPS16) /* True if the result of a load is not available to the next instruction. A nop will then be needed between instructions like "lw $4,..." and "addiu $4,$4,1". */ -#define ISA_HAS_LOAD_DELAY (mips_isa == 1 \ +#define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \ && !TARGET_MIPS3900 \ && !TARGET_MIPS16) diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 969d22fa00f..66138714914 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -1014,7 +1014,7 @@ (match_operand:GPR 2 "register_operand")))] "" { - if (GENERATE_MULT3_) + if (mode == SImode && ISA_HAS_MUL3) emit_insn (gen_mul3_mult3 (operands[0], operands[1], operands[2])); else if (!TARGET_FIX_R4000) emit_insn (gen_mul3_internal (operands[0], operands[1], @@ -1030,35 +1030,17 @@ (match_operand:SI 2 "register_operand" "d,d"))) (clobber (match_scratch:SI 3 "=h,h")) (clobber (match_scratch:SI 4 "=l,X"))] - "GENERATE_MULT3_SI" + "ISA_HAS_MUL3" { if (which_alternative == 1) return "mult\t%1,%2"; - if (TARGET_MAD - || TARGET_MIPS5400 - || TARGET_MIPS5500 - || TARGET_MIPS7000 - || TARGET_MIPS9000 - || ISA_MIPS32 - || ISA_MIPS32R2 - || ISA_MIPS64) - return "mul\t%0,%1,%2"; - return "mult\t%0,%1,%2"; + if (TARGET_MIPS3900) + return "mult\t%0,%1,%2"; + return "mul\t%0,%1,%2"; } [(set_attr "type" "imul3,imul") (set_attr "mode" "SI")]) -(define_insn "muldi3_mult3" - [(set (match_operand:DI 0 "register_operand" "=d") - (mult:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:DI 2 "register_operand" "d"))) - (clobber (match_scratch:DI 3 "=h")) - (clobber (match_scratch:DI 4 "=l"))] - "TARGET_64BIT && GENERATE_MULT3_DI" - "dmult\t%0,%1,%2" - [(set_attr "type" "imul3") - (set_attr "mode" "DI")]) - ;; If a register gets allocated to LO, and we spill to memory, the reload ;; will include a move from LO to a GPR. Merge it into the multiplication ;; if it can set the GPR directly. @@ -1077,7 +1059,7 @@ (clobber (scratch:SI))]) (set (match_operand:SI 4 "register_operand") (unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))] - "GENERATE_MULT3_SI && peep2_reg_dead_p (2, operands[0])" + "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])" [(parallel [(set (match_dup 4) (mult:SI (match_dup 1) @@ -1124,7 +1106,7 @@ (clobber (match_operand:SI 3 "register_operand"))]) (set (match_operand:SI 4 "register_operand") (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))] - "ISA_HAS_MACC && !GENERATE_MULT3_SI" + "ISA_HAS_MACC && !ISA_HAS_MUL3" [(set (match_dup 0) (const_int 0)) (parallel @@ -1359,7 +1341,7 @@ (match_operand:SI 4 "macc_msac_operand")) (clobber (match_operand:SI 5 "register_operand")) (clobber (match_dup 1))])] - "GENERATE_MULT3_SI + "ISA_HAS_MUL3 && true_regnum (operands[1]) == LO_REGNUM && peep2_reg_dead_p (2, operands[1]) && GP_REG_P (true_regnum (operands[3]))" @@ -1398,7 +1380,7 @@ (match_dup 0) (set (match_operand:SI 5 "register_operand") (unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))] - "GENERATE_MULT3_SI && peep2_reg_dead_p (3, operands[1])" + "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])" [(parallel [(set (match_dup 0) (match_dup 6)) (clobber (match_dup 4)) @@ -4259,7 +4241,7 @@ [(set (match_operand:GPR 0 "register_operand" "=d") (rotatert:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:SI 2 "arith_operand" "dI")))] - "ISA_HAS_ROTR_" + "ISA_HAS_ROR" { if (GET_CODE (operands[2]) == CONST_INT) gcc_assert (INTVAL (operands[2]) >= 0