For 128/256-bit vec_cond_expr, When mask operands is lt reg const0_rtx, blendv can be used instead of avx512 mask.
gcc/ChangeLog: PR target/100648 * config/i386/sse.md (*avx_cmp<mode>3_lt): New define_insn_and_split. (*avx_cmp<mode>3_ltint): Ditto. (*avx2_pcmp<mode>3_3): Ditto. (*avx2_pcmp<mode>3_4): Ditto. (*avx2_pcmp<mode>3_5): Ditto. gcc/testsuite/ChangeLog: PR target/100648 * g++.target/i386/avx2-pr54700-2.C: Adjust testcase. * g++.target/i386/avx512vl-pr54700-1a.C: New test. * g++.target/i386/avx512vl-pr54700-1b.C: New test. * g++.target/i386/avx512vl-pr54700-2a.C: New test. * g++.target/i386/avx512vl-pr54700-2b.C: New test. * gcc.target/i386/avx512vl-pr100648.c: New test. * gcc.target/i386/avx512vl-blendv-1.c: New test. * gcc.target/i386/avx512vl-blendv-2.c: New test.
This commit is contained in:
liuhongt
parent
28560c6d40
commit
3f1a08d9d7
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@ -3048,6 +3048,68 @@
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UNSPEC_PCMP))]
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"operands[5] = GEN_INT (INTVAL (operands[5]) ^ 4);")
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(define_insn_and_split "*avx_cmp<mode>3_lt"
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[(set (match_operand:VF_128_256 0 "register_operand")
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(vec_merge:VF_128_256
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(match_operand:VF_128_256 1 "vector_operand")
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(match_operand:VF_128_256 2 "vector_operand")
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(unspec:<avx512fmaskmode>
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[(match_operand:<sseintvecmode> 3 "register_operand")
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(match_operand:<sseintvecmode> 4 "const0_operand")
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(match_operand:SI 5 "const_0_to_7_operand")]
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UNSPEC_PCMP)))]
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"TARGET_AVX512VL && ix86_pre_reload_split ()
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/* LT or GE 0 */
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&& ((INTVAL (operands[5]) == 1 && !MEM_P (operands[2]))
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|| (INTVAL (operands[5]) == 5 && !MEM_P (operands[1])))"
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"#"
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"&& 1"
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[(set (match_dup 0)
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(unspec:VF_128_256
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[(match_dup 2)
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(match_dup 1)
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(lt:VF_128_256
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(match_dup 3)
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(match_dup 4))]
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UNSPEC_BLENDV))]
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{
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if (INTVAL (operands[5]) == 5)
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std::swap (operands[1], operands[2]);
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})
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(define_insn_and_split "*avx_cmp<mode>3_ltint"
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[(set (match_operand:VI48_AVX 0 "register_operand")
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(vec_merge:VI48_AVX
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(match_operand:VI48_AVX 1 "vector_operand")
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(match_operand:VI48_AVX 2 "vector_operand")
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(unspec:<avx512fmaskmode>
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[(match_operand:VI48_AVX 3 "register_operand")
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(match_operand:VI48_AVX 4 "const0_operand")
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(match_operand:SI 5 "const_0_to_7_operand")]
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UNSPEC_PCMP)))]
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"TARGET_AVX512VL && ix86_pre_reload_split ()
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/* LT or GE 0 */
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&& ((INTVAL (operands[5]) == 1 && !MEM_P (operands[2]))
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|| (INTVAL (operands[5]) == 5 && !MEM_P (operands[1])))"
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"#"
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"&& 1"
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[(set (match_dup 0)
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(unspec:<ssebytemode>
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[(match_dup 2)
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(match_dup 1)
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(subreg:<ssebytemode>
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(lt:VI48_AVX
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(match_dup 3)
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(match_dup 4)) 0)]
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UNSPEC_BLENDV))]
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{
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if (INTVAL (operands[5]) == 5)
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std::swap (operands[1], operands[2]);
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operands[0] = gen_lowpart (<ssebytemode>mode, operands[0]);
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operands[1] = gen_lowpart (<ssebytemode>mode, operands[1]);
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operands[2] = gen_lowpart (<ssebytemode>mode, operands[2]);
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})
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(define_insn "avx_vmcmp<mode>3"
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[(set (match_operand:VF_128 0 "register_operand" "=x")
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(vec_merge:VF_128
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@ -13063,6 +13125,96 @@
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DONE;
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})
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(define_insn_and_split "*avx2_pcmp<mode>3_3"
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[(set (match_operand:VI1_AVX2 0 "register_operand")
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(vec_merge:VI1_AVX2
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(match_operand:VI1_AVX2 1 "vector_operand")
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(match_operand:VI1_AVX2 2 "vector_operand")
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(unspec:<avx512fmaskmode>
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[(match_operand:VI1_AVX2 3 "register_operand")
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(match_operand:VI1_AVX2 4 "const0_operand")
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(match_operand:SI 5 "const_0_to_7_operand")]
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UNSPEC_PCMP)))]
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"TARGET_AVX512VL && ix86_pre_reload_split ()
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/* LT or GE 0 */
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&& ((INTVAL (operands[5]) == 1 && !MEM_P (operands[2]))
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|| (INTVAL (operands[5]) == 5 && !MEM_P (operands[1])))"
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"#"
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"&& 1"
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[(set (match_dup 0)
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(unspec:VI1_AVX2
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[(match_dup 2)
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(match_dup 1)
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(lt:VI1_AVX2
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(match_dup 3)
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(match_dup 4))]
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UNSPEC_BLENDV))]
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{
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if (INTVAL (operands[5]) == 5)
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std::swap (operands[1], operands[2]);
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})
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(define_insn_and_split "*avx2_pcmp<mode>3_4"
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[(set (match_operand:VI1_AVX2 0 "register_operand")
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(vec_merge:VI1_AVX2
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(match_operand:VI1_AVX2 1 "vector_operand")
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(match_operand:VI1_AVX2 2 "vector_operand")
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(unspec:<avx512fmaskmode>
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[(subreg:VI1_AVX2 (not (match_operand 3 "register_operand")) 0)
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(match_operand:VI1_AVX2 4 "const0_operand")
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(match_operand:SI 5 "const_0_to_7_operand")]
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UNSPEC_PCMP)))]
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"TARGET_AVX512VL && ix86_pre_reload_split ()
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&& GET_MODE_CLASS (GET_MODE (operands[3])) == MODE_VECTOR_INT
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&& GET_MODE_SIZE (GET_MODE (operands[3])) == <MODE_SIZE>
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/* LT or GE 0 */
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&& ((INTVAL (operands[5]) == 1 && !MEM_P (operands[1]))
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|| (INTVAL (operands[5]) == 5 && !MEM_P (operands[2])))"
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"#"
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"&& 1"
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[(set (match_dup 0)
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(unspec:VI1_AVX2
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[(match_dup 1)
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(match_dup 2)
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(lt:VI1_AVX2
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(match_dup 3)
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(match_dup 4))]
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UNSPEC_BLENDV))]
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{
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if (INTVAL (operands[5]) == 1)
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std::swap (operands[1], operands[2]);
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operands[3] = gen_lowpart (<MODE>mode, operands[3]);
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})
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(define_insn_and_split "*avx2_pcmp<mode>3_5"
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[(set (match_operand:VI1_AVX2 0 "register_operand")
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(vec_merge:VI1_AVX2
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(match_operand:VI1_AVX2 1 "vector_operand")
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(match_operand:VI1_AVX2 2 "vector_operand")
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(unspec:<avx512fmaskmode>
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[(not:VI1_AVX2 (match_operand:VI1_AVX2 3 "register_operand"))
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(match_operand:VI1_AVX2 4 "const0_operand")
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(match_operand:SI 5 "const_0_to_7_operand")]
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UNSPEC_PCMP)))]
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"TARGET_AVX512VL && ix86_pre_reload_split ()
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/* LT or GE 0 */
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&& ((INTVAL (operands[5]) == 1 && !MEM_P (operands[1]))
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|| (INTVAL (operands[5]) == 5 && !MEM_P (operands[2])))"
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"#"
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"&& 1"
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[(set (match_dup 0)
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(unspec:VI1_AVX2
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[(match_dup 1)
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(match_dup 2)
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(lt:VI1_AVX2
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(match_dup 3)
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(match_dup 4))]
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UNSPEC_BLENDV))]
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{
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if (INTVAL (operands[5]) == 1)
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std::swap (operands[1], operands[2]);
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})
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(define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>"
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[(set (match_operand:<avx512fmaskmode> 0 "register_operand")
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(unspec:<avx512fmaskmode>
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@ -2,9 +2,15 @@
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/* { dg-do run { target avx2 } } */
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/* { dg-options "-O2 -std=c++14 -mavx2 -mno-xop -mno-avx512f" } */
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#include "avx2-check.h"
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#ifndef CHECK_H
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#define CHECK_H "avx2-check.h"
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#endif
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#ifndef TEST
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#define TEST avx2_test
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#endif
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#include CHECK_H
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#include "avx2-pr54700-1.C"
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@ -0,0 +1,9 @@
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/* PR target/100648 */
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/* { dg-do compile } */
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/* { dg-options "-O2 -std=c++14 -mavx2 -mno-xop -mavx512vl -mavx512bw" } */
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/* { dg-final { scan-assembler-not "vpcmpgt\[bdq]" } } */
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/* { dg-final { scan-assembler-times "vpblendvb" 2 } } */
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/* { dg-final { scan-assembler-times "vblendvps" 4 } } */
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/* { dg-final { scan-assembler-times "vblendvpd" 4 } } */
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#include "avx2-pr54700-1.C"
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@ -0,0 +1,9 @@
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/* PR target/100648 */
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/* { dg-do compile } */
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/* { dg-options "-O2 -std=c++14 -mavx512vl -mavx512bw -mno-xop" } */
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/* { dg-final { scan-assembler-not "pcmpgt\[bdq]" } } */
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/* { dg-final { scan-assembler-times "pblendvb" 2 } } */
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/* { dg-final { scan-assembler-times "blendvps" 4 } } */
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/* { dg-final { scan-assembler-times "blendvpd" 4 } } */
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#include "sse4_1-pr54700-1.C"
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@ -0,0 +1,17 @@
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/* PR target/100648 */
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/* { dg-do run { target avx2 } } */
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/* { dg-options "-O2 -std=c++14 -mavx2 -mavx512vl -mavx512bw" } */
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#ifndef CHECK_H
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#define CHECK_H "avx512f-helper.h"
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#endif
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#ifndef TEST
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#define TEST_test_256
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#endif
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#include CHECK_H
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#include "avx2-pr54700-2.C"
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#define AVX512VL
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#define AVX512BW
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@ -0,0 +1,17 @@
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/* PR target/pr100648 */
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/* { dg-do run { target sse4 } } */
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/* { dg-options "-O2 -std=c++14 -msse4 -mavx512vl -mavx512bw -mno-xop" } */
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#ifndef CHECK_H
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#define CHECK_H "avx512f-helper.h"
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#endif
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#ifndef TEST
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#define TEST_test_128
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#endif
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#include CHECK_H
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#include "sse4_1-pr54700-2.C"
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#define AVX512VL
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#define AVX512BW
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@ -0,0 +1,51 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -mavx512vl" } */
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/* { dg-final { scan-assembler-times {pblendvb[\t ]*%xmm} 1 } } */
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/* { dg-final { scan-assembler-times {pblendvb[\t ]*%ymm} 1 } } */
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/* { dg-final { scan-assembler-times {blendvps[\t ]*%xmm} 1 } } */
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/* { dg-final { scan-assembler-times {blendvps[\t ]*%ymm} 1 } } */
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/* { dg-final { scan-assembler-times {blendvpd[\t ]*%xmm} 1 } } */
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/* { dg-final { scan-assembler-times {blendvpd[\t ]*%ymm} 1 } } */
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typedef float v4sf __attribute__ ((vector_size (16)));
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typedef float v8sf __attribute__ ((vector_size (32)));
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typedef double v2df __attribute__ ((vector_size (16)));
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typedef double v4df __attribute__ ((vector_size (32)));
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typedef char v16qi __attribute__ ((vector_size (16)));
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typedef char v32qi __attribute__ ((vector_size (32)));
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v4sf
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foo (v4sf a, v4sf b, v4sf c)
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{
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return __builtin_ia32_blendvps (a, b, c);
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}
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v8sf
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foo2 (v8sf a, v8sf b, v8sf c)
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{
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return __builtin_ia32_blendvps256 (a, b, c);
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}
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v2df
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foo3 (v2df a, v2df b, v2df c)
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{
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return __builtin_ia32_blendvpd (a, b, c);
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}
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v4df
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foo4 (v4df a, v4df b, v4df c)
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{
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return __builtin_ia32_blendvpd256 (a, b, c);
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}
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v16qi
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foo5 (v16qi a, v16qi b, v16qi c)
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{
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return __builtin_ia32_pblendvb128 (a, b, c);
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}
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v32qi
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foo6 (v32qi a, v32qi b, v32qi c)
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{
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return __builtin_ia32_pblendvb256 (a, b, c);
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}
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@ -0,0 +1,41 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -mavx512vl" } */
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/* { dg-final { scan-assembler-not {pblendv} } } */
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/* { dg-final { scan-assembler-not {blendvp} } } */
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#include <x86intrin.h>
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__m128
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foo (__m128 a, __m128 b)
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{
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return _mm_blendv_ps (a, b, _mm_setzero_ps ());
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}
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__m256
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foo2 (__m256 a, __m256 b)
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{
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return _mm256_blendv_ps (a, b, _mm256_set1_ps (-1.0));
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}
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__m128d
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foo3 (__m128d a, __m128d b, __m128d c)
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{
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return _mm_blendv_pd (a, b, _mm_set1_pd (1.0));
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}
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__m256d
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foo4 (__m256d a, __m256d b, __m256d c)
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{
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return _mm256_blendv_pd (a, b, _mm256_set1_pd (-134.3));
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}
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__m128i
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foo5 (__m128i a, __m128i b, __m128i c)
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{
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return _mm_blendv_epi8 (a, b, _mm_set1_epi8 (3));
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}
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__m256i
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foo6 (__m256i a, __m256i b, __m256i c)
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{
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return _mm256_blendv_epi8 (a, b, _mm256_set1_epi8 (-22));
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}
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@ -0,0 +1,21 @@
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/* PR target/100648. */
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/* { dg-do compile } */
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/* { dg-options "-O2 -mavx512vl -mavx512bw -masm=att" } */
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/* { dg-final { scan-assembler-times "\tvpblendvb\t" 2 } } */
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/* { dg-final { scan-assembler-not "\tvpcmpeq" } } */
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/* { dg-final { scan-assembler-not "\tvpandn" } } */
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#include <x86intrin.h>
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__m256i
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f1 (__m256i a, __m256i b, __m256i mask)
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{
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return _mm256_blendv_epi8(a, b,
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_mm256_andnot_si256(mask, _mm256_set1_epi8(255)));
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}
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__m128i
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f2 (__m128i a, __m128i b, __m128i mask)
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{
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return _mm_blendv_epi8(a, b,
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_mm_andnot_si128(mask, _mm_set1_epi8(255)));
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}
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