Pass QI/HI structures like the MIPS compiler; define SIZE_TYPE to be int by default.
From-SVN: r2893
This commit is contained in:
Michael Meissner
parent
d45820250a
commit
3f1f8d8c04
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@ -2413,6 +2413,7 @@ init_cumulative_args (cum, fntype, libname)
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tree fntype; /* tree ptr for function decl */
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rtx libname; /* SYMBOL_REF of library name or 0 */
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{
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static CUMULATIVE_ARGS zero_cum;
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tree param, next_param;
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if (TARGET_DEBUG_E_MODE)
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@ -2430,9 +2431,7 @@ init_cumulative_args (cum, fntype, libname)
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}
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}
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cum->gp_reg_found = 0;
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cum->arg_number = 0;
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cum->arg_words = 0;
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*cum = zero_cum;
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/* Determine if this function has variable arguments. This is
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indicated by the last argument being 'void_type_mode' if there
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@ -2461,7 +2460,7 @@ function_arg_advance (cum, mode, type, named)
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{
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if (TARGET_DEBUG_E_MODE)
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fprintf (stderr,
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"function_adv( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d )\n",
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"function_adv( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d )\n\n",
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cum->gp_reg_found, cum->arg_number, cum->arg_words, GET_MODE_NAME (mode),
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type, named);
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@ -2512,8 +2511,12 @@ function_arg (cum, mode, type, named)
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tree type; /* type of the argument or 0 if lib support */
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int named; /* != 0 for normal args, == 0 for ... args */
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{
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rtx ret;
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int regbase = -1;
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int bias = 0;
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int struct_p = ((type != (tree)0)
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&& (TREE_CODE (type) == RECORD_TYPE
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|| TREE_CODE (type) == UNION_TYPE));
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if (TARGET_DEBUG_E_MODE)
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fprintf (stderr,
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@ -2567,18 +2570,42 @@ function_arg (cum, mode, type, named)
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if (cum->arg_words >= MAX_ARGS_IN_REGISTERS)
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{
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if (TARGET_DEBUG_E_MODE)
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fprintf (stderr, "<stack>\n");
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fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : "");
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return 0;
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ret = (rtx)0;
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}
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else
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{
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if (regbase == -1)
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abort ();
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ret = gen_rtx (REG, mode, regbase + cum->arg_words + bias);
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if (TARGET_DEBUG_E_MODE)
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fprintf (stderr, "%s%s\n", reg_names[regbase + cum->arg_words + bias],
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struct_p ? ", [struct]" : "");
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/* The following is a hack in order to pass 1 byte structures
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the same way that the MIPS compiler does (namely by passing
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the structure in the high byte or half word of the register).
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This also makes varargs work. If we have such a structure,
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we save the adjustment RTL, and the call define expands will
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emit them. For the VOIDmode argument (argument after the
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last real argument, pass back a parallel vector holding each
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of the adjustments. */
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if (struct_p && (mode == QImode || mode == HImode))
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{
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rtx amount = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (mode));
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rtx reg = gen_rtx (REG, SImode, regbase + cum->arg_words + bias);
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cum->adjust[ cum->num_adjusts++ ] = gen_ashlsi3 (reg, reg, amount);
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}
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}
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if (regbase == -1)
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abort ();
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if (mode == VOIDmode && cum->num_adjusts > 0)
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ret = gen_rtx (PARALLEL, VOIDmode, gen_rtvec_v (cum->num_adjusts, cum->adjust));
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if (TARGET_DEBUG_E_MODE)
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fprintf (stderr, "%s\n", reg_names[regbase + cum->arg_words + bias]);
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return gen_rtx (REG, mode, regbase + cum->arg_words + bias);
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return ret;
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}
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@ -4237,20 +4264,56 @@ mips_expand_prologue ()
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{
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int regno;
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long tsize;
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tree fndecl = current_function_decl; /* current... is tooo long */
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tree fntype = TREE_TYPE (fndecl);
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tree fnargs = (TREE_CODE (fntype) != METHOD_TYPE)
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? DECL_ARGUMENTS (fndecl)
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: 0;
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tree next_arg;
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tree cur_arg;
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rtx tmp_rtx = (rtx)0;
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char *arg_name = (char *)0;
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tree fndecl = current_function_decl;
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tree fntype = TREE_TYPE (fndecl);
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tree fnargs = (TREE_CODE (fntype) != METHOD_TYPE)
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? DECL_ARGUMENTS (fndecl)
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: 0;
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rtx next_arg_reg;
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int i;
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tree next_arg;
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tree cur_arg;
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CUMULATIVE_ARGS args_so_far;
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/* Determine the last argument, and get its name. */
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INIT_CUMULATIVE_ARGS (args_so_far, fntype, (rtx)0);
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regno = GP_ARG_FIRST;
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for (cur_arg = fnargs; cur_arg != (tree)0; cur_arg = next_arg)
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{
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tree type = DECL_ARG_TYPE (cur_arg);
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enum machine_mode passed_mode = TYPE_MODE (type);
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rtx entry_parm = FUNCTION_ARG (args_so_far,
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passed_mode,
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DECL_ARG_TYPE (cur_arg),
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1);
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if (entry_parm)
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{
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int words;
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/* passed in a register, so will get homed automatically */
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if (GET_MODE (entry_parm) == BLKmode)
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words = (int_size_in_bytes (type) + 3) / 4;
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else
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words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
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regno = REGNO (entry_parm) + words - 1;
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}
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else
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{
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regno = GP_ARG_LAST+1;
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break;
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}
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FUNCTION_ARG_ADVANCE (args_so_far,
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passed_mode,
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DECL_ARG_TYPE (cur_arg),
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1);
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next_arg = TREE_CHAIN (cur_arg);
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if (next_arg == (tree)0)
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{
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@ -4261,52 +4324,39 @@ mips_expand_prologue ()
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}
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}
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/* In order to pass small structures by value in registers
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compatibly with the MIPS compiler, we need to shift the value
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into the high part of the register. Function_arg has encoded a
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PARALLEL rtx, holding a vector of adjustments to be made as the
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next_arg_reg variable, so we split up the insns, and emit them
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separately. */
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next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
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if (next_arg_reg != (rtx)0 && GET_CODE (next_arg_reg) == PARALLEL)
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{
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rtvec adjust = XVEC (next_arg_reg, 0);
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int num = GET_NUM_ELEM (adjust);
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for (i = 0; i < num; i++)
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{
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rtx pattern = RTVEC_ELT (adjust, i);
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if (GET_CODE (pattern) != SET
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|| GET_CODE (SET_SRC (pattern)) != ASHIFT)
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abort_with_insn (pattern, "Insn is not a shift");
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PUT_CODE (SET_SRC (pattern), ASHIFTRT);
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emit_insn (pattern);
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}
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}
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/* If this function is a varargs function, store any registers that
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would normally hold arguments ($4 - $7) on the stack. */
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if ((TYPE_ARG_TYPES (fntype) != 0
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&& (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) != void_type_node))
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|| (arg_name
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&& (strcmp (arg_name, "__builtin_va_alist") == 0
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|| strcmp (arg_name, "va_alist") == 0)))
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|| (arg_name != (char *)0
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&& ((arg_name[0] == '_' && strcmp (arg_name, "__builtin_va_alist") == 0)
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|| (arg_name[0] == 'v' && strcmp (arg_name, "va_alist") == 0))))
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{
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tree parm;
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regno = GP_ARG_FIRST;
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INIT_CUMULATIVE_ARGS (args_so_far, fntype, (rtx)0);
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for (parm = fnargs; (parm && (regno <= GP_ARG_LAST)); parm = TREE_CHAIN (parm))
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{
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rtx entry_parm;
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enum machine_mode passed_mode;
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tree type;
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type = DECL_ARG_TYPE (parm);
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passed_mode = TYPE_MODE (type);
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entry_parm = FUNCTION_ARG (args_so_far, passed_mode,
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DECL_ARG_TYPE (parm), 1);
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if (entry_parm)
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{
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int words;
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/* passed in a register, so will get homed automatically */
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if (GET_MODE (entry_parm) == BLKmode)
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words = (int_size_in_bytes (type) + 3) / 4;
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else
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words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
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regno = REGNO (entry_parm) + words - 1;
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}
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else
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{
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regno = GP_ARG_LAST+1;
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break;
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}
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FUNCTION_ARG_ADVANCE (args_so_far, passed_mode,
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DECL_ARG_TYPE (parm), 1);
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}
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for (; regno <= GP_ARG_LAST; regno++)
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{
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rtx ptr = stack_pointer_rtx;
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@ -483,7 +483,7 @@ while (0)
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/* Print subsidiary information on the compiler version in use. */
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#define MIPS_VERSION "[AL 1.1, MM 32]"
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#define MIPS_VERSION "[AL 1.1, MM 33]"
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#ifndef MACHINE_TYPE
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#define MACHINE_TYPE "BSD Mips"
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@ -1809,9 +1809,12 @@ extern struct mips_frame_info current_frame_info;
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*/
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typedef struct mips_args {
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int gp_reg_found;
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int arg_number;
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int arg_words;
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int gp_reg_found; /* whether a gp register was found yet */
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int arg_number; /* argument number */
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int arg_words; /* # total words the arguments take */
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int num_adjusts; /* number of adjustments made */
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/* Adjustments made to args pass in regs. */
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struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS];
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} CUMULATIVE_ARGS;
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/* Initialize a variable CUM of type CUMULATIVE_ARGS
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@ -3525,3 +3528,15 @@ while (0)
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#define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
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#define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
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#define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
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/* Default definitions for size_t and ptrdiff_t. */
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#ifndef SIZE_TYPE
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#define SIZE_TYPE "unsigned int"
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#endif
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#ifndef PTRDIFF_TYPE
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#define PTRDIFF_TYPE "int"
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#endif
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@ -4043,17 +4043,41 @@ move\\t%0,%z4\\n\\
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(define_expand "call"
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[(parallel [(call (match_operand 0 "memory_operand" "m")
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(match_operand 1 "" "i"))
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(clobber (match_operand 2 "" ""))])] ;; overwrite op2 with $31
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(clobber (reg:SI 31))
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(use (match_operand 2 "" "")) ;; next_arg_reg
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(use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
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""
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"
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{
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rtx addr;
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operands[2] = gen_rtx (REG, SImode, GP_REG_FIRST + 31);
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if (operands[0]) /* eliminate unused code warnings */
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{
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addr = XEXP (operands[0], 0);
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if (GET_CODE (addr) != REG && !CONSTANT_ADDRESS_P (addr))
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XEXP (operands[0], 0) = force_reg (FUNCTION_MODE, addr);
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addr = XEXP (operands[0], 0);
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if (GET_CODE (addr) != REG && !CONSTANT_ADDRESS_P (addr))
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XEXP (operands[0], 0) = force_reg (FUNCTION_MODE, addr);
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/* In order to pass small structures by value in registers
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compatibly with the MIPS compiler, we need to shift the value
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into the high part of the register. Function_arg has encoded
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a PARALLEL rtx, holding a vector of adjustments to be made
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as the next_arg_reg variable, so we split up the insns,
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and emit them separately. */
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if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL)
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{
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rtvec adjust = XVEC (operands[2], 0);
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int num = GET_NUM_ELEM (adjust);
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int i;
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for (i = 0; i < num; i++)
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emit_insn (RTVEC_ELT (adjust, i));
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}
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emit_call_insn (gen_call_internal (operands[0], operands[1],
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gen_rtx (REG, Pmode, GP_REG_FIRST + 31)));
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DONE;
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}
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}")
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(define_insn "call_internal"
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@ -4071,15 +4095,13 @@ move\\t%0,%z4\\n\\
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else if (GET_CODE (target) == CONST_INT)
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{
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operands[0] = target;
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operands[1] = gen_rtx (REG, SImode, GP_REG_FIRST + 31);
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return \"%*%[li\\t%@,%0\\n\\tjal\\t%1,%@%]\";
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return \"%*%[li\\t%@,%0\\n\\tjal\\t%2,%@%]\";
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}
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else
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{
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operands[0] = target;
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operands[1] = gen_rtx (REG, SImode, GP_REG_FIRST + 31);
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return \"%*jal\\t%1,%0\";
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return \"%*jal\\t%2,%0\";
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}
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}"
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[(set_attr "type" "call")
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@ -4092,17 +4114,42 @@ move\\t%0,%z4\\n\\
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[(parallel [(set (match_operand 0 "register_operand" "=df")
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(call (match_operand 1 "memory_operand" "m")
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(match_operand 2 "" "i")))
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(clobber (match_operand 3 "" ""))])] ;; overwrite op3 with $31
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(clobber (reg:SI 31))
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(use (match_operand 3 "" ""))])] ;; next_arg_reg
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""
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"
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{
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rtx addr;
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operands[3] = gen_rtx (REG, SImode, GP_REG_FIRST + 31);
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if (operands[0]) /* eliminate unused code warning */
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{
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addr = XEXP (operands[1], 0);
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if (GET_CODE (addr) != REG && !CONSTANT_ADDRESS_P (addr))
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XEXP (operands[1], 0) = force_reg (FUNCTION_MODE, addr);
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/* In order to pass small structures by value in registers
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compatibly with the MIPS compiler, we need to shift the value
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into the high part of the register. Function_arg has encoded
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a PARALLEL rtx, holding a vector of adjustments to be made
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as the next_arg_reg variable, so we split up the insns,
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and emit them separately. */
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if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL)
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{
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rtvec adjust = XVEC (operands[3], 0);
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int num = GET_NUM_ELEM (adjust);
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int i;
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for (i = 0; i < num; i++)
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emit_insn (RTVEC_ELT (adjust, i));
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}
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emit_call_insn (gen_call_value_internal (operands[0], operands[1], operands[2],
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gen_rtx (REG, Pmode, GP_REG_FIRST + 31)));
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DONE;
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}
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addr = XEXP (operands[1], 0);
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if (GET_CODE (addr) != REG && !CONSTANT_ADDRESS_P (addr))
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XEXP (operands[1], 0) = force_reg (FUNCTION_MODE, addr);
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}")
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(define_insn "call_value_internal"
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@ -4121,15 +4168,13 @@ move\\t%0,%z4\\n\\
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else if (GET_CODE (target) == CONST_INT)
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{
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operands[1] = target;
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operands[2] = gen_rtx (REG, SImode, GP_REG_FIRST + 31);
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return \"%*%[li\\t%@,%1\\n\\tjal\\t%2,%@%]\";
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return \"%*%[li\\t%@,%1\\n\\tjal\\t%3,%@%]\";
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}
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else
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{
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operands[1] = target;
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operands[2] = gen_rtx (REG, SImode, GP_REG_FIRST + 31);
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return \"%*jal\\t%2,%1\";
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return \"%*jal\\t%3,%1\";
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}
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}"
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[(set_attr "type" "call")
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