arm.md (andsi_iorsi3_notsi): Convert define_insn into define_insn_and_split.
2013-04-05 Greta Yorsh <Greta.Yorsh@arm.com> * config/arm/arm.md (andsi_iorsi3_notsi): Convert define_insn into define_insn_and_split. (arm_negdi2,arm_abssi2,arm_neg_abssi2): Likewise. (arm_cmpdi_insn,arm_cmpdi_unsigned): Likewise. From-SVN: r197522
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@ -1,3 +1,10 @@
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2013-04-05 Greta Yorsh <Greta.Yorsh@arm.com>
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* config/arm/arm.md (andsi_iorsi3_notsi): Convert define_insn into
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define_insn_and_split.
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(arm_negdi2,arm_abssi2,arm_neg_abssi2): Likewise.
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(arm_cmpdi_insn,arm_cmpdi_unsigned): Likewise.
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2013-04-05 Greta Yorsh <Greta.Yorsh@arm.com>
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* config/arm/arm.md (arm_subdi3): Convert define_insn into
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@ -3215,13 +3215,17 @@
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""
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)
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(define_insn "*andsi_iorsi3_notsi"
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(define_insn_and_split "*andsi_iorsi3_notsi"
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[(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r")
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(and:SI (ior:SI (match_operand:SI 1 "s_register_operand" "%0,r,r")
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(match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))
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(not:SI (match_operand:SI 3 "arm_rhs_operand" "rI,rI,rI"))))]
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"TARGET_32BIT"
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"orr%?\\t%0, %1, %2\;bic%?\\t%0, %0, %3"
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"#" ; "orr%?\\t%0, %1, %2\;bic%?\\t%0, %0, %3"
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"&& reload_completed"
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[(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 2)))
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(set (match_dup 0) (and:SI (not:SI (match_dup 3)) (match_dup 0)))]
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""
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[(set_attr "length" "8")
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(set_attr "ce_count" "2")
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(set_attr "predicable" "yes")]
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@ -4273,12 +4277,24 @@
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;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1).
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;; The first alternative allows the common case of a *full* overlap.
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(define_insn "*arm_negdi2"
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(define_insn_and_split "*arm_negdi2"
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[(set (match_operand:DI 0 "s_register_operand" "=r,&r")
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(neg:DI (match_operand:DI 1 "s_register_operand" "0,r")))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_ARM"
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"rsbs\\t%Q0, %Q1, #0\;rsc\\t%R0, %R1, #0"
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"#" ; "rsbs\\t%Q0, %Q1, #0\;rsc\\t%R0, %R1, #0"
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"&& reload_completed"
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[(parallel [(set (reg:CC CC_REGNUM)
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(compare:CC (const_int 0) (match_dup 1)))
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(set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))])
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(set (match_dup 2) (minus:SI (minus:SI (const_int 0) (match_dup 3))
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(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
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{
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operands[2] = gen_highpart (SImode, operands[0]);
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operands[0] = gen_lowpart (SImode, operands[0]);
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operands[3] = gen_highpart (SImode, operands[1]);
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operands[1] = gen_lowpart (SImode, operands[1]);
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}
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[(set_attr "conds" "clob")
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(set_attr "length" "8")]
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)
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@ -4346,14 +4362,67 @@
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operands[2] = gen_rtx_REG (CCmode, CC_REGNUM);
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")
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(define_insn "*arm_abssi2"
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(define_insn_and_split "*arm_abssi2"
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[(set (match_operand:SI 0 "s_register_operand" "=r,&r")
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(abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_ARM"
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"@
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cmp\\t%0, #0\;rsblt\\t%0, %0, #0
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eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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/* if (which_alternative == 0) */
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if (REGNO(operands[0]) == REGNO(operands[1]))
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{
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/* Emit the pattern:
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cmp\\t%0, #0\;rsblt\\t%0, %0, #0
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[(set (reg:CC CC_REGNUM)
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(compare:CC (match_dup 0) (const_int 0)))
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(cond_exec (lt:CC (reg:CC CC_REGNUM) (const_int 0))
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(set (match_dup 0) (minus:SI (const_int 0) (match_dup 1))))]
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*/
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emit_insn (gen_rtx_SET (VOIDmode,
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gen_rtx_REG (CCmode, CC_REGNUM),
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gen_rtx_COMPARE (CCmode, operands[0], const0_rtx)));
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emit_insn (gen_rtx_COND_EXEC (VOIDmode,
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(gen_rtx_LT (SImode,
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gen_rtx_REG (CCmode, CC_REGNUM),
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const0_rtx)),
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(gen_rtx_SET (VOIDmode,
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operands[0],
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(gen_rtx_MINUS (SImode,
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const0_rtx,
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operands[1]))))));
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DONE;
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}
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else
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{
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/* Emit the pattern:
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alt1: eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31
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[(set (match_dup 0)
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(xor:SI (match_dup 1)
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(ashiftrt:SI (match_dup 1) (const_int 31))))
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(set (match_dup 0)
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(minus:SI (match_dup 0)
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(ashiftrt:SI (match_dup 1) (const_int 31))))]
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*/
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emit_insn (gen_rtx_SET (VOIDmode,
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operands[0],
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gen_rtx_XOR (SImode,
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gen_rtx_ASHIFTRT (SImode,
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operands[1],
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GEN_INT (31)),
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operands[1])));
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emit_insn (gen_rtx_SET (VOIDmode,
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operands[0],
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gen_rtx_MINUS (SImode,
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operands[0],
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gen_rtx_ASHIFTRT (SImode,
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operands[1],
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GEN_INT (31)))));
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DONE;
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}
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}
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[(set_attr "conds" "clob,*")
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(set_attr "shift" "1")
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(set_attr "predicable" "no, yes")
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@ -4374,14 +4443,56 @@
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[(set_attr "length" "6")]
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)
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(define_insn "*arm_neg_abssi2"
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(define_insn_and_split "*arm_neg_abssi2"
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[(set (match_operand:SI 0 "s_register_operand" "=r,&r")
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(neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_ARM"
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"@
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cmp\\t%0, #0\;rsbgt\\t%0, %0, #0
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eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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/* if (which_alternative == 0) */
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if (REGNO (operands[0]) == REGNO (operands[1]))
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{
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/* Emit the pattern:
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cmp\\t%0, #0\;rsbgt\\t%0, %0, #0
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*/
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emit_insn (gen_rtx_SET (VOIDmode,
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gen_rtx_REG (CCmode, CC_REGNUM),
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gen_rtx_COMPARE (CCmode, operands[0], const0_rtx)));
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emit_insn (gen_rtx_COND_EXEC (VOIDmode,
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gen_rtx_GT (SImode,
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gen_rtx_REG (CCmode, CC_REGNUM),
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const0_rtx),
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gen_rtx_SET (VOIDmode,
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operands[0],
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(gen_rtx_MINUS (SImode,
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const0_rtx,
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operands[1])))));
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}
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else
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{
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/* Emit the pattern:
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eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31
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*/
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emit_insn (gen_rtx_SET (VOIDmode,
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operands[0],
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gen_rtx_XOR (SImode,
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gen_rtx_ASHIFTRT (SImode,
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operands[1],
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GEN_INT (31)),
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operands[1])));
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emit_insn (gen_rtx_SET (VOIDmode,
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operands[0],
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gen_rtx_MINUS (SImode,
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gen_rtx_ASHIFTRT (SImode,
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operands[1],
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GEN_INT (31)),
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operands[0])));
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}
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DONE;
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}
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[(set_attr "conds" "clob,*")
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(set_attr "shift" "1")
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(set_attr "predicable" "no, yes")
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@ -7736,23 +7847,64 @@
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;; if-conversion can not reduce to a conditional compare, so we do
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;; that directly.
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(define_insn "*arm_cmpdi_insn"
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(define_insn_and_split "*arm_cmpdi_insn"
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[(set (reg:CC_NCV CC_REGNUM)
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(compare:CC_NCV (match_operand:DI 0 "s_register_operand" "r")
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(match_operand:DI 1 "arm_di_operand" "rDi")))
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(clobber (match_scratch:SI 2 "=r"))]
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"TARGET_32BIT"
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"cmp\\t%Q0, %Q1\;sbcs\\t%2, %R0, %R1"
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"#" ; "cmp\\t%Q0, %Q1\;sbcs\\t%2, %R0, %R1"
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"&& reload_completed"
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[(set (reg:CC CC_REGNUM)
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(compare:CC (match_dup 0) (match_dup 1)))
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(parallel [(set (reg:CC CC_REGNUM)
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(compare:CC (match_dup 3) (match_dup 4)))
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(set (match_dup 2)
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(minus:SI (match_dup 5)
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(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))])]
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{
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operands[3] = gen_highpart (SImode, operands[0]);
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operands[0] = gen_lowpart (SImode, operands[0]);
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if (CONST_INT_P (operands[1]))
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{
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operands[4] = GEN_INT (~INTVAL (gen_highpart_mode (SImode,
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DImode,
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operands[1])));
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operands[5] = gen_rtx_PLUS (SImode, operands[3], operands[4]);
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}
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else
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{
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operands[4] = gen_highpart (SImode, operands[1]);
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operands[5] = gen_rtx_MINUS (SImode, operands[3], operands[4]);
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}
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operands[1] = gen_lowpart (SImode, operands[1]);
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operands[2] = gen_lowpart (SImode, operands[2]);
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}
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[(set_attr "conds" "set")
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(set_attr "length" "8")]
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)
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(define_insn "*arm_cmpdi_unsigned"
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(define_insn_and_split "*arm_cmpdi_unsigned"
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[(set (reg:CC_CZ CC_REGNUM)
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(compare:CC_CZ (match_operand:DI 0 "s_register_operand" "r")
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(match_operand:DI 1 "arm_di_operand" "rDi")))]
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"TARGET_32BIT"
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"cmp\\t%R0, %R1\;it eq\;cmpeq\\t%Q0, %Q1"
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"#" ; "cmp\\t%R0, %R1\;it eq\;cmpeq\\t%Q0, %Q1"
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"&& reload_completed"
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[(set (reg:CC CC_REGNUM)
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(compare:CC (match_dup 2) (match_dup 3)))
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(cond_exec (eq:SI (reg:CC CC_REGNUM) (const_int 0))
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(set (reg:CC CC_REGNUM)
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(compare:CC (match_dup 0) (match_dup 1))))]
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{
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operands[2] = gen_highpart (SImode, operands[0]);
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operands[0] = gen_lowpart (SImode, operands[0]);
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if (CONST_INT_P (operands[1]))
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operands[3] = gen_highpart_mode (SImode, DImode, operands[1]);
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else
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operands[3] = gen_highpart (SImode, operands[1]);
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operands[1] = gen_lowpart (SImode, operands[1]);
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}
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[(set_attr "conds" "set")
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(set_attr "length" "8")]
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)
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