mips.h (PROCESSOR_R4121): Rename to PROCESSOR_R4120.
* config/mips/mips.h (PROCESSOR_R4121): Rename to PROCESSOR_R4120. (TARGET_MIPS4121): Rename to TARGET_MIPS4120. * config/mips/mips.c (mips_cpu_info): Rename vr4121 to vr4120. * config/mips/mips.md: Apply same renaming here. From-SVN: r57687
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@ -1,3 +1,10 @@
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2002-10-01 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips.h (PROCESSOR_R4121): Rename to PROCESSOR_R4120.
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(TARGET_MIPS4121): Rename to TARGET_MIPS4120.
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* config/mips/mips.c (mips_cpu_info): Rename vr4121 to vr4120.
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* config/mips/mips.md: Apply same renaming here.
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2002-10-01 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips.c (PROCESSOR_R4320, TARGET_MIPS4320): Remove.
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@ -596,7 +596,7 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
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{ "r4000", PROCESSOR_R4000, 3 },
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{ "vr4100", PROCESSOR_R4100, 3 },
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{ "vr4111", PROCESSOR_R4111, 3 },
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{ "vr4121", PROCESSOR_R4121, 3 },
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{ "vr4120", PROCESSOR_R4120, 3 },
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{ "vr4300", PROCESSOR_R4300, 3 },
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{ "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
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{ "r4600", PROCESSOR_R4600, 3 },
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@ -64,7 +64,7 @@ enum processor_type {
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PROCESSOR_R4000,
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PROCESSOR_R4100,
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PROCESSOR_R4111,
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PROCESSOR_R4121,
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PROCESSOR_R4120,
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PROCESSOR_R4300,
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PROCESSOR_R4600,
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PROCESSOR_R4650,
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@ -357,7 +357,7 @@ extern void sbss_section PARAMS ((void));
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#define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
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#define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
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#define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
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#define TARGET_MIPS4121 (mips_arch == PROCESSOR_R4121)
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#define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
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#define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
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#define TARGET_MIPS4KC (mips_arch == PROCESSOR_R4KC)
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#define TARGET_MIPS5KC (mips_arch == PROCESSOR_R5KC)
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@ -122,7 +122,7 @@
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;; ??? Fix everything that tests this attribute.
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(define_attr "cpu"
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"default,r3000,r3900,r6000,r4000,r4100,r4121,r4300,r4600,r4650,r5000,r5400,r5500,r8000,sr71000,r4kc,r5kc,r20kc"
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"default,r3000,r3900,r6000,r4000,r4100,r4120,r4300,r4600,r4650,r5000,r5400,r5500,r8000,sr71000,r4kc,r5kc,r20kc"
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(const (symbol_ref "mips_cpu_attr")))
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;; Does the instruction have a mandatory delay slot?
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@ -207,12 +207,12 @@
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(define_function_unit "memory" 1 0
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(and (eq_attr "type" "load")
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(eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4121,r4300,r5000"))
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(eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
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3 0)
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(define_function_unit "memory" 1 0
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(and (eq_attr "type" "load")
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(eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4121,r4300,r5000"))
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(eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
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2 0)
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(define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
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@ -225,7 +225,7 @@
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "imul,imadd")
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(eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4121,r4300,r5000"))
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(eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
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17 17)
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;; On them mips16, we want to stronly discourage a mult from appearing
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@ -252,12 +252,12 @@
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "imul,imadd")
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(and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100,r4121")))
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(and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100,r4120")))
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1 1)
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "imul,imadd")
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(and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100,r4121")))
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(and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100,r4120")))
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4 4)
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(define_function_unit "imuldiv" 1 0
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@ -277,7 +277,7 @@
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4121,r4300,r5000"))
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(eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
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38 38)
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(define_function_unit "imuldiv" 1 0
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@ -298,12 +298,12 @@
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "idiv")
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(and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100,r4121")))
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(and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100,r4120")))
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35 35)
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "idiv")
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(and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100,r4121")))
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(and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100,r4120")))
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67 67)
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(define_function_unit "imuldiv" 1 0
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