i386-common.c (OPTION_MASK_ISA_AVX512F_SET): New.
* common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512F_SET): New. (OPTION_MASK_ISA_AVX512CD_SET): Ditto. (OPTION_MASK_ISA_AVX512PF_SET): Ditto. (OPTION_MASK_ISA_AVX512ER_SET): Ditto. (OPTION_MASK_ISA_AVX2_UNSET): Update. (OPTION_MASK_ISA_AVX512F_UNSET): New. (OPTION_MASK_ISA_AVX512CD_UNSET): Ditto. (OPTION_MASK_ISA_AVX512PF_UNSET): Ditto. (OPTION_MASK_ISA_AVX512ER_UNSET): Ditto. (ix86_handle_option): Handle OPT_mavx512f, OPT_mavx512cd, OPT_mavx512pf, OPT_mavx512er cases. * config/i386/constraints.md (v): New constraint. (Yi, Yj): Replace SSE_REGS with ALL_SSE_REGS. * config/i386/cpuid.h (bit_AVX512F, bit_AVX512PF, bit_AVX512ER) (bit_AVX512CD): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect AVX512F, AVX512ER, AVX512PF, AVX512CD features. * config/i386/i386-c.c (ix86_target_macros_internal): Conditionally define __AVX512F__, __AVX512ER__, __AVX512CD__, __AVX512PF__. * config/i386/i386-modes.def (VECTOR_MODES (INT, 128)) (VECTOR_MODES (FLOAT, 128), INT_MODE (XI, 64)): New modes. * config/i386/i386.c (regclass_map, dbx_register_map) (dbx64_register_map, svr4_dbx_register_map): Add new SSE registers. (gate_insert_vzeroupper): Disable vzeroupper for TARGET_AVX512F. (ix86_target_string): Define -mavx512f, -mavx512er, -mavx512cd, -mavx512pf options. (ix86_option_override_internal): Define PTA_AVX512F, PTA_AVX512ER, PTA_AVX512PF, PTA_AVX512CD. Handle -mavx512f, -mavx512er, -mavx512cd, -mavx512pf options. Fix formatting. (ix86_conditional_register_usage): Squash EXT_REX_SSE_REGs for 32-bit targets. Squash EVEX_SSE_REGS if AVX512F is disabled. (ix86_valid_target_attribute_inner_p): Handle -mavx512f, -mavx512er, -mavx512cd, -mavx512pf options. (standard_sse_constant_opcode): Add vpternlogd for 512-bit modes. (print_reg, ix86_print_operand): Handle 'g' to output 512-bit operands. (ix86_preferred_output_reload_class): Replace SSE_REGS with ALL_SSE_REGS. (ix86_hard_regno_mode_ok): Support 512-bit registers. (ix86_set_reg_reg_cost): Ditto. (x86_order_regs_for_local_alloc): Ditto. (MAX_VECT_LEN): Extend to 64-byte. (ix86_spill_class): Replace SSE_REGS with ALL_SSE_REGS. * config/i386/i386.h (TARGET_AVX512F, TARGET_AVX512PF) (TARGET_AVX512ER, TARGET_AVX512CD): New. (BIGGEST_ALIGNMENT): Extend to 512-bits. (FIRST_PSEUDO_REGISTER, FIXED_REGISTERS): Add new registers. (CALL_USED_REGISTERS, REG_ALLOC_ORDER): Likewise. (VALID_AVX512F_SCALAR_MODE, VALID_AVX512F_REG_MODE): New. (SSE_REG_MODE_P): Support new modes. (FIRST_MMX_REG, FIRST_REX_INT_REG, FIRST_REX_SSE_REG): Add comments. (FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG): New. (reg_class, REG_CLASS_NAMES): Add EVEX_SSE_REGS, ALL_SSE_REGS. (SSE_CLASS_P, MAYBE_SSE_CLASS_P): Replace SSE_REGS with ALL_SSE_REGS. (REG_CLASS_CONTENTS): Add new registers. (SSE_REGNO_P, SSE_REGNO, HARD_REGNO_RENAME_OK): Support new registers. (EXT_REX_SSE_REGNO_P): New. (HI_REGISTER_NAMES): Add new registers. * config/i386/i386.md: Define constants for new registers. (mode): Add new 512-bit modes. (prefix): Support evex prefix. (isa): Support avx512f, noavx512f, fma_avx512f. (ssemodesuffix): Add new 512-bit modes. (movxi): New. (*movxi_internal_avx512f): Ditto. (*movdi_internal): Replace constraint "x" with the new constraint "v". Support MODE_XI. (*movsi_internal): Likewise. (*movdf_internal): Likewise. (*movsf_internal): Likewise. (*fop_<mode>_comm_sse): Replace constraint "x" with new constraint "v". (<code><mode>3): Likewise. * config/i386/i386.opt (mavx512f, mavx512pf, mavx512er, mavx512cd): New. * config/i386/mmx.md (*mov<mode>_internal): Replace constraint "x" with the new constraint "v". * config/i386/sse.md (*mov<mode>_internal): Support new registers and modes. (<sse>_loadu<ssemodesuffix><avxsizesuffix>): Replace constraint "x" with the new constraint "v". (<sse2>_loaddqu<avxsizesuffix>): Likewise. (<sse2>_storedqu<avxsizesuffix>): Likewise. (*<plusminus_insn><mode>3): Likewise. (<sse>_vm<plusminus_insn><mode>3): Likewise. (*mul<mode>3): Likewise. (<sse>_vmmul<mode>3): Likewise. (<sse>_div<mode>3): Likewise. (<sse>_vmdiv<mode>3): Likewise. (<sse>_sqrt<mode>2): Likewise. (<sse>_vmsqrt<mode>2): Likewise. (*<code><mode>3_finite): Likewise. (*<code><mode>3) <smaxmin>: Likewise. (<sse>_vm<code><mode>3): Likewise. (*<code><mode>3) <any_logic>: Likewise. (*fma_fmadd_<mode>): Likewise. (*fma_fmsub_<mode>): Likewise. (*fma_fnmadd_<mode>): Likewise. (*fma_fnmsub_<mode>): Likewise. (*fma_fmaddsub_<mode>): Likewise. (*fma_fmsubadd_<mode>): Likewise. (*fmai_fmadd_<mode>): Likewise. (*fmai_fmsub_<mode>): Likewise. (*fmai_fnmadd_<mode>): Likewise. (*fmai_fnmsub_<mode>): Likewise. (sse_cvtsi2ss): Likewise. (sse_cvtsi2ssq): Likewise. (sse_cvtss2si): Likewise. (sse_cvtss2si_2): Likewise. (sse_cvtss2siq): Likewise. (sse_cvtss2siq_2): Likewise. (sse_cvttss2si): Likewise. (sse_cvtss2siq_2): Likewise. (float<sseintvecmodelower><mode>2): Likewise. (sse2_cvtsd2si_2): Likewise. (sse2_cvtsd2siq_2): Likewise. (*<plusminus_insn><mode>3): Likewise. (*<sse2_avx2>_<plusminus_insn><mode>3): Likewise. (*<sse4_1_avx2>_mul<mode>3): Likewise. (ashr<mode>3): Likewise. (<shift_insn><mode>3): Likewise. (avx2_<code><mode>3): Likewise. (*avx2_<code><mode>3): Likewise. (*andnot<mode>3): Likewise. (*<code><mode>3) <any_logic>: Likewise. (abs<mode>2): Likewise. (avx2_permvar<mode>): Likewise. (avx2_perm<mode>_1): Likewise. (*avx_vpermilp<mode>): Likewise. (avx_vpermilvar<mode>3): Likewise. (avx2_ashrv<mode>): Likewise. (avx2_<shift_insn>v<mode>): Likewise. * doc/invoke.texi: Document -mavx512f, -mavx512pf, -mavx512er, -mavx512cd. * doc/rtl.texi: Document XImode. Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com> Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com> Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com> Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com> Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com> Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com> Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com> Co-Authored-By: Sergey Lega <sergey.s.lega@intel.com> From-SVN: r201915
This commit is contained in:
Alexander Ivchenko
Kirill Yukhin
parent
1b488e33b6
commit
3f97cb0b27
144
gcc/ChangeLog
144
gcc/ChangeLog
@ -1,3 +1,147 @@
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2013-08-22 Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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Sergey Lega <sergey.s.lega@intel.com>
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Anna Tikhonova <anna.tikhonova@intel.com>
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Ilya Tocar <ilya.tocar@intel.com>
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Andrey Turetskiy <andrey.turetskiy@intel.com>
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Ilya Verbin <ilya.verbin@intel.com>
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Kirill Yukhin <kirill.yukhin@intel.com>
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Michael Zolotukhin <michael.v.zolotukhin@intel.com>
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* common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512F_SET): New.
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(OPTION_MASK_ISA_AVX512CD_SET): Ditto.
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(OPTION_MASK_ISA_AVX512PF_SET): Ditto.
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(OPTION_MASK_ISA_AVX512ER_SET): Ditto.
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(OPTION_MASK_ISA_AVX2_UNSET): Update.
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(OPTION_MASK_ISA_AVX512F_UNSET): New.
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(OPTION_MASK_ISA_AVX512CD_UNSET): Ditto.
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(OPTION_MASK_ISA_AVX512PF_UNSET): Ditto.
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(OPTION_MASK_ISA_AVX512ER_UNSET): Ditto.
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(ix86_handle_option): Handle OPT_mavx512f, OPT_mavx512cd,
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OPT_mavx512pf, OPT_mavx512er cases.
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* config/i386/constraints.md (v): New constraint.
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(Yi, Yj): Replace SSE_REGS with ALL_SSE_REGS.
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* config/i386/cpuid.h (bit_AVX512F, bit_AVX512PF, bit_AVX512ER)
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(bit_AVX512CD): New.
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* config/i386/driver-i386.c (host_detect_local_cpu): Detect
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AVX512F, AVX512ER, AVX512PF, AVX512CD features.
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* config/i386/i386-c.c (ix86_target_macros_internal):
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Conditionally define __AVX512F__, __AVX512ER__, __AVX512CD__,
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__AVX512PF__.
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* config/i386/i386-modes.def (VECTOR_MODES (INT, 128))
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(VECTOR_MODES (FLOAT, 128), INT_MODE (XI, 64)): New modes.
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* config/i386/i386.c (regclass_map, dbx_register_map)
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(dbx64_register_map, svr4_dbx_register_map): Add new SSE registers.
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(gate_insert_vzeroupper): Disable vzeroupper for TARGET_AVX512F.
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(ix86_target_string): Define -mavx512f, -mavx512er, -mavx512cd,
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-mavx512pf options.
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(ix86_option_override_internal): Define PTA_AVX512F, PTA_AVX512ER,
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PTA_AVX512PF, PTA_AVX512CD. Handle -mavx512f, -mavx512er, -mavx512cd,
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-mavx512pf options. Fix formatting.
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(ix86_conditional_register_usage): Squash EXT_REX_SSE_REGs for 32-bit
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targets. Squash EVEX_SSE_REGS if AVX512F is disabled.
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(ix86_valid_target_attribute_inner_p): Handle -mavx512f, -mavx512er,
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-mavx512cd, -mavx512pf options.
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(standard_sse_constant_opcode): Add vpternlogd for 512-bit modes.
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(print_reg, ix86_print_operand): Handle 'g' to output 512-bit operands.
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(ix86_preferred_output_reload_class): Replace SSE_REGS with
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ALL_SSE_REGS.
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(ix86_hard_regno_mode_ok): Support 512-bit registers.
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(ix86_set_reg_reg_cost): Ditto.
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(x86_order_regs_for_local_alloc): Ditto.
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(MAX_VECT_LEN): Extend to 64-byte.
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(ix86_spill_class): Replace SSE_REGS with ALL_SSE_REGS.
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* config/i386/i386.h (TARGET_AVX512F, TARGET_AVX512PF)
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(TARGET_AVX512ER, TARGET_AVX512CD): New.
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(BIGGEST_ALIGNMENT): Extend to 512-bits.
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(FIRST_PSEUDO_REGISTER, FIXED_REGISTERS): Add new registers.
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(CALL_USED_REGISTERS, REG_ALLOC_ORDER): Likewise.
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(VALID_AVX512F_SCALAR_MODE, VALID_AVX512F_REG_MODE): New.
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(SSE_REG_MODE_P): Support new modes.
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(FIRST_MMX_REG, FIRST_REX_INT_REG, FIRST_REX_SSE_REG): Add comments.
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(FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG): New.
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(reg_class, REG_CLASS_NAMES): Add EVEX_SSE_REGS, ALL_SSE_REGS.
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(SSE_CLASS_P, MAYBE_SSE_CLASS_P): Replace SSE_REGS with ALL_SSE_REGS.
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(REG_CLASS_CONTENTS): Add new registers.
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(SSE_REGNO_P, SSE_REGNO, HARD_REGNO_RENAME_OK): Support new registers.
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(EXT_REX_SSE_REGNO_P): New.
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(HI_REGISTER_NAMES): Add new registers.
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* config/i386/i386.md: Define constants for new registers.
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(mode): Add new 512-bit modes.
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(prefix): Support evex prefix.
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(isa): Support avx512f, noavx512f, fma_avx512f.
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(ssemodesuffix): Add new 512-bit modes.
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(movxi): New.
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(*movxi_internal_avx512f): Ditto.
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(*movdi_internal): Replace constraint "x" with the new constraint "v".
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Support MODE_XI.
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(*movsi_internal): Likewise.
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(*movdf_internal): Likewise.
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(*movsf_internal): Likewise.
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(*fop_<mode>_comm_sse): Replace constraint "x" with new constraint "v".
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(<code><mode>3): Likewise.
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* config/i386/i386.opt (mavx512f, mavx512pf, mavx512er, mavx512cd): New.
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* config/i386/mmx.md (*mov<mode>_internal): Replace constraint "x"
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with the new constraint "v".
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* config/i386/sse.md (*mov<mode>_internal): Support new registers and
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modes.
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(<sse>_loadu<ssemodesuffix><avxsizesuffix>): Replace constraint "x"
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with the new constraint "v".
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(<sse2>_loaddqu<avxsizesuffix>): Likewise.
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(<sse2>_storedqu<avxsizesuffix>): Likewise.
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(*<plusminus_insn><mode>3): Likewise.
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(<sse>_vm<plusminus_insn><mode>3): Likewise.
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(*mul<mode>3): Likewise.
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(<sse>_vmmul<mode>3): Likewise.
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(<sse>_div<mode>3): Likewise.
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(<sse>_vmdiv<mode>3): Likewise.
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(<sse>_sqrt<mode>2): Likewise.
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(<sse>_vmsqrt<mode>2): Likewise.
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(*<code><mode>3_finite): Likewise.
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(*<code><mode>3) <smaxmin>: Likewise.
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(<sse>_vm<code><mode>3): Likewise.
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(*<code><mode>3) <any_logic>: Likewise.
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(*fma_fmadd_<mode>): Likewise.
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(*fma_fmsub_<mode>): Likewise.
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(*fma_fnmadd_<mode>): Likewise.
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(*fma_fnmsub_<mode>): Likewise.
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(*fma_fmaddsub_<mode>): Likewise.
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(*fma_fmsubadd_<mode>): Likewise.
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(*fmai_fmadd_<mode>): Likewise.
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(*fmai_fmsub_<mode>): Likewise.
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(*fmai_fnmadd_<mode>): Likewise.
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(*fmai_fnmsub_<mode>): Likewise.
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(sse_cvtsi2ss): Likewise.
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(sse_cvtsi2ssq): Likewise.
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(sse_cvtss2si): Likewise.
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(sse_cvtss2si_2): Likewise.
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(sse_cvtss2siq): Likewise.
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(sse_cvtss2siq_2): Likewise.
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(sse_cvttss2si): Likewise.
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(sse_cvtss2siq_2): Likewise.
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(float<sseintvecmodelower><mode>2): Likewise.
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(sse2_cvtsd2si_2): Likewise.
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(sse2_cvtsd2siq_2): Likewise.
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(*<plusminus_insn><mode>3): Likewise.
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(*<sse2_avx2>_<plusminus_insn><mode>3): Likewise.
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(*<sse4_1_avx2>_mul<mode>3): Likewise.
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(ashr<mode>3): Likewise.
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(<shift_insn><mode>3): Likewise.
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(avx2_<code><mode>3): Likewise.
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(*avx2_<code><mode>3): Likewise.
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(*andnot<mode>3): Likewise.
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(*<code><mode>3) <any_logic>: Likewise.
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(abs<mode>2): Likewise.
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(avx2_permvar<mode>): Likewise.
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(avx2_perm<mode>_1): Likewise.
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(*avx_vpermilp<mode>): Likewise.
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(avx_vpermilvar<mode>3): Likewise.
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(avx2_ashrv<mode>): Likewise.
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(avx2_<shift_insn>v<mode>): Likewise.
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* doc/invoke.texi: Document -mavx512f, -mavx512pf, -mavx512er,
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-mavx512cd.
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* doc/rtl.texi: Document XImode.
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2013-08-21 Jeff Law <law@redhat.com>
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* tree-flow.h (register_jump_thread): Pass vector of edges
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@ -57,6 +57,14 @@ along with GCC; see the file COPYING3. If not see
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#define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
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#define OPTION_MASK_ISA_XSAVEOPT_SET \
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(OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE)
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#define OPTION_MASK_ISA_AVX512F_SET \
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(OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
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#define OPTION_MASK_ISA_AVX512CD_SET \
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(OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
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#define OPTION_MASK_ISA_AVX512PF_SET \
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(OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET)
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#define OPTION_MASK_ISA_AVX512ER_SET \
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(OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET)
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#define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
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#define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
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#define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
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@ -128,11 +136,18 @@ along with GCC; see the file COPYING3. If not see
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| OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
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| OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_XSAVE_UNSET)
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#define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
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#define OPTION_MASK_ISA_AVX2_UNSET OPTION_MASK_ISA_AVX2
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#define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
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#define OPTION_MASK_ISA_XSAVE_UNSET \
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(OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET)
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#define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
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#define OPTION_MASK_ISA_AVX2_UNSET \
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(OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
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#define OPTION_MASK_ISA_AVX512F_UNSET \
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(OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
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| OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET)
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#define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
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#define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF
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#define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER
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#define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
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#define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
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#define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
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@ -313,6 +328,58 @@ ix86_handle_option (struct gcc_options *opts,
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}
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return true;
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case OPT_mavx512f:
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if (value)
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{
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opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
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opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
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}
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else
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{
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opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET;
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opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
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}
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return true;
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case OPT_mavx512cd:
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if (value)
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{
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opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET;
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opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET;
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}
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else
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{
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opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
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opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
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}
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return true;
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case OPT_mavx512pf:
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if (value)
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{
|
||||
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF_SET;
|
||||
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512PF_UNSET;
|
||||
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_UNSET;
|
||||
}
|
||||
return true;
|
||||
|
||||
case OPT_mavx512er:
|
||||
if (value)
|
||||
{
|
||||
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER_SET;
|
||||
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512ER_UNSET;
|
||||
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_UNSET;
|
||||
}
|
||||
return true;
|
||||
|
||||
case OPT_mfma:
|
||||
if (value)
|
||||
{
|
||||
|
||||
@ -19,7 +19,7 @@
|
||||
|
||||
;;; Unused letters:
|
||||
;;; B H T
|
||||
;;; h jk v
|
||||
;;; h jk
|
||||
|
||||
;; Integer register constraints.
|
||||
;; It is not necessary to define 'r' here.
|
||||
@ -101,11 +101,11 @@
|
||||
"First SSE register (@code{%xmm0}).")
|
||||
|
||||
(define_register_constraint "Yi"
|
||||
"TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC ? SSE_REGS : NO_REGS"
|
||||
"TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC ? ALL_SSE_REGS : NO_REGS"
|
||||
"@internal Any SSE register, when SSE2 and inter-unit moves to vector registers are enabled.")
|
||||
|
||||
(define_register_constraint "Yj"
|
||||
"TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_FROM_VEC ? SSE_REGS : NO_REGS"
|
||||
"TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_FROM_VEC ? ALL_SSE_REGS : NO_REGS"
|
||||
"@internal Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled.")
|
||||
|
||||
(define_register_constraint "Ym"
|
||||
@ -138,6 +138,9 @@
|
||||
"(ix86_fpmath & FPMATH_387) ? FLOAT_REGS : NO_REGS"
|
||||
"@internal Any x87 register when 80387 FP arithmetic is enabled.")
|
||||
|
||||
(define_register_constraint "v" "TARGET_SSE ? ALL_SSE_REGS : NO_REGS"
|
||||
"Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).")
|
||||
|
||||
(define_constraint "z"
|
||||
"@internal Constant call address operand."
|
||||
(match_operand 0 "constant_call_address_operand"))
|
||||
|
||||
@ -71,8 +71,12 @@
|
||||
#define bit_AVX2 (1 << 5)
|
||||
#define bit_BMI2 (1 << 8)
|
||||
#define bit_RTM (1 << 11)
|
||||
#define bit_AVX512F (1 << 16)
|
||||
#define bit_RDSEED (1 << 18)
|
||||
#define bit_ADX (1 << 19)
|
||||
#define bit_AVX512PF (1 << 26)
|
||||
#define bit_AVX512ER (1 << 27)
|
||||
#define bit_AVX512CD (1 << 28)
|
||||
|
||||
/* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
|
||||
#define bit_XSAVEOPT (1 << 0)
|
||||
|
||||
@ -390,6 +390,8 @@ const char *host_detect_local_cpu (int argc, const char **argv)
|
||||
unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
|
||||
unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0;
|
||||
unsigned int has_osxsave = 0, has_fxsr = 0, has_xsave = 0, has_xsaveopt = 0;
|
||||
unsigned int has_avx512er = 0, has_avx512pf = 0, has_avx512cd = 0;
|
||||
unsigned int has_avx512f = 0;
|
||||
|
||||
bool arch;
|
||||
|
||||
@ -461,6 +463,10 @@ const char *host_detect_local_cpu (int argc, const char **argv)
|
||||
has_fsgsbase = ebx & bit_FSGSBASE;
|
||||
has_rdseed = ebx & bit_RDSEED;
|
||||
has_adx = ebx & bit_ADX;
|
||||
has_avx512f = ebx & bit_AVX512F;
|
||||
has_avx512er = ebx & bit_AVX512ER;
|
||||
has_avx512pf = ebx & bit_AVX512PF;
|
||||
has_avx512cd = ebx & bit_AVX512CD;
|
||||
}
|
||||
|
||||
if (max_level >= 13)
|
||||
@ -828,13 +834,18 @@ const char *host_detect_local_cpu (int argc, const char **argv)
|
||||
const char *fxsr = has_fxsr ? " -mfxsr" : " -mno-fxsr";
|
||||
const char *xsave = has_xsave ? " -mxsave" : " -mno-xsave";
|
||||
const char *xsaveopt = has_xsaveopt ? " -mxsaveopt" : " -mno-xsaveopt";
|
||||
const char *avx512f = has_avx512f ? " -mavx512f" : " -mno-avx512f";
|
||||
const char *avx512er = has_avx512er ? " -mavx512er" : " -mno-avx512er";
|
||||
const char *avx512cd = has_avx512cd ? " -mavx512cd" : " -mno-avx512cd";
|
||||
const char *avx512pf = has_avx512pf ? " -mavx512pf" : " -mno-avx512pf";
|
||||
|
||||
options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
|
||||
sse4a, cx16, sahf, movbe, aes, pclmul,
|
||||
popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
|
||||
tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
|
||||
hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx,
|
||||
fxsr, xsave, xsaveopt, NULL);
|
||||
fxsr, xsave, xsaveopt, avx512f, avx512er,
|
||||
avx512cd, avx512pf, NULL);
|
||||
}
|
||||
|
||||
done:
|
||||
|
||||
@ -306,6 +306,14 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
|
||||
def_or_undef (parse_in, "__AVX__");
|
||||
if (isa_flag & OPTION_MASK_ISA_AVX2)
|
||||
def_or_undef (parse_in, "__AVX2__");
|
||||
if (isa_flag & OPTION_MASK_ISA_AVX512F)
|
||||
def_or_undef (parse_in, "__AVX512F__");
|
||||
if (isa_flag & OPTION_MASK_ISA_AVX512ER)
|
||||
def_or_undef (parse_in, "__AVX512ER__");
|
||||
if (isa_flag & OPTION_MASK_ISA_AVX512CD)
|
||||
def_or_undef (parse_in, "__AVX512CD__");
|
||||
if (isa_flag & OPTION_MASK_ISA_AVX512PF)
|
||||
def_or_undef (parse_in, "__AVX512PF__");
|
||||
if (isa_flag & OPTION_MASK_ISA_FMA)
|
||||
def_or_undef (parse_in, "__FMA__");
|
||||
if (isa_flag & OPTION_MASK_ISA_RTM)
|
||||
|
||||
@ -76,16 +76,19 @@ VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */
|
||||
VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */
|
||||
VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */
|
||||
VECTOR_MODES (INT, 64); /* V64QI V32HI V16SI V8DI */
|
||||
VECTOR_MODES (INT, 128); /* V128QI V64HI V32SI V16DI */
|
||||
VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */
|
||||
VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */
|
||||
VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */
|
||||
VECTOR_MODES (FLOAT, 64); /* V32HF V16SF V8DF */
|
||||
VECTOR_MODES (FLOAT, 128); /* V64HF V32SF V16DF */
|
||||
VECTOR_MODE (INT, TI, 1); /* V1TI */
|
||||
VECTOR_MODE (INT, DI, 1); /* V1DI */
|
||||
VECTOR_MODE (INT, SI, 1); /* V1SI */
|
||||
VECTOR_MODE (INT, QI, 2); /* V2QI */
|
||||
|
||||
INT_MODE (OI, 32);
|
||||
INT_MODE (XI, 64);
|
||||
|
||||
/* The symbol Pmode stands for one of the above machine modes (usually SImode).
|
||||
The tm.h file specifies which one. It is not a distinct mode. */
|
||||
|
||||
@ -2027,6 +2027,11 @@ enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
|
||||
/* SSE REX registers */
|
||||
SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
|
||||
SSE_REGS, SSE_REGS,
|
||||
/* AVX-512 SSE registers */
|
||||
EVEX_SSE_REGS, EVEX_SSE_REGS, EVEX_SSE_REGS, EVEX_SSE_REGS,
|
||||
EVEX_SSE_REGS, EVEX_SSE_REGS, EVEX_SSE_REGS, EVEX_SSE_REGS,
|
||||
EVEX_SSE_REGS, EVEX_SSE_REGS, EVEX_SSE_REGS, EVEX_SSE_REGS,
|
||||
EVEX_SSE_REGS, EVEX_SSE_REGS, EVEX_SSE_REGS, EVEX_SSE_REGS,
|
||||
};
|
||||
|
||||
/* The "default" register map used in 32bit mode. */
|
||||
@ -2040,6 +2045,8 @@ int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
|
||||
29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* AVX-512 registers 16-23*/
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* AVX-512 registers 24-31*/
|
||||
};
|
||||
|
||||
/* The "default" register map used in 64bit mode. */
|
||||
@ -2053,6 +2060,8 @@ int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
|
||||
41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
|
||||
8,9,10,11,12,13,14,15, /* extended integer registers */
|
||||
25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
|
||||
67, 68, 69, 70, 71, 72, 73, 74, /* AVX-512 registers 16-23 */
|
||||
75, 76, 77, 78, 79, 80, 81, 82, /* AVX-512 registers 24-31 */
|
||||
};
|
||||
|
||||
/* Define the register numbers to be used in Dwarf debugging information.
|
||||
@ -2118,6 +2127,8 @@ int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
|
||||
29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* AVX-512 registers 16-23*/
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* AVX-512 registers 24-31*/
|
||||
};
|
||||
|
||||
/* Define parameter passing and return registers. */
|
||||
@ -2417,7 +2428,7 @@ static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
|
||||
static bool
|
||||
gate_insert_vzeroupper (void)
|
||||
{
|
||||
return TARGET_AVX && TARGET_VZEROUPPER;
|
||||
return TARGET_AVX && !TARGET_AVX512F && TARGET_VZEROUPPER;
|
||||
}
|
||||
|
||||
static unsigned int
|
||||
@ -2507,6 +2518,10 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch,
|
||||
{ "-mfma", OPTION_MASK_ISA_FMA },
|
||||
{ "-mxop", OPTION_MASK_ISA_XOP },
|
||||
{ "-mlwp", OPTION_MASK_ISA_LWP },
|
||||
{ "-mavx512f", OPTION_MASK_ISA_AVX512F },
|
||||
{ "-mavx512er", OPTION_MASK_ISA_AVX512ER },
|
||||
{ "-mavx512cd", OPTION_MASK_ISA_AVX512CD },
|
||||
{ "-mavx512pf", OPTION_MASK_ISA_AVX512PF },
|
||||
{ "-msse4a", OPTION_MASK_ISA_SSE4A },
|
||||
{ "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
|
||||
{ "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
|
||||
@ -3026,6 +3041,10 @@ ix86_option_override_internal (bool main_args_p)
|
||||
#define PTA_FXSR (HOST_WIDE_INT_1 << 37)
|
||||
#define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
|
||||
#define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
|
||||
#define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
|
||||
#define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
|
||||
#define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
|
||||
#define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
|
||||
|
||||
/* if this reaches 64, need to widen struct pta flags below */
|
||||
|
||||
@ -3547,6 +3566,18 @@ ix86_option_override_internal (bool main_args_p)
|
||||
if (processor_alias_table[i].flags & PTA_XSAVEOPT
|
||||
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVEOPT))
|
||||
ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT;
|
||||
if (processor_alias_table[i].flags & PTA_AVX512F
|
||||
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512F))
|
||||
ix86_isa_flags |= OPTION_MASK_ISA_AVX512F;
|
||||
if (processor_alias_table[i].flags & PTA_AVX512ER
|
||||
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512ER))
|
||||
ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER;
|
||||
if (processor_alias_table[i].flags & PTA_AVX512PF
|
||||
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512PF))
|
||||
ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF;
|
||||
if (processor_alias_table[i].flags & PTA_AVX512CD
|
||||
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512CD))
|
||||
ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD;
|
||||
if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
|
||||
x86_prefetch_sse = true;
|
||||
|
||||
@ -4007,22 +4038,22 @@ ix86_option_override_internal (bool main_args_p)
|
||||
TARGET_AVX with -fexpensive-optimizations and split 32-byte
|
||||
AVX unaligned load/store. */
|
||||
if (!optimize_size)
|
||||
{
|
||||
if (flag_expensive_optimizations
|
||||
&& !(target_flags_explicit & MASK_VZEROUPPER))
|
||||
{
|
||||
if (flag_expensive_optimizations
|
||||
&& !(target_flags_explicit & MASK_VZEROUPPER))
|
||||
target_flags |= MASK_VZEROUPPER;
|
||||
if ((x86_avx256_split_unaligned_load & ix86_tune_mask)
|
||||
&& !(target_flags_explicit & MASK_AVX256_SPLIT_UNALIGNED_LOAD))
|
||||
if ((x86_avx256_split_unaligned_load & ix86_tune_mask)
|
||||
&& !(target_flags_explicit & MASK_AVX256_SPLIT_UNALIGNED_LOAD))
|
||||
target_flags |= MASK_AVX256_SPLIT_UNALIGNED_LOAD;
|
||||
if ((x86_avx256_split_unaligned_store & ix86_tune_mask)
|
||||
&& !(target_flags_explicit & MASK_AVX256_SPLIT_UNALIGNED_STORE))
|
||||
if ((x86_avx256_split_unaligned_store & ix86_tune_mask)
|
||||
&& !(target_flags_explicit & MASK_AVX256_SPLIT_UNALIGNED_STORE))
|
||||
target_flags |= MASK_AVX256_SPLIT_UNALIGNED_STORE;
|
||||
/* Enable 128-bit AVX instruction generation
|
||||
for the auto-vectorizer. */
|
||||
if (TARGET_AVX128_OPTIMAL
|
||||
&& !(target_flags_explicit & MASK_PREFER_AVX128))
|
||||
/* Enable 128-bit AVX instruction generation
|
||||
for the auto-vectorizer. */
|
||||
if (TARGET_AVX128_OPTIMAL
|
||||
&& !(target_flags_explicit & MASK_PREFER_AVX128))
|
||||
target_flags |= MASK_PREFER_AVX128;
|
||||
}
|
||||
}
|
||||
|
||||
if (ix86_recip_name)
|
||||
{
|
||||
@ -4143,6 +4174,8 @@ ix86_conditional_register_usage (void)
|
||||
fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
|
||||
for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
|
||||
fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
|
||||
for (i = FIRST_EXT_REX_SSE_REG; i <= LAST_EXT_REX_SSE_REG; i++)
|
||||
fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
|
||||
}
|
||||
|
||||
/* See the definition of CALL_USED_REGISTERS in i386.h. */
|
||||
@ -4183,6 +4216,11 @@ ix86_conditional_register_usage (void)
|
||||
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
|
||||
if (TEST_HARD_REG_BIT (reg_class_contents[(int)FLOAT_REGS], i))
|
||||
fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
|
||||
|
||||
/* If AVX512F is disabled, squash the registers. */
|
||||
if (! TARGET_AVX512F)
|
||||
for (i = FIRST_EXT_REX_SSE_REG; i < LAST_EXT_REX_SSE_REG; i++)
|
||||
fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
|
||||
}
|
||||
|
||||
|
||||
@ -4322,6 +4360,10 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[],
|
||||
IX86_ATTR_ISA ("aes", OPT_maes),
|
||||
IX86_ATTR_ISA ("avx", OPT_mavx),
|
||||
IX86_ATTR_ISA ("avx2", OPT_mavx2),
|
||||
IX86_ATTR_ISA ("avx512f", OPT_mavx512f),
|
||||
IX86_ATTR_ISA ("avx512pf", OPT_mavx512pf),
|
||||
IX86_ATTR_ISA ("avx512er", OPT_mavx512er),
|
||||
IX86_ATTR_ISA ("avx512cd", OPT_mavx512cd),
|
||||
IX86_ATTR_ISA ("mmx", OPT_mmmx),
|
||||
IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
|
||||
IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
|
||||
@ -8648,6 +8690,10 @@ standard_sse_constant_opcode (rtx insn, rtx x)
|
||||
}
|
||||
|
||||
case 2:
|
||||
if (get_attr_mode (insn) == MODE_XI
|
||||
|| get_attr_mode (insn) == MODE_V8DF
|
||||
|| get_attr_mode (insn) == MODE_V16SF)
|
||||
return "vpternlogd\t{$0xFF, %g0, %g0, %g0|%g0, %g0, %g0, 0xFF}";
|
||||
if (TARGET_AVX)
|
||||
return "vpcmpeqd\t%0, %0, %0";
|
||||
else
|
||||
@ -14173,6 +14219,7 @@ put_condition_code (enum rtx_code code, enum machine_mode mode, bool reverse,
|
||||
If CODE is 'q', pretend the mode is DImode.
|
||||
If CODE is 'x', pretend the mode is V4SFmode.
|
||||
If CODE is 't', pretend the mode is V8SFmode.
|
||||
If CODE is 'g', pretend the mode is V16SFmode.
|
||||
If CODE is 'h', pretend the reg is the 'high' byte register.
|
||||
If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
|
||||
If CODE is 'd', duplicate the operand for AVX instruction.
|
||||
@ -14218,6 +14265,8 @@ print_reg (rtx x, int code, FILE *file)
|
||||
code = 16;
|
||||
else if (code == 't')
|
||||
code = 32;
|
||||
else if (code == 'g')
|
||||
code = 64;
|
||||
else
|
||||
code = GET_MODE_SIZE (GET_MODE (x));
|
||||
|
||||
@ -14291,6 +14340,14 @@ print_reg (rtx x, int code, FILE *file)
|
||||
fputs (hi_reg_name[regno] + 1, file);
|
||||
return;
|
||||
}
|
||||
case 64:
|
||||
if (SSE_REG_P (x))
|
||||
{
|
||||
gcc_assert (!duplicated);
|
||||
putc ('z', file);
|
||||
fputs (hi_reg_name[REGNO (x)] + 1, file);
|
||||
return;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
gcc_unreachable ();
|
||||
@ -14364,6 +14421,7 @@ get_some_local_dynamic_name (void)
|
||||
q -- likewise, print the DImode name of the register.
|
||||
x -- likewise, print the V4SFmode name of the register.
|
||||
t -- likewise, print the V8SFmode name of the register.
|
||||
g -- likewise, print the V16SFmode name of the register.
|
||||
h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
|
||||
y -- print "st(0)" instead of "st" as a register.
|
||||
d -- print duplicated register operand for AVX instruction.
|
||||
@ -14593,6 +14651,7 @@ ix86_print_operand (FILE *file, rtx x, int code)
|
||||
case 'q':
|
||||
case 'h':
|
||||
case 't':
|
||||
case 'g':
|
||||
case 'y':
|
||||
case 'x':
|
||||
case 'X':
|
||||
@ -14901,6 +14960,7 @@ ix86_print_operand (FILE *file, rtx x, int code)
|
||||
size = "XMMWORD";
|
||||
break;
|
||||
case 32: size = "YMMWORD"; break;
|
||||
case 64: size = "ZMMWORD"; break;
|
||||
default:
|
||||
gcc_unreachable ();
|
||||
}
|
||||
@ -33898,7 +33958,7 @@ ix86_preferred_output_reload_class (rtx x, reg_class_t regclass)
|
||||
alternative: if reload cannot do this, it will still use its choice. */
|
||||
mode = GET_MODE (x);
|
||||
if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
|
||||
return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
|
||||
return MAYBE_SSE_CLASS_P (regclass) ? ALL_SSE_REGS : NO_REGS;
|
||||
|
||||
if (X87_FLOAT_MODE_P (mode))
|
||||
{
|
||||
@ -34365,8 +34425,23 @@ ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
|
||||
{
|
||||
/* We implement the move patterns for all vector modes into and
|
||||
out of SSE registers, even when no operation instructions
|
||||
are available. OImode move is available only when AVX is
|
||||
enabled. */
|
||||
are available. */
|
||||
|
||||
/* For AVX-512 we allow, regardless of regno:
|
||||
- XI mode
|
||||
- any of 512-bit wide vector mode
|
||||
- any scalar mode. */
|
||||
if (TARGET_AVX512F
|
||||
&& (mode == XImode
|
||||
|| VALID_AVX512F_REG_MODE (mode)
|
||||
|| VALID_AVX512F_SCALAR_MODE (mode)))
|
||||
return true;
|
||||
|
||||
/* xmm16-xmm31 are only available for AVX-512. */
|
||||
if (EXT_REX_SSE_REGNO_P (regno))
|
||||
return false;
|
||||
|
||||
/* OImode move is available only when AVX is enabled. */
|
||||
return ((TARGET_AVX && mode == OImode)
|
||||
|| VALID_AVX256_REG_MODE (mode)
|
||||
|| VALID_SSE_REG_MODE (mode)
|
||||
@ -34518,7 +34593,8 @@ ix86_set_reg_reg_cost (enum machine_mode mode)
|
||||
|
||||
case MODE_VECTOR_INT:
|
||||
case MODE_VECTOR_FLOAT:
|
||||
if ((TARGET_AVX && VALID_AVX256_REG_MODE (mode))
|
||||
if ((TARGET_AVX512F && VALID_AVX512F_REG_MODE (mode))
|
||||
|| (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
|
||||
|| (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
|
||||
|| (TARGET_SSE && VALID_SSE_REG_MODE (mode))
|
||||
|| (TARGET_MMX && VALID_MMX_REG_MODE (mode)))
|
||||
@ -35150,6 +35226,10 @@ x86_order_regs_for_local_alloc (void)
|
||||
for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
|
||||
reg_alloc_order [pos++] = i;
|
||||
|
||||
/* Extended REX SSE registers. */
|
||||
for (i = FIRST_EXT_REX_SSE_REG; i <= LAST_EXT_REX_SSE_REG; i++)
|
||||
reg_alloc_order [pos++] = i;
|
||||
|
||||
/* x87 registers. */
|
||||
if (TARGET_SSE_MATH)
|
||||
for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
|
||||
@ -36147,9 +36227,9 @@ x86_emit_floatuns (rtx operands[2])
|
||||
emit_label (donelab);
|
||||
}
|
||||
|
||||
/* AVX2 does support 32-byte integer vector operations,
|
||||
thus the longest vector we are faced with is V32QImode. */
|
||||
#define MAX_VECT_LEN 32
|
||||
/* AVX512F does support 64-byte integer vector operations,
|
||||
thus the longest vector we are faced with is V64QImode. */
|
||||
#define MAX_VECT_LEN 64
|
||||
|
||||
struct expand_vec_perm_d
|
||||
{
|
||||
@ -42686,7 +42766,7 @@ ix86_spill_class (reg_class_t rclass, enum machine_mode mode)
|
||||
if (TARGET_SSE && TARGET_GENERAL_REGS_SSE_SPILL && ! TARGET_MMX
|
||||
&& (mode == SImode || (TARGET_64BIT && mode == DImode))
|
||||
&& INTEGER_CLASS_P (rclass))
|
||||
return SSE_REGS;
|
||||
return ALL_SSE_REGS;
|
||||
return NO_REGS;
|
||||
}
|
||||
|
||||
|
||||
@ -51,6 +51,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
#define TARGET_SSE4_2 TARGET_ISA_SSE4_2
|
||||
#define TARGET_AVX TARGET_ISA_AVX
|
||||
#define TARGET_AVX2 TARGET_ISA_AVX2
|
||||
#define TARGET_AVX512F TARGET_ISA_AVX512F
|
||||
#define TARGET_AVX512PF TARGET_ISA_AVX512PF
|
||||
#define TARGET_AVX512ER TARGET_ISA_AVX512ER
|
||||
#define TARGET_AVX512CD TARGET_ISA_AVX512CD
|
||||
#define TARGET_FMA TARGET_ISA_FMA
|
||||
#define TARGET_SSE4A TARGET_ISA_SSE4A
|
||||
#define TARGET_FMA4 TARGET_ISA_FMA4
|
||||
@ -732,7 +736,8 @@ enum target_cpu_default
|
||||
Pentium+ prefers DFmode values to be aligned to 64 bit boundary
|
||||
and Pentium Pro XFmode values at 128 bit boundaries. */
|
||||
|
||||
#define BIGGEST_ALIGNMENT (TARGET_AVX ? 256 : 128)
|
||||
#define BIGGEST_ALIGNMENT \
|
||||
(TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : 128))
|
||||
|
||||
/* Maximum stack alignment. */
|
||||
#define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT
|
||||
@ -888,7 +893,7 @@ enum target_cpu_default
|
||||
eliminated during reloading in favor of either the stack or frame
|
||||
pointer. */
|
||||
|
||||
#define FIRST_PSEUDO_REGISTER 53
|
||||
#define FIRST_PSEUDO_REGISTER 69
|
||||
|
||||
/* Number of hardware registers that go into the DWARF-2 unwind info.
|
||||
If not defined, equals FIRST_PSEUDO_REGISTER. */
|
||||
@ -914,6 +919,10 @@ enum target_cpu_default
|
||||
/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
/*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
/*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 }
|
||||
|
||||
/* 1 for registers not available across function calls.
|
||||
@ -942,7 +951,11 @@ enum target_cpu_default
|
||||
/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
|
||||
1, 1, 1, 1, 2, 2, 2, 2, \
|
||||
/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
|
||||
6, 6, 6, 6, 6, 6, 6, 6 }
|
||||
6, 6, 6, 6, 6, 6, 6, 6, \
|
||||
/*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \
|
||||
6, 6, 6, 6, 6, 6, 6, 6, \
|
||||
/*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
|
||||
6, 6, 6, 6, 6, 6, 6, 6 }
|
||||
|
||||
/* Order in which to allocate registers. Each register must be
|
||||
listed once, even those in FIXED_REGISTERS. List frame pointer
|
||||
@ -957,7 +970,8 @@ enum target_cpu_default
|
||||
{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
|
||||
18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
|
||||
33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
|
||||
48, 49, 50, 51, 52 }
|
||||
48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \
|
||||
63, 64, 65, 66, 67, 68 }
|
||||
|
||||
/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
|
||||
to be rearranged based on a particular function. When using sse math,
|
||||
@ -1003,6 +1017,14 @@ enum target_cpu_default
|
||||
#define VALID_AVX256_REG_OR_OI_MODE(MODE) \
|
||||
(VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode)
|
||||
|
||||
#define VALID_AVX512F_SCALAR_MODE(MODE) \
|
||||
((MODE) == DImode || (MODE) == DFmode || (MODE) == SImode \
|
||||
|| (MODE) == SFmode)
|
||||
|
||||
#define VALID_AVX512F_REG_MODE(MODE) \
|
||||
((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \
|
||||
|| (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode)
|
||||
|
||||
#define VALID_SSE2_REG_MODE(MODE) \
|
||||
((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
|
||||
|| (MODE) == V2DImode || (MODE) == DFmode)
|
||||
@ -1042,7 +1064,9 @@ enum target_cpu_default
|
||||
|| (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \
|
||||
|| (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
|
||||
|| (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \
|
||||
|| (MODE) == V2TImode)
|
||||
|| (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \
|
||||
|| (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \
|
||||
|| (MODE) == V16SFmode)
|
||||
|
||||
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
|
||||
|
||||
@ -1105,15 +1129,18 @@ enum target_cpu_default
|
||||
#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
|
||||
#define LAST_SSE_REG (FIRST_SSE_REG + 7)
|
||||
|
||||
#define FIRST_MMX_REG (LAST_SSE_REG + 1)
|
||||
#define FIRST_MMX_REG (LAST_SSE_REG + 1) /*29*/
|
||||
#define LAST_MMX_REG (FIRST_MMX_REG + 7)
|
||||
|
||||
#define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
|
||||
#define FIRST_REX_INT_REG (LAST_MMX_REG + 1) /*37*/
|
||||
#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
|
||||
|
||||
#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
|
||||
#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) /*45*/
|
||||
#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
|
||||
|
||||
#define FIRST_EXT_REX_SSE_REG (LAST_REX_SSE_REG + 1) /*53*/
|
||||
#define LAST_EXT_REX_SSE_REG (FIRST_EXT_REX_SSE_REG + 15) /*68*/
|
||||
|
||||
/* Override this in other tm.h files to cope with various OS lossage
|
||||
requiring a frame pointer. */
|
||||
#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
|
||||
@ -1193,6 +1220,8 @@ enum reg_class
|
||||
FLOAT_REGS,
|
||||
SSE_FIRST_REG,
|
||||
SSE_REGS,
|
||||
EVEX_SSE_REGS,
|
||||
ALL_SSE_REGS,
|
||||
MMX_REGS,
|
||||
FP_TOP_SSE_REGS,
|
||||
FP_SECOND_SSE_REGS,
|
||||
@ -1210,7 +1239,7 @@ enum reg_class
|
||||
#define FLOAT_CLASS_P(CLASS) \
|
||||
reg_class_subset_p ((CLASS), FLOAT_REGS)
|
||||
#define SSE_CLASS_P(CLASS) \
|
||||
reg_class_subset_p ((CLASS), SSE_REGS)
|
||||
reg_class_subset_p ((CLASS), ALL_SSE_REGS)
|
||||
#define MMX_CLASS_P(CLASS) \
|
||||
((CLASS) == MMX_REGS)
|
||||
#define MAYBE_INTEGER_CLASS_P(CLASS) \
|
||||
@ -1218,7 +1247,7 @@ enum reg_class
|
||||
#define MAYBE_FLOAT_CLASS_P(CLASS) \
|
||||
reg_classes_intersect_p ((CLASS), FLOAT_REGS)
|
||||
#define MAYBE_SSE_CLASS_P(CLASS) \
|
||||
reg_classes_intersect_p ((CLASS), SSE_REGS)
|
||||
reg_classes_intersect_p ((CLASS), ALL_SSE_REGS)
|
||||
#define MAYBE_MMX_CLASS_P(CLASS) \
|
||||
reg_classes_intersect_p ((CLASS), MMX_REGS)
|
||||
|
||||
@ -1244,6 +1273,8 @@ enum reg_class
|
||||
"FLOAT_REGS", \
|
||||
"SSE_FIRST_REG", \
|
||||
"SSE_REGS", \
|
||||
"EVEX_SSE_REGS", \
|
||||
"ALL_SSE_REGS", \
|
||||
"MMX_REGS", \
|
||||
"FP_TOP_SSE_REGS", \
|
||||
"FP_SECOND_SSE_REGS", \
|
||||
@ -1259,30 +1290,36 @@ enum reg_class
|
||||
Note that CLOBBERED_REGS are calculated by
|
||||
TARGET_CONDITIONAL_REGISTER_USAGE. */
|
||||
|
||||
#define REG_CLASS_CONTENTS \
|
||||
{ { 0x00, 0x0 }, \
|
||||
{ 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
|
||||
{ 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
|
||||
{ 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
|
||||
{ 0x03, 0x0 }, /* AD_REGS */ \
|
||||
{ 0x0f, 0x0 }, /* Q_REGS */ \
|
||||
{ 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
|
||||
{ 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
|
||||
{ 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
|
||||
{ 0x00, 0x0 }, /* CLOBBERED_REGS */ \
|
||||
{ 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
|
||||
{ 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
|
||||
{ 0xff00, 0x0 }, /* FLOAT_REGS */ \
|
||||
{ 0x200000, 0x0 }, /* SSE_FIRST_REG */ \
|
||||
{ 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
|
||||
{ 0xe0000000, 0x1f }, /* MMX_REGS */ \
|
||||
{ 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
|
||||
{ 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
|
||||
{ 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
|
||||
{ 0x11ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
|
||||
{ 0x1ff100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
|
||||
{ 0x1ff1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
|
||||
{ 0xffffffff,0x1fffff } \
|
||||
#define REG_CLASS_CONTENTS \
|
||||
{ { 0x00, 0x0, 0x0 }, \
|
||||
{ 0x01, 0x0, 0x0 }, /* AREG */ \
|
||||
{ 0x02, 0x0, 0x0 }, /* DREG */ \
|
||||
{ 0x04, 0x0, 0x0 }, /* CREG */ \
|
||||
{ 0x08, 0x0, 0x0 }, /* BREG */ \
|
||||
{ 0x10, 0x0, 0x0 }, /* SIREG */ \
|
||||
{ 0x20, 0x0, 0x0 }, /* DIREG */ \
|
||||
{ 0x03, 0x0, 0x0 }, /* AD_REGS */ \
|
||||
{ 0x0f, 0x0, 0x0 }, /* Q_REGS */ \
|
||||
{ 0x1100f0, 0x1fe0, 0x0 }, /* NON_Q_REGS */ \
|
||||
{ 0x7f, 0x1fe0, 0x0 }, /* INDEX_REGS */ \
|
||||
{ 0x1100ff, 0x0, 0x0 }, /* LEGACY_REGS */ \
|
||||
{ 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \
|
||||
{ 0x1100ff, 0x1fe0, 0x0 }, /* GENERAL_REGS */ \
|
||||
{ 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \
|
||||
{ 0x0200, 0x0, 0x0 }, /* FP_SECOND_REG */ \
|
||||
{ 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \
|
||||
{ 0x200000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \
|
||||
{ 0x1fe00000, 0x1fe000, 0x0 }, /* SSE_REGS */ \
|
||||
{ 0x0,0xffe00000, 0x1f }, /* EVEX_SSE_REGS */ \
|
||||
{ 0x1fe00000,0xffffe000, 0x1f }, /* ALL_SSE_REGS */ \
|
||||
{ 0xe0000000, 0x1f, 0x0 }, /* MMX_REGS */ \
|
||||
{ 0x1fe00100,0xffffe000, 0x1f }, /* FP_TOP_SSE_REG */ \
|
||||
{ 0x1fe00200,0xffffe000, 0x1f }, /* FP_SECOND_SSE_REG */ \
|
||||
{ 0x1fe0ff00,0xffffe000, 0x1f }, /* FLOAT_SSE_REGS */ \
|
||||
{ 0x11ffff, 0x1fe0, 0x0 }, /* FLOAT_INT_REGS */ \
|
||||
{ 0x1ff100ff,0xffffffe0, 0x1f }, /* INT_SSE_REGS */ \
|
||||
{ 0x1ff1ffff,0xffffffe0, 0x1f }, /* FLOAT_INT_SSE_REGS */ \
|
||||
{ 0xffffffff,0xffffffff, 0x1f } \
|
||||
}
|
||||
|
||||
/* The same information, inverted:
|
||||
@ -1326,13 +1363,20 @@ enum reg_class
|
||||
#define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X)))
|
||||
#define SSE_REGNO_P(N) \
|
||||
(IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
|
||||
|| REX_SSE_REGNO_P (N))
|
||||
|| REX_SSE_REGNO_P (N) \
|
||||
|| EXT_REX_SSE_REGNO_P (N))
|
||||
|
||||
#define REX_SSE_REGNO_P(N) \
|
||||
IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
|
||||
|
||||
#define EXT_REX_SSE_REGNO_P(N) \
|
||||
IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG)
|
||||
|
||||
#define SSE_REGNO(N) \
|
||||
((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
|
||||
((N) < 8 ? FIRST_SSE_REG + (N) \
|
||||
: (N) <= LAST_REX_SSE_REG ? (FIRST_REX_SSE_REG + (N) - 8) \
|
||||
: (FIRST_EXT_REX_SSE_REG + (N) - 16))
|
||||
|
||||
|
||||
#define SSE_FLOAT_MODE_P(MODE) \
|
||||
((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
|
||||
@ -1885,7 +1929,11 @@ do { \
|
||||
"xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
|
||||
"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
|
||||
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
|
||||
"xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
|
||||
"xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \
|
||||
"xmm16", "xmm17", "xmm18", "xmm19", \
|
||||
"xmm20", "xmm21", "xmm22", "xmm23", \
|
||||
"xmm24", "xmm25", "xmm26", "xmm27", \
|
||||
"xmm28", "xmm29", "xmm30", "xmm31" }
|
||||
|
||||
#define REGISTER_NAMES HI_REGISTER_NAMES
|
||||
|
||||
@ -2206,9 +2254,13 @@ enum avx_u128_state
|
||||
scheduling just increases amount of live registers at time and in
|
||||
the turn amount of fxch instructions needed.
|
||||
|
||||
??? Maybe Pentium chips benefits from renaming, someone can try.... */
|
||||
??? Maybe Pentium chips benefits from renaming, someone can try....
|
||||
|
||||
#define HARD_REGNO_RENAME_OK(SRC, TARGET) !STACK_REGNO_P (SRC)
|
||||
Don't rename evex to non-evex sse registers. */
|
||||
|
||||
#define HARD_REGNO_RENAME_OK(SRC, TARGET) (!STACK_REGNO_P (SRC) && \
|
||||
(EXT_REX_SSE_REGNO_P (SRC) == \
|
||||
EXT_REX_SSE_REGNO_P (TARGET)))
|
||||
|
||||
|
||||
#define FASTCALL_PREFIX '@'
|
||||
|
||||
@ -312,6 +312,22 @@
|
||||
(XMM13_REG 50)
|
||||
(XMM14_REG 51)
|
||||
(XMM15_REG 52)
|
||||
(XMM16_REG 53)
|
||||
(XMM17_REG 54)
|
||||
(XMM18_REG 55)
|
||||
(XMM19_REG 56)
|
||||
(XMM20_REG 57)
|
||||
(XMM21_REG 58)
|
||||
(XMM22_REG 59)
|
||||
(XMM23_REG 60)
|
||||
(XMM24_REG 61)
|
||||
(XMM25_REG 62)
|
||||
(XMM26_REG 63)
|
||||
(XMM27_REG 64)
|
||||
(XMM28_REG 65)
|
||||
(XMM29_REG 66)
|
||||
(XMM30_REG 67)
|
||||
(XMM31_REG 68)
|
||||
])
|
||||
|
||||
;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
|
||||
@ -350,7 +366,8 @@
|
||||
|
||||
;; Main data type used by the insn
|
||||
(define_attr "mode"
|
||||
"unknown,none,QI,HI,SI,DI,TI,OI,SF,DF,XF,TF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF"
|
||||
"unknown,none,QI,HI,SI,DI,TI,OI,XI,SF,DF,XF,TF,V16SF,V8SF,V4DF,V4SF,
|
||||
V2DF,V2SF,V1DF,V8DF"
|
||||
(const_string "unknown"))
|
||||
|
||||
;; The CPU unit operations uses.
|
||||
@ -471,10 +488,13 @@
|
||||
(const_int 0)))
|
||||
|
||||
;; Prefix used: original, VEX or maybe VEX.
|
||||
(define_attr "prefix" "orig,vex,maybe_vex"
|
||||
(if_then_else (eq_attr "mode" "OI,V8SF,V4DF")
|
||||
(const_string "vex")
|
||||
(const_string "orig")))
|
||||
(define_attr "prefix" "orig,vex,maybe_vex,evex,maybe_evex"
|
||||
(cond [(eq_attr "mode" "OI,V8SF,V4DF")
|
||||
(const_string "vex")
|
||||
(eq_attr "mode" "XI,V16SF,V8DF")
|
||||
(const_string "evex")
|
||||
]
|
||||
(const_string "orig")))
|
||||
|
||||
;; VEX W bit is used.
|
||||
(define_attr "prefix_vex_w" "" (const_int 0))
|
||||
@ -493,6 +513,9 @@
|
||||
(symbol_ref "ix86_attr_length_vex_default (insn, false, true)")
|
||||
(symbol_ref "ix86_attr_length_vex_default (insn, false, false)"))))
|
||||
|
||||
;; 4-bytes evex prefix and 1 byte opcode.
|
||||
(define_attr "length_evex" "" (const_int 5))
|
||||
|
||||
;; Set when modrm byte is used.
|
||||
(define_attr "modrm" ""
|
||||
(cond [(eq_attr "type" "str,leave")
|
||||
@ -544,8 +567,17 @@
|
||||
(plus (const_int 2)
|
||||
(plus (attr "prefix_data16")
|
||||
(attr "length_address")))
|
||||
(ior (eq_attr "prefix" "evex")
|
||||
(and (ior (eq_attr "prefix" "maybe_evex")
|
||||
(eq_attr "prefix" "maybe_vex"))
|
||||
(match_test "TARGET_AVX512F")))
|
||||
(plus (attr "length_evex")
|
||||
(plus (attr "length_immediate")
|
||||
(plus (attr "modrm")
|
||||
(attr "length_address"))))
|
||||
(ior (eq_attr "prefix" "vex")
|
||||
(and (eq_attr "prefix" "maybe_vex")
|
||||
(and (ior (eq_attr "prefix" "maybe_vex")
|
||||
(eq_attr "prefix" "maybe_evex"))
|
||||
(match_test "TARGET_AVX")))
|
||||
(plus (attr "length_vex")
|
||||
(plus (attr "length_immediate")
|
||||
@ -663,7 +695,7 @@
|
||||
;; Used to control the "enabled" attribute on a per-instruction basis.
|
||||
(define_attr "isa" "base,x64,x64_sse4,x64_sse4_noavx,x64_avx,nox64,
|
||||
sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx,
|
||||
avx2,noavx2,bmi2,fma4,fma"
|
||||
avx2,noavx2,bmi2,fma4,fma,avx512f,noavx512f,fma_avx512f"
|
||||
(const_string "base"))
|
||||
|
||||
(define_attr "enabled" ""
|
||||
@ -689,6 +721,10 @@
|
||||
(eq_attr "isa" "bmi2") (symbol_ref "TARGET_BMI2")
|
||||
(eq_attr "isa" "fma4") (symbol_ref "TARGET_FMA4")
|
||||
(eq_attr "isa" "fma") (symbol_ref "TARGET_FMA")
|
||||
(eq_attr "isa" "avx512f") (symbol_ref "TARGET_AVX512F")
|
||||
(eq_attr "isa" "noavx512f") (symbol_ref "!TARGET_AVX512F")
|
||||
(eq_attr "isa" "fma_avx512f")
|
||||
(symbol_ref "TARGET_FMA || TARGET_AVX512F")
|
||||
]
|
||||
(const_int 1)))
|
||||
|
||||
@ -924,10 +960,12 @@
|
||||
;; SSE instruction suffix for various modes
|
||||
(define_mode_attr ssemodesuffix
|
||||
[(SF "ss") (DF "sd")
|
||||
(V16SF "ps") (V8DF "pd")
|
||||
(V8SF "ps") (V4DF "pd")
|
||||
(V4SF "ps") (V2DF "pd")
|
||||
(V16QI "b") (V8HI "w") (V4SI "d") (V2DI "q")
|
||||
(V32QI "b") (V16HI "w") (V8SI "d") (V4DI "q")])
|
||||
(V32QI "b") (V16HI "w") (V8SI "d") (V4DI "q")
|
||||
(V64QI "b") (V16SI "d") (V8DI "q")])
|
||||
|
||||
;; SSE vector suffix for floating point modes
|
||||
(define_mode_attr ssevecmodesuffix [(SF "ps") (DF "pd")])
|
||||
@ -1649,6 +1687,12 @@
|
||||
|
||||
;; Move instructions.
|
||||
|
||||
(define_expand "movxi"
|
||||
[(set (match_operand:XI 0 "nonimmediate_operand")
|
||||
(match_operand:XI 1 "general_operand"))]
|
||||
"TARGET_AVX512F"
|
||||
"ix86_expand_move (XImode, operands); DONE;")
|
||||
|
||||
;; Reload patterns to support multi-word load/store
|
||||
;; with non-offsetable address.
|
||||
(define_expand "reload_noff_store"
|
||||
@ -1746,6 +1790,30 @@
|
||||
(set_attr "mode" "<MODE>")
|
||||
(set_attr "length_immediate" "1")])
|
||||
|
||||
(define_insn "*movxi_internal_avx512f"
|
||||
[(set (match_operand:XI 0 "nonimmediate_operand" "=x,x ,m")
|
||||
(match_operand:XI 1 "vector_move_operand" "C ,xm,x"))]
|
||||
"TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
|
||||
{
|
||||
switch (which_alternative)
|
||||
{
|
||||
case 0:
|
||||
return standard_sse_constant_opcode (insn, operands[1]);
|
||||
case 1:
|
||||
case 2:
|
||||
if (misaligned_operand (operands[0], XImode)
|
||||
|| misaligned_operand (operands[1], XImode))
|
||||
return "vmovdqu32\t{%1, %0|%0, %1}";
|
||||
else
|
||||
return "vmovdqa32\t{%1, %0|%0, %1}";
|
||||
default:
|
||||
gcc_unreachable ();
|
||||
}
|
||||
}
|
||||
[(set_attr "type" "sselog1,ssemov,ssemov")
|
||||
(set_attr "prefix" "evex")
|
||||
(set_attr "mode" "XI")])
|
||||
|
||||
(define_insn "*movoi_internal_avx"
|
||||
[(set (match_operand:OI 0 "nonimmediate_operand" "=x,x ,m")
|
||||
(match_operand:OI 1 "vector_move_operand" "C ,xm,x"))]
|
||||
@ -1857,9 +1925,9 @@
|
||||
|
||||
(define_insn "*movdi_internal"
|
||||
[(set (match_operand:DI 0 "nonimmediate_operand"
|
||||
"=r ,o ,r,r ,r,m ,*y,*y,?*y,?m,?r ,?*Ym,*x,*x,*x,m ,?r ,?r,?*Yi,?*Ym,?*Yi")
|
||||
"=r ,o ,r,r ,r,m ,*y,*y,?*y,?m,?r ,?*Ym,*v,*v,*v,m ,?r ,?r,?*Yi,?*Ym,?*Yi")
|
||||
(match_operand:DI 1 "general_operand"
|
||||
"riFo,riF,Z,rem,i,re,C ,*y,m ,*y,*Yn,r ,C ,*x,m ,*x,*Yj,*x,r ,*Yj ,*Yn"))]
|
||||
"riFo,riF,Z,rem,i,re,C ,*y,m ,*y,*Yn,r ,C ,*v,m ,*v,*Yj,*v,r ,*Yj ,*Yn"))]
|
||||
"!(MEM_P (operands[0]) && MEM_P (operands[1]))"
|
||||
{
|
||||
switch (get_attr_type (insn))
|
||||
@ -1896,6 +1964,8 @@
|
||||
return "%vmovq\t{%1, %0|%0, %1}";
|
||||
case MODE_TI:
|
||||
return "%vmovdqa\t{%1, %0|%0, %1}";
|
||||
case MODE_XI:
|
||||
return "vmovdqa64\t{%g1, %g0|%g0, %g1}";
|
||||
|
||||
case MODE_V2SF:
|
||||
gcc_assert (!TARGET_AVX);
|
||||
@ -1989,7 +2059,11 @@
|
||||
(cond [(eq_attr "alternative" "2")
|
||||
(const_string "SI")
|
||||
(eq_attr "alternative" "12,13")
|
||||
(cond [(ior (not (match_test "TARGET_SSE2"))
|
||||
(cond [(ior (match_test "EXT_REX_SSE_REGNO_P (REGNO (operands[0]))")
|
||||
(and (match_test "REG_P (operands[1])")
|
||||
(match_test "EXT_REX_SSE_REGNO_P (REGNO (operands[1]))")))
|
||||
(const_string "XI")
|
||||
(ior (not (match_test "TARGET_SSE2"))
|
||||
(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL"))
|
||||
(const_string "V4SF")
|
||||
(match_test "TARGET_AVX")
|
||||
@ -2018,9 +2092,9 @@
|
||||
|
||||
(define_insn "*movsi_internal"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand"
|
||||
"=r,m ,*y,*y,?rm,?*y,*x,*x,*x,m ,?r ,?r,?*Yi")
|
||||
"=r,m ,*y,*y,?rm,?*y,*v,*v,*v,m ,?r ,?r,?*Yi")
|
||||
(match_operand:SI 1 "general_operand"
|
||||
"g ,re,C ,*y,*y ,rm ,C ,*x,m ,*x,*Yj,*x,r"))]
|
||||
"g ,re,C ,*y,*y ,rm ,C ,*v,m ,*v,*Yj,*v,r"))]
|
||||
"!(MEM_P (operands[0]) && MEM_P (operands[1]))"
|
||||
{
|
||||
switch (get_attr_type (insn))
|
||||
@ -2038,6 +2112,8 @@
|
||||
return "%vmovd\t{%1, %0|%0, %1}";
|
||||
case MODE_TI:
|
||||
return "%vmovdqa\t{%1, %0|%0, %1}";
|
||||
case MODE_XI:
|
||||
return "vmovdqa32\t{%g1, %g0|%g0, %g1}";
|
||||
|
||||
case MODE_V4SF:
|
||||
return "%vmovaps\t{%1, %0|%0, %1}";
|
||||
@ -2116,7 +2192,11 @@
|
||||
(cond [(eq_attr "alternative" "2,3")
|
||||
(const_string "DI")
|
||||
(eq_attr "alternative" "6,7")
|
||||
(cond [(ior (not (match_test "TARGET_SSE2"))
|
||||
(cond [(ior (match_test "EXT_REX_SSE_REGNO_P (REGNO (operands[0]))")
|
||||
(and (match_test "REG_P (operands[1])")
|
||||
(match_test "EXT_REX_SSE_REGNO_P (REGNO (operands[1]))")))
|
||||
(const_string "XI")
|
||||
(ior (not (match_test "TARGET_SSE2"))
|
||||
(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL"))
|
||||
(const_string "V4SF")
|
||||
(match_test "TARGET_AVX")
|
||||
@ -2703,9 +2783,9 @@
|
||||
;; Possible store forwarding (partial memory) stall in alternative 4.
|
||||
(define_insn "*movdf_internal"
|
||||
[(set (match_operand:DF 0 "nonimmediate_operand"
|
||||
"=Yf*f,m ,Yf*f,?Yd*r ,!o ,?r,?m,?r,?r,x,x,x,m,*x,*x,*x,m ,r ,Yi")
|
||||
"=Yf*f,m ,Yf*f,?Yd*r ,!o ,?r,?m,?r,?r,v,v,v,m,*x,*x,*x,m ,r ,Yi")
|
||||
(match_operand:DF 1 "general_operand"
|
||||
"Yf*fm,Yf*f,G ,Yd*roF,Yd*rF,rm,rC,C ,F ,C,x,m,x,C ,*x,m ,*x,Yj,r"))]
|
||||
"Yf*fm,Yf*f,G ,Yd*roF,Yd*rF,rm,rC,C ,F ,C,v,m,v,C ,*x,m ,*x,Yj,r"))]
|
||||
"!(MEM_P (operands[0]) && MEM_P (operands[1]))
|
||||
&& (!can_create_pseudo_p ()
|
||||
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
|
||||
@ -2750,6 +2830,8 @@
|
||||
|
||||
case MODE_V4SF:
|
||||
return "%vmovaps\t{%1, %0|%0, %1}";
|
||||
case MODE_V8DF:
|
||||
return "vmovapd\t{%g1, %g0|%g0, %g1}";
|
||||
case MODE_V2DF:
|
||||
return "%vmovapd\t{%1, %0|%0, %1}";
|
||||
|
||||
@ -2824,6 +2906,8 @@
|
||||
(eq_attr "alternative" "9,13")
|
||||
(cond [(not (match_test "TARGET_SSE2"))
|
||||
(const_string "V4SF")
|
||||
(match_test "TARGET_AVX512F")
|
||||
(const_string "XI")
|
||||
(match_test "TARGET_AVX")
|
||||
(const_string "V2DF")
|
||||
(match_test "optimize_function_for_size_p (cfun)")
|
||||
@ -2839,7 +2923,11 @@
|
||||
|
||||
/* movaps is one byte shorter for non-AVX targets. */
|
||||
(eq_attr "alternative" "10,14")
|
||||
(cond [(ior (not (match_test "TARGET_SSE2"))
|
||||
(cond [(ior (match_test "EXT_REX_SSE_REGNO_P (REGNO (operands[0]))")
|
||||
(and (match_test "REG_P (operands[1])")
|
||||
(match_test "EXT_REX_SSE_REGNO_P (REGNO (operands[1]))")))
|
||||
(const_string "V8DF")
|
||||
(ior (not (match_test "TARGET_SSE2"))
|
||||
(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL"))
|
||||
(const_string "V4SF")
|
||||
(match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
|
||||
@ -2872,9 +2960,9 @@
|
||||
|
||||
(define_insn "*movsf_internal"
|
||||
[(set (match_operand:SF 0 "nonimmediate_operand"
|
||||
"=Yf*f,m ,Yf*f,?r ,?m,x,x,x,m,?r,?Yi,!*y,!*y,!m,!r ,!*Ym")
|
||||
"=Yf*f,m ,Yf*f,?r ,?m,v,v,v,m,?r,?Yi,!*y,!*y,!m,!r ,!*Ym")
|
||||
(match_operand:SF 1 "general_operand"
|
||||
"Yf*fm,Yf*f,G ,rmF,rF,C,x,m,x,Yj,r ,*y ,m ,*y,*Yn,r"))]
|
||||
"Yf*fm,Yf*f,G ,rmF,rF,C,v,m,v,Yj,r ,*y ,m ,*y,*Yn,r"))]
|
||||
"!(MEM_P (operands[0]) && MEM_P (operands[1]))
|
||||
&& (!can_create_pseudo_p ()
|
||||
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
|
||||
@ -2907,6 +2995,8 @@
|
||||
return "vmovss\t{%1, %0, %0|%0, %0, %1}";
|
||||
return "%vmovss\t{%1, %0|%0, %1}";
|
||||
|
||||
case MODE_V16SF:
|
||||
return "vmovaps\t{%g1, %g0|%g0, %g1}";
|
||||
case MODE_V4SF:
|
||||
return "%vmovaps\t{%1, %0|%0, %1}";
|
||||
|
||||
@ -2960,6 +3050,8 @@
|
||||
(eq_attr "alternative" "5")
|
||||
(cond [(not (match_test "TARGET_SSE2"))
|
||||
(const_string "V4SF")
|
||||
(match_test "TARGET_AVX512F")
|
||||
(const_string "V16SF")
|
||||
(match_test "TARGET_AVX")
|
||||
(const_string "V4SF")
|
||||
(match_test "optimize_function_for_size_p (cfun)")
|
||||
@ -2979,10 +3071,16 @@
|
||||
of instructions to load just part of the register. It is
|
||||
better to maintain the whole registers in single format
|
||||
to avoid problems on using packed logical operations. */
|
||||
(and (eq_attr "alternative" "6")
|
||||
(ior (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
|
||||
(match_test "TARGET_SSE_SPLIT_REGS")))
|
||||
(const_string "V4SF")
|
||||
(eq_attr "alternative" "6")
|
||||
(cond [(ior (match_test "EXT_REX_SSE_REGNO_P (REGNO (operands[0]))")
|
||||
(and (match_test "REG_P (operands[1])")
|
||||
(match_test "EXT_REX_SSE_REGNO_P (REGNO (operands[1]))")))
|
||||
(const_string "V16SF")
|
||||
(ior (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
|
||||
(match_test "TARGET_SSE_SPLIT_REGS"))
|
||||
(const_string "V4SF")
|
||||
]
|
||||
(const_string "SF"))
|
||||
]
|
||||
(const_string "SF")))])
|
||||
|
||||
@ -12654,10 +12752,10 @@
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*fop_<mode>_comm_sse"
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x,v")
|
||||
(match_operator:MODEF 3 "binary_fp_operator"
|
||||
[(match_operand:MODEF 1 "nonimmediate_operand" "%0,x")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "xm,xm")]))]
|
||||
[(match_operand:MODEF 1 "nonimmediate_operand" "%0,v")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "xm,vm")]))]
|
||||
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
|
||||
&& COMMUTATIVE_ARITH_P (operands[3])
|
||||
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
@ -16002,10 +16100,10 @@
|
||||
;; are undefined in this condition, we're certain this is correct.
|
||||
|
||||
(define_insn "<code><mode>3"
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x,v")
|
||||
(smaxmin:MODEF
|
||||
(match_operand:MODEF 1 "nonimmediate_operand" "%0,x")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "xm,xm")))]
|
||||
(match_operand:MODEF 1 "nonimmediate_operand" "%0,v")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "xm,vm")))]
|
||||
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
|
||||
"@
|
||||
<maxmin_float><ssemodesuffix>\t{%2, %0|%0, %2}
|
||||
|
||||
@ -517,6 +517,22 @@ mavx2
|
||||
Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save
|
||||
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation
|
||||
|
||||
mavx512f
|
||||
Target Report Mask(ISA_AVX512F) Var(ix86_isa_flags) Save
|
||||
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and code generation
|
||||
|
||||
mavx512pf
|
||||
Target Report Mask(ISA_AVX512PF) Var(ix86_isa_flags) Save
|
||||
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation
|
||||
|
||||
mavx512er
|
||||
Target Report Mask(ISA_AVX512ER) Var(ix86_isa_flags) Save
|
||||
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation
|
||||
|
||||
mavx512cd
|
||||
Target Report Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save
|
||||
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation
|
||||
|
||||
mfma
|
||||
Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save
|
||||
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation
|
||||
|
||||
@ -78,9 +78,9 @@
|
||||
|
||||
(define_insn "*mov<mode>_internal"
|
||||
[(set (match_operand:MMXMODE 0 "nonimmediate_operand"
|
||||
"=r ,o ,r,r ,m ,?!y,!y,?!y,m ,r ,?!Ym,x,x,x,m,*x,*x,*x,m ,r ,Yi,!Ym,*Yi")
|
||||
"=r ,o ,r,r ,m ,?!y,!y,?!y,m ,r ,?!Ym,v,v,v,m,*x,*x,*x,m ,r ,Yi,!Ym,*Yi")
|
||||
(match_operand:MMXMODE 1 "vector_move_operand"
|
||||
"rCo,rC,C,rm,rC,C ,!y,m ,?!y,?!Yn,r ,C,x,m,x,C ,*x,m ,*x,Yj,r ,*Yj,!Yn"))]
|
||||
"rCo,rC,C,rm,rC,C ,!y,m ,?!y,?!Yn,r ,C,v,m,v,C ,*x,m ,*x,Yj,r ,*Yj,!Yn"))]
|
||||
"TARGET_MMX
|
||||
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
|
||||
{
|
||||
@ -128,6 +128,9 @@
|
||||
case MODE_TI:
|
||||
return "%vmovdqa\t{%1, %0|%0, %1}";
|
||||
|
||||
case MODE_XI:
|
||||
return "vmovdqa64\t{%g1, %g0|%g0, %g1}";
|
||||
|
||||
case MODE_V2SF:
|
||||
if (TARGET_AVX && REG_P (operands[0]))
|
||||
return "vmovlps\t{%1, %0, %0|%0, %0, %1}";
|
||||
@ -182,7 +185,11 @@
|
||||
(cond [(eq_attr "alternative" "2")
|
||||
(const_string "SI")
|
||||
(eq_attr "alternative" "11,12,15,16")
|
||||
(cond [(match_test "<MODE>mode == V2SFmode")
|
||||
(cond [(ior (match_test "EXT_REX_SSE_REGNO_P (REGNO (operands[0]))")
|
||||
(and (match_test "REG_P (operands[1])")
|
||||
(match_test "EXT_REX_SSE_REGNO_P (REGNO (operands[1]))")))
|
||||
(const_string "XI")
|
||||
(match_test "<MODE>mode == V2SFmode")
|
||||
(const_string "V4SF")
|
||||
(ior (not (match_test "TARGET_SSE2"))
|
||||
(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL"))
|
||||
|
||||
@ -244,6 +244,13 @@
|
||||
(V4SI "vec") (V8SI "avx2")
|
||||
(V2DI "vec") (V4DI "avx2")])
|
||||
|
||||
(define_mode_attr shuffletype
|
||||
[(V16SF "f") (V16SI "i") (V8DF "f") (V8DI "i")
|
||||
(V8SF "f") (V8SI "i") (V4DF "f") (V4DI "i")
|
||||
(V4SF "f") (V4SI "i") (V2DF "f") (V2DI "i")
|
||||
(V32QI "i") (V16HI "u") (V16QI "i") (V8HI "i")
|
||||
(V64QI "i") (V1TI "i") (V2TI "i")])
|
||||
|
||||
(define_mode_attr ssedoublemode
|
||||
[(V16HI "V16SI") (V8HI "V8SI") (V4HI "V4SI")
|
||||
(V32QI "V32HI") (V16QI "V16HI")])
|
||||
@ -301,8 +308,10 @@
|
||||
|
||||
;; SSE instruction mode
|
||||
(define_mode_attr sseinsnmode
|
||||
[(V32QI "OI") (V16HI "OI") (V8SI "OI") (V4DI "OI") (V2TI "OI")
|
||||
[(V64QI "XI") (V32HI "XI") (V16SI "XI") (V8DI "XI")
|
||||
(V32QI "OI") (V16HI "OI") (V8SI "OI") (V4DI "OI") (V2TI "OI")
|
||||
(V16QI "TI") (V8HI "TI") (V4SI "TI") (V2DI "TI") (V1TI "TI")
|
||||
(V16SF "V16SF") (V8DF "V8DF")
|
||||
(V8SF "V8SF") (V4DF "V4DF")
|
||||
(V4SF "V4SF") (V2DF "V2DF")
|
||||
(TI "TI")])
|
||||
@ -444,20 +453,64 @@
|
||||
})
|
||||
|
||||
(define_insn "*mov<mode>_internal"
|
||||
[(set (match_operand:VMOVE 0 "nonimmediate_operand" "=x,x ,m")
|
||||
(match_operand:VMOVE 1 "nonimmediate_or_sse_const_operand" "C ,xm,x"))]
|
||||
[(set (match_operand:VMOVE 0 "nonimmediate_operand" "=v,v ,m")
|
||||
(match_operand:VMOVE 1 "nonimmediate_or_sse_const_operand" "C ,vm,v"))]
|
||||
"TARGET_SSE
|
||||
&& (register_operand (operands[0], <MODE>mode)
|
||||
|| register_operand (operands[1], <MODE>mode))"
|
||||
{
|
||||
int mode = get_attr_mode (insn);
|
||||
switch (which_alternative)
|
||||
{
|
||||
case 0:
|
||||
return standard_sse_constant_opcode (insn, operands[1]);
|
||||
case 1:
|
||||
case 2:
|
||||
switch (get_attr_mode (insn))
|
||||
/* There is no evex-encoded vmov* for sizes smaller than 64-bytes
|
||||
in avx512f, so we need to use workarounds, to access sse registers
|
||||
16-31, which are evex-only. */
|
||||
if (TARGET_AVX512F && GET_MODE_SIZE (<MODE>mode) < 64
|
||||
&& (EXT_REX_SSE_REGNO_P (REGNO (operands[0]))
|
||||
|| EXT_REX_SSE_REGNO_P (REGNO (operands[1]))))
|
||||
{
|
||||
if (memory_operand (operands[0], <MODE>mode))
|
||||
{
|
||||
if (GET_MODE_SIZE (<MODE>mode) == 32)
|
||||
return "vextract<shuffletype>64x4\t{$0x0, %g1, %0|%0, %g1, 0x0}";
|
||||
else if (GET_MODE_SIZE (<MODE>mode) == 16)
|
||||
return "vextract<shuffletype>32x4\t{$0x0, %g1, %0|%0, %g1, 0x0}";
|
||||
else
|
||||
gcc_unreachable ();
|
||||
}
|
||||
else if (memory_operand (operands[1], <MODE>mode))
|
||||
{
|
||||
if (GET_MODE_SIZE (<MODE>mode) == 32)
|
||||
return "vbroadcast<shuffletype>64x4\t{%1, %g0|%g0, %1}";
|
||||
else if (GET_MODE_SIZE (<MODE>mode) == 16)
|
||||
return "vbroadcast<shuffletype>32x4\t{%1, %g0|%g0, %1}";
|
||||
else
|
||||
gcc_unreachable ();
|
||||
}
|
||||
else
|
||||
/* Reg -> reg move is always aligned. Just use wider move. */
|
||||
switch (mode)
|
||||
{
|
||||
case MODE_V8SF:
|
||||
case MODE_V4SF:
|
||||
return "vmovaps\t{%g1, %g0|%g0, %g1}";
|
||||
case MODE_V4DF:
|
||||
case MODE_V2DF:
|
||||
return "vmovapd\t{%g1, %g0|%g0, %g1}";
|
||||
case MODE_OI:
|
||||
case MODE_TI:
|
||||
return "vmovdqa64\t{%g1, %g0|%g0, %g1}";
|
||||
default:
|
||||
gcc_unreachable ();
|
||||
}
|
||||
}
|
||||
switch (mode)
|
||||
{
|
||||
case MODE_V16SF:
|
||||
case MODE_V8SF:
|
||||
case MODE_V4SF:
|
||||
if (TARGET_AVX
|
||||
@ -467,6 +520,7 @@
|
||||
else
|
||||
return "%vmovaps\t{%1, %0|%0, %1}";
|
||||
|
||||
case MODE_V8DF:
|
||||
case MODE_V4DF:
|
||||
case MODE_V2DF:
|
||||
if (TARGET_AVX
|
||||
@ -484,6 +538,12 @@
|
||||
return "vmovdqu\t{%1, %0|%0, %1}";
|
||||
else
|
||||
return "%vmovdqa\t{%1, %0|%0, %1}";
|
||||
case MODE_XI:
|
||||
if (misaligned_operand (operands[0], <MODE>mode)
|
||||
|| misaligned_operand (operands[1], <MODE>mode))
|
||||
return "vmovdqu64\t{%1, %0|%0, %1}";
|
||||
else
|
||||
return "vmovdqa64\t{%1, %0|%0, %1}";
|
||||
|
||||
default:
|
||||
gcc_unreachable ();
|
||||
@ -603,7 +663,7 @@
|
||||
})
|
||||
|
||||
(define_insn "<sse>_loadu<ssemodesuffix><avxsizesuffix>"
|
||||
[(set (match_operand:VF 0 "register_operand" "=x")
|
||||
[(set (match_operand:VF 0 "register_operand" "=v")
|
||||
(unspec:VF
|
||||
[(match_operand:VF 1 "memory_operand" "m")]
|
||||
UNSPEC_LOADU))]
|
||||
@ -662,7 +722,7 @@
|
||||
(const_string "<MODE>")))])
|
||||
|
||||
(define_insn "<sse2>_loaddqu<avxsizesuffix>"
|
||||
[(set (match_operand:VI1 0 "register_operand" "=x")
|
||||
[(set (match_operand:VI1 0 "register_operand" "=v")
|
||||
(unspec:VI1 [(match_operand:VI1 1 "memory_operand" "m")]
|
||||
UNSPEC_LOADU))]
|
||||
"TARGET_SSE2"
|
||||
@ -696,7 +756,7 @@
|
||||
|
||||
(define_insn "<sse2>_storedqu<avxsizesuffix>"
|
||||
[(set (match_operand:VI1 0 "memory_operand" "=m")
|
||||
(unspec:VI1 [(match_operand:VI1 1 "register_operand" "x")]
|
||||
(unspec:VI1 [(match_operand:VI1 1 "register_operand" "v")]
|
||||
UNSPEC_STOREU))]
|
||||
"TARGET_SSE2"
|
||||
{
|
||||
@ -863,10 +923,10 @@
|
||||
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
|
||||
|
||||
(define_insn "*<plusminus_insn><mode>3"
|
||||
[(set (match_operand:VF 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:VF 0 "register_operand" "=x,v")
|
||||
(plusminus:VF
|
||||
(match_operand:VF 1 "nonimmediate_operand" "<comm>0,x")
|
||||
(match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
|
||||
(match_operand:VF 1 "nonimmediate_operand" "<comm>0,v")
|
||||
(match_operand:VF 2 "nonimmediate_operand" "xm,vm")))]
|
||||
"TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
|
||||
"@
|
||||
<plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2}
|
||||
@ -877,11 +937,11 @@
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "<sse>_vm<plusminus_insn><mode>3"
|
||||
[(set (match_operand:VF_128 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:VF_128 0 "register_operand" "=x,v")
|
||||
(vec_merge:VF_128
|
||||
(plusminus:VF_128
|
||||
(match_operand:VF_128 1 "register_operand" "0,x")
|
||||
(match_operand:VF_128 2 "nonimmediate_operand" "xm,xm"))
|
||||
(match_operand:VF_128 1 "register_operand" "0,v")
|
||||
(match_operand:VF_128 2 "nonimmediate_operand" "xm,vm"))
|
||||
(match_dup 1)
|
||||
(const_int 1)))]
|
||||
"TARGET_SSE"
|
||||
@ -917,11 +977,11 @@
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "<sse>_vmmul<mode>3"
|
||||
[(set (match_operand:VF_128 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:VF_128 0 "register_operand" "=x,v")
|
||||
(vec_merge:VF_128
|
||||
(mult:VF_128
|
||||
(match_operand:VF_128 1 "register_operand" "0,x")
|
||||
(match_operand:VF_128 2 "nonimmediate_operand" "xm,xm"))
|
||||
(match_operand:VF_128 1 "register_operand" "0,v")
|
||||
(match_operand:VF_128 2 "nonimmediate_operand" "xm,vm"))
|
||||
(match_dup 1)
|
||||
(const_int 1)))]
|
||||
"TARGET_SSE"
|
||||
@ -960,10 +1020,10 @@
|
||||
})
|
||||
|
||||
(define_insn "<sse>_div<mode>3"
|
||||
[(set (match_operand:VF 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:VF 0 "register_operand" "=x,v")
|
||||
(div:VF
|
||||
(match_operand:VF 1 "register_operand" "0,x")
|
||||
(match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
|
||||
(match_operand:VF 1 "register_operand" "0,v")
|
||||
(match_operand:VF 2 "nonimmediate_operand" "xm,vm")))]
|
||||
"TARGET_SSE"
|
||||
"@
|
||||
div<ssemodesuffix>\t{%2, %0|%0, %2}
|
||||
@ -974,11 +1034,11 @@
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "<sse>_vmdiv<mode>3"
|
||||
[(set (match_operand:VF_128 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:VF_128 0 "register_operand" "=x,v")
|
||||
(vec_merge:VF_128
|
||||
(div:VF_128
|
||||
(match_operand:VF_128 1 "register_operand" "0,x")
|
||||
(match_operand:VF_128 2 "nonimmediate_operand" "xm,xm"))
|
||||
(match_operand:VF_128 1 "register_operand" "0,v")
|
||||
(match_operand:VF_128 2 "nonimmediate_operand" "xm,vm"))
|
||||
(match_dup 1)
|
||||
(const_int 1)))]
|
||||
"TARGET_SSE"
|
||||
@ -1043,8 +1103,8 @@
|
||||
})
|
||||
|
||||
(define_insn "<sse>_sqrt<mode>2"
|
||||
[(set (match_operand:VF 0 "register_operand" "=x")
|
||||
(sqrt:VF (match_operand:VF 1 "nonimmediate_operand" "xm")))]
|
||||
[(set (match_operand:VF 0 "register_operand" "=v")
|
||||
(sqrt:VF (match_operand:VF 1 "nonimmediate_operand" "vm")))]
|
||||
"TARGET_SSE"
|
||||
"%vsqrt<ssemodesuffix>\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "sse")
|
||||
@ -1054,11 +1114,11 @@
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "<sse>_vmsqrt<mode>2"
|
||||
[(set (match_operand:VF_128 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:VF_128 0 "register_operand" "=x,v")
|
||||
(vec_merge:VF_128
|
||||
(sqrt:VF_128
|
||||
(match_operand:VF_128 1 "nonimmediate_operand" "xm,xm"))
|
||||
(match_operand:VF_128 2 "register_operand" "0,x")
|
||||
(match_operand:VF_128 1 "nonimmediate_operand" "xm,vm"))
|
||||
(match_operand:VF_128 2 "register_operand" "0,v")
|
||||
(const_int 1)))]
|
||||
"TARGET_SSE"
|
||||
"@
|
||||
@ -1124,10 +1184,10 @@
|
||||
})
|
||||
|
||||
(define_insn "*<code><mode>3_finite"
|
||||
[(set (match_operand:VF 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:VF 0 "register_operand" "=x,v")
|
||||
(smaxmin:VF
|
||||
(match_operand:VF 1 "nonimmediate_operand" "%0,x")
|
||||
(match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
|
||||
(match_operand:VF 1 "nonimmediate_operand" "%0,v")
|
||||
(match_operand:VF 2 "nonimmediate_operand" "xm,vm")))]
|
||||
"TARGET_SSE && flag_finite_math_only
|
||||
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
|
||||
"@
|
||||
@ -1140,10 +1200,10 @@
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*<code><mode>3"
|
||||
[(set (match_operand:VF 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:VF 0 "register_operand" "=x,v")
|
||||
(smaxmin:VF
|
||||
(match_operand:VF 1 "register_operand" "0,x")
|
||||
(match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
|
||||
(match_operand:VF 1 "register_operand" "0,v")
|
||||
(match_operand:VF 2 "nonimmediate_operand" "xm,vm")))]
|
||||
"TARGET_SSE && !flag_finite_math_only"
|
||||
"@
|
||||
<maxmin_float><ssemodesuffix>\t{%2, %0|%0, %2}
|
||||
@ -1155,11 +1215,11 @@
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "<sse>_vm<code><mode>3"
|
||||
[(set (match_operand:VF_128 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:VF_128 0 "register_operand" "=x,v")
|
||||
(vec_merge:VF_128
|
||||
(smaxmin:VF_128
|
||||
(match_operand:VF_128 1 "register_operand" "0,x")
|
||||
(match_operand:VF_128 2 "nonimmediate_operand" "xm,xm"))
|
||||
(match_operand:VF_128 1 "register_operand" "0,v")
|
||||
(match_operand:VF_128 2 "nonimmediate_operand" "xm,vm"))
|
||||
(match_dup 1)
|
||||
(const_int 1)))]
|
||||
"TARGET_SSE"
|
||||
@ -1790,10 +1850,10 @@
|
||||
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
|
||||
|
||||
(define_insn "*<code><mode>3"
|
||||
[(set (match_operand:VF 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:VF 0 "register_operand" "=x,v")
|
||||
(any_logic:VF
|
||||
(match_operand:VF 1 "nonimmediate_operand" "%0,x")
|
||||
(match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
|
||||
(match_operand:VF 1 "nonimmediate_operand" "%0,v")
|
||||
(match_operand:VF 2 "nonimmediate_operand" "xm,vm")))]
|
||||
"TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
|
||||
{
|
||||
static char buf[32];
|
||||
@ -2101,11 +2161,11 @@
|
||||
"TARGET_FMA || TARGET_FMA4")
|
||||
|
||||
(define_insn "*fma_fmadd_<mode>"
|
||||
[(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x,x,x")
|
||||
[(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x")
|
||||
(fma:FMAMODE
|
||||
(match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x, x,x")
|
||||
(match_operand:FMAMODE 2 "nonimmediate_operand" "xm, x,xm,x,m")
|
||||
(match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0,xm,x")))]
|
||||
(match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0, v, x,x")
|
||||
(match_operand:FMAMODE 2 "nonimmediate_operand" "vm, v,vm, x,m")
|
||||
(match_operand:FMAMODE 3 "nonimmediate_operand" " v,vm, 0,xm,x")))]
|
||||
"TARGET_FMA || TARGET_FMA4"
|
||||
"@
|
||||
vfmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
|
||||
@ -2113,17 +2173,17 @@
|
||||
vfmadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
|
||||
vfmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}
|
||||
vfmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
|
||||
[(set_attr "isa" "fma,fma,fma,fma4,fma4")
|
||||
[(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4")
|
||||
(set_attr "type" "ssemuladd")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*fma_fmsub_<mode>"
|
||||
[(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x,x,x")
|
||||
[(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x")
|
||||
(fma:FMAMODE
|
||||
(match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x, x,x")
|
||||
(match_operand:FMAMODE 2 "nonimmediate_operand" "xm, x,xm,x,m")
|
||||
(match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0, v, x,x")
|
||||
(match_operand:FMAMODE 2 "nonimmediate_operand" "vm, v,vm, x,m")
|
||||
(neg:FMAMODE
|
||||
(match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0,xm,x"))))]
|
||||
(match_operand:FMAMODE 3 "nonimmediate_operand" " v,vm, 0,xm,x"))))]
|
||||
"TARGET_FMA || TARGET_FMA4"
|
||||
"@
|
||||
vfmsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
|
||||
@ -2131,17 +2191,17 @@
|
||||
vfmsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
|
||||
vfmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}
|
||||
vfmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
|
||||
[(set_attr "isa" "fma,fma,fma,fma4,fma4")
|
||||
[(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4")
|
||||
(set_attr "type" "ssemuladd")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*fma_fnmadd_<mode>"
|
||||
[(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x,x,x")
|
||||
[(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x")
|
||||
(fma:FMAMODE
|
||||
(neg:FMAMODE
|
||||
(match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x, x,x"))
|
||||
(match_operand:FMAMODE 2 "nonimmediate_operand" "xm, x,xm,x,m")
|
||||
(match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0,xm,x")))]
|
||||
(match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0, v, x,x"))
|
||||
(match_operand:FMAMODE 2 "nonimmediate_operand" "vm, v,vm, x,m")
|
||||
(match_operand:FMAMODE 3 "nonimmediate_operand" " v,vm, 0,xm,x")))]
|
||||
"TARGET_FMA || TARGET_FMA4"
|
||||
"@
|
||||
vfnmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
|
||||
@ -2149,18 +2209,18 @@
|
||||
vfnmadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
|
||||
vfnmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}
|
||||
vfnmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
|
||||
[(set_attr "isa" "fma,fma,fma,fma4,fma4")
|
||||
[(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4")
|
||||
(set_attr "type" "ssemuladd")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*fma_fnmsub_<mode>"
|
||||
[(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x,x,x")
|
||||
[(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x")
|
||||
(fma:FMAMODE
|
||||
(neg:FMAMODE
|
||||
(match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x, x,x"))
|
||||
(match_operand:FMAMODE 2 "nonimmediate_operand" "xm, x,xm,x,m")
|
||||
(match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0, v, x,x"))
|
||||
(match_operand:FMAMODE 2 "nonimmediate_operand" "vm, v,vm, x,m")
|
||||
(neg:FMAMODE
|
||||
(match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0,xm,x"))))]
|
||||
(match_operand:FMAMODE 3 "nonimmediate_operand" " v,vm, 0,xm,x"))))]
|
||||
"TARGET_FMA || TARGET_FMA4"
|
||||
"@
|
||||
vfnmsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
|
||||
@ -2168,7 +2228,7 @@
|
||||
vfnmsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
|
||||
vfnmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}
|
||||
vfnmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
|
||||
[(set_attr "isa" "fma,fma,fma,fma4,fma4")
|
||||
[(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4")
|
||||
(set_attr "type" "ssemuladd")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
@ -2193,11 +2253,11 @@
|
||||
"TARGET_FMA || TARGET_FMA4")
|
||||
|
||||
(define_insn "*fma_fmaddsub_<mode>"
|
||||
[(set (match_operand:VF 0 "register_operand" "=x,x,x,x,x")
|
||||
[(set (match_operand:VF 0 "register_operand" "=v,v,v,x,x")
|
||||
(unspec:VF
|
||||
[(match_operand:VF 1 "nonimmediate_operand" "%0, 0,x, x,x")
|
||||
(match_operand:VF 2 "nonimmediate_operand" "xm, x,xm,x,m")
|
||||
(match_operand:VF 3 "nonimmediate_operand" " x,xm,0,xm,x")]
|
||||
[(match_operand:VF 1 "nonimmediate_operand" "%0, 0, v, x,x")
|
||||
(match_operand:VF 2 "nonimmediate_operand" "vm, v,vm, x,m")
|
||||
(match_operand:VF 3 "nonimmediate_operand" " v,vm, 0,xm,x")]
|
||||
UNSPEC_FMADDSUB))]
|
||||
"TARGET_FMA || TARGET_FMA4"
|
||||
"@
|
||||
@ -2206,17 +2266,17 @@
|
||||
vfmaddsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
|
||||
vfmaddsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}
|
||||
vfmaddsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
|
||||
[(set_attr "isa" "fma,fma,fma,fma4,fma4")
|
||||
[(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4")
|
||||
(set_attr "type" "ssemuladd")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*fma_fmsubadd_<mode>"
|
||||
[(set (match_operand:VF 0 "register_operand" "=x,x,x,x,x")
|
||||
[(set (match_operand:VF 0 "register_operand" "=v,v,v,x,x")
|
||||
(unspec:VF
|
||||
[(match_operand:VF 1 "nonimmediate_operand" "%0, 0,x, x,x")
|
||||
(match_operand:VF 2 "nonimmediate_operand" "xm, x,xm,x,m")
|
||||
[(match_operand:VF 1 "nonimmediate_operand" "%0, 0, v, x,x")
|
||||
(match_operand:VF 2 "nonimmediate_operand" "vm, v,vm, x,m")
|
||||
(neg:VF
|
||||
(match_operand:VF 3 "nonimmediate_operand" " x,xm,0,xm,x"))]
|
||||
(match_operand:VF 3 "nonimmediate_operand" " v,vm, 0,xm,x"))]
|
||||
UNSPEC_FMADDSUB))]
|
||||
"TARGET_FMA || TARGET_FMA4"
|
||||
"@
|
||||
@ -2225,7 +2285,7 @@
|
||||
vfmsubadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
|
||||
vfmsubadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}
|
||||
vfmsubadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
|
||||
[(set_attr "isa" "fma,fma,fma,fma4,fma4")
|
||||
[(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4")
|
||||
(set_attr "type" "ssemuladd")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
@ -2244,12 +2304,12 @@
|
||||
"TARGET_FMA")
|
||||
|
||||
(define_insn "*fmai_fmadd_<mode>"
|
||||
[(set (match_operand:VF_128 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:VF_128 0 "register_operand" "=v,v")
|
||||
(vec_merge:VF_128
|
||||
(fma:VF_128
|
||||
(match_operand:VF_128 1 "nonimmediate_operand" " 0, 0")
|
||||
(match_operand:VF_128 2 "nonimmediate_operand" "xm, x")
|
||||
(match_operand:VF_128 3 "nonimmediate_operand" " x,xm"))
|
||||
(match_operand:VF_128 2 "nonimmediate_operand" "vm, v")
|
||||
(match_operand:VF_128 3 "nonimmediate_operand" " v,vm"))
|
||||
(match_dup 1)
|
||||
(const_int 1)))]
|
||||
"TARGET_FMA"
|
||||
@ -2260,13 +2320,13 @@
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*fmai_fmsub_<mode>"
|
||||
[(set (match_operand:VF_128 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:VF_128 0 "register_operand" "=v,v")
|
||||
(vec_merge:VF_128
|
||||
(fma:VF_128
|
||||
(match_operand:VF_128 1 "nonimmediate_operand" " 0, 0")
|
||||
(match_operand:VF_128 2 "nonimmediate_operand" "xm, x")
|
||||
(match_operand:VF_128 2 "nonimmediate_operand" "vm, v")
|
||||
(neg:VF_128
|
||||
(match_operand:VF_128 3 "nonimmediate_operand" " x,xm")))
|
||||
(match_operand:VF_128 3 "nonimmediate_operand" " v,vm")))
|
||||
(match_dup 1)
|
||||
(const_int 1)))]
|
||||
"TARGET_FMA"
|
||||
@ -2277,13 +2337,13 @@
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*fmai_fnmadd_<mode>"
|
||||
[(set (match_operand:VF_128 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:VF_128 0 "register_operand" "=v,v")
|
||||
(vec_merge:VF_128
|
||||
(fma:VF_128
|
||||
(neg:VF_128
|
||||
(match_operand:VF_128 2 "nonimmediate_operand" "xm, x"))
|
||||
(match_operand:VF_128 2 "nonimmediate_operand" "vm, v"))
|
||||
(match_operand:VF_128 1 "nonimmediate_operand" " 0, 0")
|
||||
(match_operand:VF_128 3 "nonimmediate_operand" " x,xm"))
|
||||
(match_operand:VF_128 3 "nonimmediate_operand" " v,vm"))
|
||||
(match_dup 1)
|
||||
(const_int 1)))]
|
||||
"TARGET_FMA"
|
||||
@ -2294,14 +2354,14 @@
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*fmai_fnmsub_<mode>"
|
||||
[(set (match_operand:VF_128 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:VF_128 0 "register_operand" "=v,v")
|
||||
(vec_merge:VF_128
|
||||
(fma:VF_128
|
||||
(neg:VF_128
|
||||
(match_operand:VF_128 2 "nonimmediate_operand" "xm, x"))
|
||||
(match_operand:VF_128 2 "nonimmediate_operand" "vm, v"))
|
||||
(match_operand:VF_128 1 "nonimmediate_operand" " 0, 0")
|
||||
(neg:VF_128
|
||||
(match_operand:VF_128 3 "nonimmediate_operand" " x,xm")))
|
||||
(match_operand:VF_128 3 "nonimmediate_operand" " v,vm")))
|
||||
(match_dup 1)
|
||||
(const_int 1)))]
|
||||
"TARGET_FMA"
|
||||
@ -2429,11 +2489,11 @@
|
||||
(set_attr "mode" "SF")])
|
||||
|
||||
(define_insn "sse_cvtsi2ss"
|
||||
[(set (match_operand:V4SF 0 "register_operand" "=x,x,x")
|
||||
[(set (match_operand:V4SF 0 "register_operand" "=x,x,v")
|
||||
(vec_merge:V4SF
|
||||
(vec_duplicate:V4SF
|
||||
(float:SF (match_operand:SI 2 "nonimmediate_operand" "r,m,rm")))
|
||||
(match_operand:V4SF 1 "register_operand" "0,0,x")
|
||||
(match_operand:V4SF 1 "register_operand" "0,0,v")
|
||||
(const_int 1)))]
|
||||
"TARGET_SSE"
|
||||
"@
|
||||
@ -2450,11 +2510,11 @@
|
||||
(set_attr "mode" "SF")])
|
||||
|
||||
(define_insn "sse_cvtsi2ssq"
|
||||
[(set (match_operand:V4SF 0 "register_operand" "=x,x,x")
|
||||
[(set (match_operand:V4SF 0 "register_operand" "=x,x,v")
|
||||
(vec_merge:V4SF
|
||||
(vec_duplicate:V4SF
|
||||
(float:SF (match_operand:DI 2 "nonimmediate_operand" "r,m,rm")))
|
||||
(match_operand:V4SF 1 "register_operand" "0,0,x")
|
||||
(match_operand:V4SF 1 "register_operand" "0,0,v")
|
||||
(const_int 1)))]
|
||||
"TARGET_SSE && TARGET_64BIT"
|
||||
"@
|
||||
@ -2476,7 +2536,7 @@
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
||||
(unspec:SI
|
||||
[(vec_select:SF
|
||||
(match_operand:V4SF 1 "nonimmediate_operand" "x,m")
|
||||
(match_operand:V4SF 1 "nonimmediate_operand" "v,m")
|
||||
(parallel [(const_int 0)]))]
|
||||
UNSPEC_FIX_NOTRUNC))]
|
||||
"TARGET_SSE"
|
||||
@ -2490,7 +2550,7 @@
|
||||
|
||||
(define_insn "sse_cvtss2si_2"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
||||
(unspec:SI [(match_operand:SF 1 "nonimmediate_operand" "x,m")]
|
||||
(unspec:SI [(match_operand:SF 1 "nonimmediate_operand" "v,m")]
|
||||
UNSPEC_FIX_NOTRUNC))]
|
||||
"TARGET_SSE"
|
||||
"%vcvtss2si\t{%1, %0|%0, %k1}"
|
||||
@ -2506,7 +2566,7 @@
|
||||
[(set (match_operand:DI 0 "register_operand" "=r,r")
|
||||
(unspec:DI
|
||||
[(vec_select:SF
|
||||
(match_operand:V4SF 1 "nonimmediate_operand" "x,m")
|
||||
(match_operand:V4SF 1 "nonimmediate_operand" "v,m")
|
||||
(parallel [(const_int 0)]))]
|
||||
UNSPEC_FIX_NOTRUNC))]
|
||||
"TARGET_SSE && TARGET_64BIT"
|
||||
@ -2536,7 +2596,7 @@
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
||||
(fix:SI
|
||||
(vec_select:SF
|
||||
(match_operand:V4SF 1 "nonimmediate_operand" "x,m")
|
||||
(match_operand:V4SF 1 "nonimmediate_operand" "v,m")
|
||||
(parallel [(const_int 0)]))))]
|
||||
"TARGET_SSE"
|
||||
"%vcvttss2si\t{%1, %0|%0, %k1}"
|
||||
@ -2552,7 +2612,7 @@
|
||||
[(set (match_operand:DI 0 "register_operand" "=r,r")
|
||||
(fix:DI
|
||||
(vec_select:SF
|
||||
(match_operand:V4SF 1 "nonimmediate_operand" "x,m")
|
||||
(match_operand:V4SF 1 "nonimmediate_operand" "v,m")
|
||||
(parallel [(const_int 0)]))))]
|
||||
"TARGET_SSE && TARGET_64BIT"
|
||||
"%vcvttss2si{q}\t{%1, %0|%0, %k1}"
|
||||
@ -2565,9 +2625,9 @@
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
(define_insn "float<sseintvecmodelower><mode>2"
|
||||
[(set (match_operand:VF1 0 "register_operand" "=x")
|
||||
[(set (match_operand:VF1 0 "register_operand" "=v")
|
||||
(float:VF1
|
||||
(match_operand:<sseintvecmode> 1 "nonimmediate_operand" "xm")))]
|
||||
(match_operand:<sseintvecmode> 1 "nonimmediate_operand" "vm")))]
|
||||
"TARGET_SSE2"
|
||||
"%vcvtdq2ps\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssecvt")
|
||||
@ -2752,7 +2812,7 @@
|
||||
|
||||
(define_insn "sse2_cvtsd2si_2"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
||||
(unspec:SI [(match_operand:DF 1 "nonimmediate_operand" "x,m")]
|
||||
(unspec:SI [(match_operand:DF 1 "nonimmediate_operand" "v,m")]
|
||||
UNSPEC_FIX_NOTRUNC))]
|
||||
"TARGET_SSE2"
|
||||
"%vcvtsd2si\t{%1, %0|%0, %q1}"
|
||||
@ -2782,7 +2842,7 @@
|
||||
|
||||
(define_insn "sse2_cvtsd2siq_2"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r,r")
|
||||
(unspec:DI [(match_operand:DF 1 "nonimmediate_operand" "x,m")]
|
||||
(unspec:DI [(match_operand:DF 1 "nonimmediate_operand" "v,m")]
|
||||
UNSPEC_FIX_NOTRUNC))]
|
||||
"TARGET_SSE2 && TARGET_64BIT"
|
||||
"%vcvtsd2si{q}\t{%1, %0|%0, %q1}"
|
||||
@ -2981,12 +3041,12 @@
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_insn "sse2_cvtsd2ss"
|
||||
[(set (match_operand:V4SF 0 "register_operand" "=x,x,x")
|
||||
[(set (match_operand:V4SF 0 "register_operand" "=x,x,v")
|
||||
(vec_merge:V4SF
|
||||
(vec_duplicate:V4SF
|
||||
(float_truncate:V2SF
|
||||
(match_operand:V2DF 2 "nonimmediate_operand" "x,m,xm")))
|
||||
(match_operand:V4SF 1 "register_operand" "0,0,x")
|
||||
(match_operand:V2DF 2 "nonimmediate_operand" "x,m,vm")))
|
||||
(match_operand:V4SF 1 "register_operand" "0,0,v")
|
||||
(const_int 1)))]
|
||||
"TARGET_SSE2"
|
||||
"@
|
||||
@ -3003,13 +3063,13 @@
|
||||
(set_attr "mode" "SF")])
|
||||
|
||||
(define_insn "sse2_cvtss2sd"
|
||||
[(set (match_operand:V2DF 0 "register_operand" "=x,x,x")
|
||||
[(set (match_operand:V2DF 0 "register_operand" "=x,x,v")
|
||||
(vec_merge:V2DF
|
||||
(float_extend:V2DF
|
||||
(vec_select:V2SF
|
||||
(match_operand:V4SF 2 "nonimmediate_operand" "x,m,xm")
|
||||
(match_operand:V4SF 2 "nonimmediate_operand" "x,m,vm")
|
||||
(parallel [(const_int 0) (const_int 1)])))
|
||||
(match_operand:V2DF 1 "register_operand" "0,0,x")
|
||||
(match_operand:V2DF 1 "register_operand" "0,0,v")
|
||||
(const_int 1)))]
|
||||
"TARGET_SSE2"
|
||||
"@
|
||||
@ -5243,10 +5303,10 @@
|
||||
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
|
||||
|
||||
(define_insn "*<plusminus_insn><mode>3"
|
||||
[(set (match_operand:VI_AVX2 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:VI_AVX2 0 "register_operand" "=x,v")
|
||||
(plusminus:VI_AVX2
|
||||
(match_operand:VI_AVX2 1 "nonimmediate_operand" "<comm>0,x")
|
||||
(match_operand:VI_AVX2 2 "nonimmediate_operand" "xm,xm")))]
|
||||
(match_operand:VI_AVX2 1 "nonimmediate_operand" "<comm>0,v")
|
||||
(match_operand:VI_AVX2 2 "nonimmediate_operand" "xm,vm")))]
|
||||
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
|
||||
"@
|
||||
p<plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2}
|
||||
@ -5266,10 +5326,10 @@
|
||||
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
|
||||
|
||||
(define_insn "*<sse2_avx2>_<plusminus_insn><mode>3"
|
||||
[(set (match_operand:VI12_AVX2 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:VI12_AVX2 0 "register_operand" "=x,v")
|
||||
(sat_plusminus:VI12_AVX2
|
||||
(match_operand:VI12_AVX2 1 "nonimmediate_operand" "<comm>0,x")
|
||||
(match_operand:VI12_AVX2 2 "nonimmediate_operand" "xm,xm")))]
|
||||
(match_operand:VI12_AVX2 1 "nonimmediate_operand" "<comm>0,v")
|
||||
(match_operand:VI12_AVX2 2 "nonimmediate_operand" "xm,vm")))]
|
||||
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
|
||||
"@
|
||||
p<plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2}
|
||||
@ -5641,10 +5701,10 @@
|
||||
})
|
||||
|
||||
(define_insn "*<sse4_1_avx2>_mul<mode>3"
|
||||
[(set (match_operand:VI4_AVX2 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:VI4_AVX2 0 "register_operand" "=x,v")
|
||||
(mult:VI4_AVX2
|
||||
(match_operand:VI4_AVX2 1 "nonimmediate_operand" "%0,x")
|
||||
(match_operand:VI4_AVX2 2 "nonimmediate_operand" "xm,xm")))]
|
||||
(match_operand:VI4_AVX2 1 "nonimmediate_operand" "%0,v")
|
||||
(match_operand:VI4_AVX2 2 "nonimmediate_operand" "xm,vm")))]
|
||||
"TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
|
||||
"@
|
||||
pmulld\t{%2, %0|%0, %2}
|
||||
@ -5765,9 +5825,9 @@
|
||||
(set_attr "mode" "<sseinsnmode>")])
|
||||
|
||||
(define_insn "<shift_insn><mode>3"
|
||||
[(set (match_operand:VI248_AVX2 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:VI248_AVX2 0 "register_operand" "=x,v")
|
||||
(any_lshift:VI248_AVX2
|
||||
(match_operand:VI248_AVX2 1 "register_operand" "0,x")
|
||||
(match_operand:VI248_AVX2 1 "register_operand" "0,v")
|
||||
(match_operand:SI 2 "nonmemory_operand" "xN,xN")))]
|
||||
"TARGET_SSE2"
|
||||
"@
|
||||
@ -5868,10 +5928,10 @@
|
||||
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
|
||||
|
||||
(define_insn "*avx2_<code><mode>3"
|
||||
[(set (match_operand:VI124_256 0 "register_operand" "=x")
|
||||
[(set (match_operand:VI124_256 0 "register_operand" "=v")
|
||||
(maxmin:VI124_256
|
||||
(match_operand:VI124_256 1 "nonimmediate_operand" "%x")
|
||||
(match_operand:VI124_256 2 "nonimmediate_operand" "xm")))]
|
||||
(match_operand:VI124_256 1 "nonimmediate_operand" "%v")
|
||||
(match_operand:VI124_256 2 "nonimmediate_operand" "vm")))]
|
||||
"TARGET_AVX2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
|
||||
"vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "type" "sseiadd")
|
||||
@ -6345,10 +6405,10 @@
|
||||
"TARGET_SSE2")
|
||||
|
||||
(define_insn "*andnot<mode>3"
|
||||
[(set (match_operand:VI 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:VI 0 "register_operand" "=x,v")
|
||||
(and:VI
|
||||
(not:VI (match_operand:VI 1 "register_operand" "0,x"))
|
||||
(match_operand:VI 2 "nonimmediate_operand" "xm,xm")))]
|
||||
(not:VI (match_operand:VI 1 "register_operand" "0,v"))
|
||||
(match_operand:VI 2 "nonimmediate_operand" "xm,vm")))]
|
||||
"TARGET_SSE"
|
||||
{
|
||||
static char buf[32];
|
||||
@ -6429,10 +6489,10 @@
|
||||
})
|
||||
|
||||
(define_insn "*<code><mode>3"
|
||||
[(set (match_operand:VI 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:VI 0 "register_operand" "=x,v")
|
||||
(any_logic:VI
|
||||
(match_operand:VI 1 "nonimmediate_operand" "%0,x")
|
||||
(match_operand:VI 2 "nonimmediate_operand" "xm,xm")))]
|
||||
(match_operand:VI 1 "nonimmediate_operand" "%0,v")
|
||||
(match_operand:VI 2 "nonimmediate_operand" "xm,vm")))]
|
||||
"TARGET_SSE
|
||||
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
|
||||
{
|
||||
@ -8368,9 +8428,9 @@
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
(define_insn "abs<mode>2"
|
||||
[(set (match_operand:VI124_AVX2 0 "register_operand" "=x")
|
||||
[(set (match_operand:VI124_AVX2 0 "register_operand" "=v")
|
||||
(abs:VI124_AVX2
|
||||
(match_operand:VI124_AVX2 1 "nonimmediate_operand" "xm")))]
|
||||
(match_operand:VI124_AVX2 1 "nonimmediate_operand" "vm")))]
|
||||
"TARGET_SSSE3"
|
||||
"%vpabs<ssemodesuffix>\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "sselog1")
|
||||
@ -10481,10 +10541,10 @@
|
||||
(set_attr "mode" "<sseinsnmode>")])
|
||||
|
||||
(define_insn "avx2_permvar<mode>"
|
||||
[(set (match_operand:VI4F_256 0 "register_operand" "=x")
|
||||
[(set (match_operand:VI4F_256 0 "register_operand" "=v")
|
||||
(unspec:VI4F_256
|
||||
[(match_operand:VI4F_256 1 "nonimmediate_operand" "xm")
|
||||
(match_operand:V8SI 2 "register_operand" "x")]
|
||||
[(match_operand:VI4F_256 1 "nonimmediate_operand" "vm")
|
||||
(match_operand:V8SI 2 "register_operand" "v")]
|
||||
UNSPEC_VPERMVAR))]
|
||||
"TARGET_AVX2"
|
||||
"vperm<ssemodesuffix>\t{%1, %2, %0|%0, %2, %1}"
|
||||
@ -10508,9 +10568,9 @@
|
||||
})
|
||||
|
||||
(define_insn "avx2_perm<mode>_1"
|
||||
[(set (match_operand:VI8F_256 0 "register_operand" "=x")
|
||||
[(set (match_operand:VI8F_256 0 "register_operand" "=v")
|
||||
(vec_select:VI8F_256
|
||||
(match_operand:VI8F_256 1 "nonimmediate_operand" "xm")
|
||||
(match_operand:VI8F_256 1 "nonimmediate_operand" "vm")
|
||||
(parallel [(match_operand 2 "const_0_to_3_operand")
|
||||
(match_operand 3 "const_0_to_3_operand")
|
||||
(match_operand 4 "const_0_to_3_operand")
|
||||
@ -10735,9 +10795,9 @@
|
||||
})
|
||||
|
||||
(define_insn "*avx_vpermilp<mode>"
|
||||
[(set (match_operand:VF 0 "register_operand" "=x")
|
||||
[(set (match_operand:VF 0 "register_operand" "=v")
|
||||
(vec_select:VF
|
||||
(match_operand:VF 1 "nonimmediate_operand" "xm")
|
||||
(match_operand:VF 1 "nonimmediate_operand" "vm")
|
||||
(match_parallel 2 ""
|
||||
[(match_operand 3 "const_int_operand")])))]
|
||||
"TARGET_AVX
|
||||
@ -10754,10 +10814,10 @@
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "avx_vpermilvar<mode>3"
|
||||
[(set (match_operand:VF 0 "register_operand" "=x")
|
||||
[(set (match_operand:VF 0 "register_operand" "=v")
|
||||
(unspec:VF
|
||||
[(match_operand:VF 1 "register_operand" "x")
|
||||
(match_operand:<sseintvecmode> 2 "nonimmediate_operand" "xm")]
|
||||
[(match_operand:VF 1 "register_operand" "v")
|
||||
(match_operand:<sseintvecmode> 2 "nonimmediate_operand" "vm")]
|
||||
UNSPEC_VPERMIL))]
|
||||
"TARGET_AVX"
|
||||
"vpermil<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
|
||||
@ -11149,10 +11209,10 @@
|
||||
})
|
||||
|
||||
(define_insn "avx2_ashrv<mode>"
|
||||
[(set (match_operand:VI4_AVX2 0 "register_operand" "=x")
|
||||
[(set (match_operand:VI4_AVX2 0 "register_operand" "=v")
|
||||
(ashiftrt:VI4_AVX2
|
||||
(match_operand:VI4_AVX2 1 "register_operand" "x")
|
||||
(match_operand:VI4_AVX2 2 "nonimmediate_operand" "xm")))]
|
||||
(match_operand:VI4_AVX2 1 "register_operand" "v")
|
||||
(match_operand:VI4_AVX2 2 "nonimmediate_operand" "vm")))]
|
||||
"TARGET_AVX2"
|
||||
"vpsravd\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "type" "sseishft")
|
||||
@ -11160,10 +11220,10 @@
|
||||
(set_attr "mode" "<sseinsnmode>")])
|
||||
|
||||
(define_insn "avx2_<shift_insn>v<mode>"
|
||||
[(set (match_operand:VI48_AVX2 0 "register_operand" "=x")
|
||||
[(set (match_operand:VI48_AVX2 0 "register_operand" "=v")
|
||||
(any_lshift:VI48_AVX2
|
||||
(match_operand:VI48_AVX2 1 "register_operand" "x")
|
||||
(match_operand:VI48_AVX2 2 "nonimmediate_operand" "xm")))]
|
||||
(match_operand:VI48_AVX2 1 "register_operand" "v")
|
||||
(match_operand:VI48_AVX2 2 "nonimmediate_operand" "vm")))]
|
||||
"TARGET_AVX2"
|
||||
"vp<vshift>v<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "type" "sseishft")
|
||||
|
||||
@ -648,7 +648,8 @@ Objective-C and Objective-C++ Dialects}.
|
||||
-mrecip -mrecip=@var{opt} @gol
|
||||
-mvzeroupper -mprefer-avx128 @gol
|
||||
-mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol
|
||||
-mavx2 -maes -mpclmul -mfsgsbase -mrdrnd -mf16c -mfma @gol
|
||||
-mavx2 -mavx512f -mavx512pf -mavx512er -mavx512cd @gol
|
||||
-maes -mpclmul -mfsgsbase -mrdrnd -mf16c -mfma @gol
|
||||
-msse4a -m3dnow -mpopcnt -mabm -mbmi -mtbm -mfma4 -mxop -mlzcnt @gol
|
||||
-mbmi2 -mrtm -mlwp -mthreads @gol
|
||||
-mno-align-stringops -minline-all-stringops @gol
|
||||
@ -14368,11 +14369,20 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
|
||||
@itemx -mno-avx
|
||||
@itemx -mavx2
|
||||
@itemx -mno-avx2
|
||||
@itemx -mavx512f
|
||||
@itemx -mno-avx512f
|
||||
@need 800
|
||||
@itemx -mavx512pf
|
||||
@itemx -mno-avx512pf
|
||||
@itemx -mavx512er
|
||||
@itemx -mno-avx512er
|
||||
@itemx -mavx512cd
|
||||
@itemx -mno-avx512cd
|
||||
@itemx -maes
|
||||
@itemx -mno-aes
|
||||
@itemx -mpclmul
|
||||
@need 800
|
||||
@itemx -mno-pclmul
|
||||
@need 800
|
||||
@itemx -mfsgsbase
|
||||
@itemx -mno-fsgsbase
|
||||
@itemx -mrdrnd
|
||||
@ -14384,8 +14394,8 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
|
||||
@itemx -msse4a
|
||||
@itemx -mno-sse4a
|
||||
@itemx -mfma4
|
||||
@need 800
|
||||
@itemx -mno-fma4
|
||||
@need 800
|
||||
@itemx -mxop
|
||||
@itemx -mno-xop
|
||||
@itemx -mlwp
|
||||
@ -14412,8 +14422,9 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
|
||||
@opindex m3dnow
|
||||
@opindex mno-3dnow
|
||||
These switches enable or disable the use of instructions in the MMX, SSE,
|
||||
SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, F16C,
|
||||
FMA, SSE4A, FMA4, XOP, LWP, ABM, BMI, BMI2, LZCNT, RTM or 3DNow!@:
|
||||
SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD,
|
||||
AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM, BMI, BMI2,
|
||||
LZCNT, RTM or 3DNow!@:
|
||||
extended instruction sets.
|
||||
These extensions are also available as built-in functions: see
|
||||
@ref{X86 Built-in Functions}, for details of the functions enabled and
|
||||
|
||||
@ -1097,6 +1097,10 @@ this is the right mode to use for certain pointers.
|
||||
@item OImode
|
||||
``Octa Integer'' (?) mode represents a thirty-two-byte integer.
|
||||
|
||||
@findex XImode
|
||||
@item XImode
|
||||
``Hexadeca Integer'' (?) mode represents a sixty-four-byte integer.
|
||||
|
||||
@findex QFmode
|
||||
@item QFmode
|
||||
``Quarter-Floating'' mode represents a quarter-precision (single byte)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user