bfin.md (define_attr "type"): Add "sync".
* config/bfin/bfin.md (define_attr "type"): Add "sync". (define_insn_reservation "alu"): Likewise. (csync, ssync): Now of type sync. * config/bfin/bfin.h (TARGET_DEFAULT): Defaults to -mcsync-anomaly -mspecld-anomaly. * config/bfin/bfin.opt (mcsync): Remove. (mcsync-anomaly, mspecld-anomaly): Add. * config/bfin/bfin.c: Include "insn-codes.h". (bfin_reorg): Extend to handle the CSYNC anomaly as well. (TARGET_DEFAULT_TARGET_FLAGS): New. * doc/invoke.texi: Document -mcsync-anomaly, -mspecld-anomaly. From-SVN: r101880
This commit is contained in:
Bernd Schmidt
Bernd Schmidt
parent
2dd2d53e2c
commit
3fb192d2c7
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@ -1,3 +1,17 @@
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2005-07-11 Bernd Schmidt <bernd.schmidt@analog.com>
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* config/bfin/bfin.md (define_attr "type"): Add "sync".
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(define_insn_reservation "alu"): Likewise.
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(csync, ssync): Now of type sync.
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* config/bfin/bfin.h (TARGET_DEFAULT): Defaults to
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-mcsync-anomaly -mspecld-anomaly.
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* config/bfin/bfin.opt (mcsync): Remove.
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(mcsync-anomaly, mspecld-anomaly): Add.
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* config/bfin/bfin.c: Include "insn-codes.h".
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(bfin_reorg): Extend to handle the CSYNC anomaly as well.
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(TARGET_DEFAULT_TARGET_FLAGS): New.
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* doc/invoke.texi: Document -mcsync-anomaly, -mspecld-anomaly.
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2005-07-11 Steven Bosscher <stevenb@suse.de>
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* basic-block.h: Give the BB flags enum a name, bb_flags.
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@ -28,6 +28,7 @@
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#include "hard-reg-set.h"
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#include "real.h"
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#include "insn-config.h"
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#include "insn-codes.h"
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#include "conditions.h"
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#include "insn-flags.h"
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#include "output.h"
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@ -2470,9 +2471,11 @@ bfin_reorg (void)
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rtx insn, last_condjump = NULL_RTX;
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int cycles_since_jump = INT_MAX;
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if (! TARGET_CSYNC)
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if (! TARGET_SPECLD_ANOMALY || ! TARGET_CSYNC_ANOMALY)
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return;
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/* First pass: find predicted-false branches; if something after them
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needs nops, insert them or change the branch to predict true. */
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for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
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{
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rtx pat;
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@ -2500,29 +2503,109 @@ bfin_reorg (void)
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else if (INSN_P (insn))
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{
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enum attr_type type = get_attr_type (insn);
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int delay_needed = 0;
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if (cycles_since_jump < INT_MAX)
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cycles_since_jump++;
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if (type == TYPE_MCLD && cycles_since_jump < 3)
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if (type == TYPE_MCLD && TARGET_SPECLD_ANOMALY)
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{
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rtx pat = single_set (insn);
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if (may_trap_p (SET_SRC (pat)))
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delay_needed = 3;
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}
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else if (type == TYPE_SYNC && TARGET_CSYNC_ANOMALY)
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delay_needed = 4;
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if (delay_needed > cycles_since_jump)
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{
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rtx pat;
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int num_clobbers;
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rtx *op = recog_data.operand;
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delay_needed -= cycles_since_jump;
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extract_insn (last_condjump);
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if (optimize_size)
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{
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pat = gen_cbranch_predicted_taken (op[0], op[1], op[2],
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op[3]);
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cycles_since_jump = INT_MAX;
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}
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else
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/* Do not adjust cycles_since_jump in this case, so that
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we'll increase the number of NOPs for a subsequent insn
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if necessary. */
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pat = gen_cbranch_with_nops (op[0], op[1], op[2], op[3],
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GEN_INT (delay_needed));
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PATTERN (last_condjump) = pat;
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INSN_CODE (last_condjump) = recog (pat, insn, &num_clobbers);
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}
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}
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}
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/* Second pass: for predicted-true branches, see if anything at the
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branch destination needs extra nops. */
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if (! TARGET_CSYNC_ANOMALY)
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return;
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for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
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{
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if (JUMP_P (insn)
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&& any_condjump_p (insn)
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&& (INSN_CODE (insn) == CODE_FOR_cbranch_predicted_taken
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|| cbranch_predicted_taken_p (insn)))
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{
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rtx target = JUMP_LABEL (insn);
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rtx label = target;
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cycles_since_jump = 0;
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for (; target && cycles_since_jump < 3; target = NEXT_INSN (target))
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{
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rtx pat;
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pat = single_set (insn);
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if (may_trap_p (SET_SRC (pat)))
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{
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int num_clobbers;
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rtx *op = recog_data.operand;
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if (NOTE_P (target) || BARRIER_P (target) || LABEL_P (target))
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continue;
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extract_insn (last_condjump);
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if (optimize_size)
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pat = gen_cbranch_predicted_taken (op[0], op[1], op[2],
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op[3]);
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else
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pat = gen_cbranch_with_nops (op[0], op[1], op[2], op[3],
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GEN_INT (3 - cycles_since_jump));
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PATTERN (last_condjump) = pat;
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INSN_CODE (last_condjump) = recog (pat, insn, &num_clobbers);
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cycles_since_jump = INT_MAX;
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pat = PATTERN (target);
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if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER
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|| GET_CODE (pat) == ASM_INPUT || GET_CODE (pat) == ADDR_VEC
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|| GET_CODE (pat) == ADDR_DIFF_VEC || asm_noperands (pat) >= 0)
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continue;
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if (INSN_P (target))
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{
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enum attr_type type = get_attr_type (target);
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int delay_needed = 0;
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if (cycles_since_jump < INT_MAX)
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cycles_since_jump++;
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if (type == TYPE_SYNC && TARGET_CSYNC_ANOMALY)
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delay_needed = 2;
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if (delay_needed > cycles_since_jump)
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{
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rtx prev = prev_real_insn (label);
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delay_needed -= cycles_since_jump;
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if (dump_file)
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fprintf (dump_file, "Adding %d nops after %d\n",
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delay_needed, INSN_UID (label));
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if (JUMP_P (prev)
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&& INSN_CODE (prev) == CODE_FOR_cbranch_with_nops)
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{
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rtx x;
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HOST_WIDE_INT v;
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if (dump_file)
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fprintf (dump_file,
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"Reducing nops on insn %d.\n",
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INSN_UID (prev));
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x = PATTERN (prev);
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x = XVECEXP (x, 0, 1);
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v = INTVAL (XVECEXP (x, 0, 0)) - delay_needed;
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XVECEXP (x, 0, 0) = GEN_INT (v);
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}
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while (delay_needed-- > 0)
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emit_insn_after (gen_nop (), label);
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break;
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}
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}
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}
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}
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@ -2792,4 +2875,7 @@ bfin_expand_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
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#undef TARGET_HANDLE_OPTION
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#define TARGET_HANDLE_OPTION bfin_handle_option
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#undef TARGET_DEFAULT_TARGET_FLAGS
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#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
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struct gcc_target targetm = TARGET_INITIALIZER;
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@ -48,7 +48,7 @@ extern int target_flags;
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/* Generate DSP instructions, like DSP halfword loads */
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#define TARGET_DSP (1)
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#define TARGET_DEFAULT MASK_CSYNC
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#define TARGET_DEFAULT (MASK_SPECLD_ANOMALY | MASK_CSYNC_ANOMALY)
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/* Maximum number of library ids we permit */
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#define MAX_LIBRARY_ID 255
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@ -125,7 +125,7 @@
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(UNSPEC_VOLATILE_SSYNC 2)])
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(define_attr "type"
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"move,mvi,mcld,mcst,dsp32,mult,alu0,shft,brcc,br,call,misc,compare,dummy"
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"move,mvi,mcld,mcst,dsp32,mult,alu0,shft,brcc,br,call,misc,sync,compare,dummy"
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(const_string "misc"))
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;; Scheduling definitions
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@ -135,7 +135,7 @@
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(define_cpu_unit "core" "bfin")
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(define_insn_reservation "alu" 1
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(eq_attr "type" "move,mvi,mcst,dsp32,alu0,shft,brcc,br,call,misc,compare")
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(eq_attr "type" "move,mvi,mcst,dsp32,alu0,shft,brcc,br,call,misc,sync,compare")
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"core")
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(define_insn_reservation "imul" 3
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@ -1931,13 +1931,13 @@
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[(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_CSYNC)]
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""
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"csync;"
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[(set_attr "type" "misc")])
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[(set_attr "type" "sync")])
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(define_insn "ssync"
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[(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_SSYNC)]
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""
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"ssync;"
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[(set_attr "type" "misc")])
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[(set_attr "type" "sync")])
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;;; Vector instructions
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@ -27,9 +27,14 @@ mlow64k
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Target Report Mask(LOW_64K)
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Program is entirely located in low 64k of memory
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mcsync
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Target Report Mask(CSYNC)
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Avoid speculative loads by inserting CSYNC or equivalent
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mcsync-anomaly
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Target Report Mask(CSYNC_ANOMALY)
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Work around a hardware anomaly by adding a number of NOPs before a
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CSYNC or SSYNC instruction.
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mspecld-anomaly
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Target Report Mask(SPECLD_ANOMALY)
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Avoid speculative loads to work around a hardware anomaly.
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mid-shared-library
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Target Report Mask(ID_SHARED_LIBRARY)
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@ -414,8 +414,9 @@ Objective-C and Objective-C++ Dialects}.
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-mcall-prologues -mno-tablejump -mtiny-stack -mint8}
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@emph{Blackfin Options}
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@gccoptlist{-momit-leaf-frame-pointer -mno-omit-leaf-frame-pointer -mcsync @gol
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-mno-csync -mlow-64k -mno-low64k -mid-shared-library @gol
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@gccoptlist{-momit-leaf-frame-pointer -mno-omit-leaf-frame-pointer @gol
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-mspecld-anomaly -mno-specld-anomaly -mcsync-anomaly -mno-csync-anomaly @gol
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-mlow-64k -mno-low64k -mid-shared-library @gol
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-mno-id-shared-library -mshared-library-id=@var{n} @gol
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-mlong-calls -mno-long-calls}
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@ -7403,16 +7404,27 @@ makes an extra register available in leaf functions. The option
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@option{-fomit-frame-pointer} removes the frame pointer for all functions
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which might make debugging harder.
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@item -mcsync
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@opindex mcsync
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@item -mspecld-anomaly
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@opindex mspecld-anomaly
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When enabled, the compiler will ensure that the generated code does not
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contain speculative loads after jump instructions. This option is enabled
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by default.
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@item -mno-csync
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@opindex mno-csync
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@item -mno-specld-anomaly
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@opindex mno-specld-anomaly
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Don't generate extra code to prevent speculative loads from occurring.
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@item -mcsync-anomaly
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@opindex mspecld-anomaly
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When enabled, the compiler will ensure that the generated code does not
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contain CSYNC or SSYNC instructions too soon after conditional branches.
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This option is enabled by default.
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@item -mno-csync-anomaly
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@opindex mno-specld-anomaly
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Don't generate extra code to prevent CSYNC or SSYNC instructions from
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occurring too soon after a conditional branch.
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@item -mlow-64k
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@opindex mlow-64k
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When enabled, the compiler is free to take advantage of the knowledge that
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