aarch64: Use RTL builtins for integer mls_n intrinsics
Rewrite integer mls_n Neon intrinsics to use RTL builtins rather than inline assembly code, allowing for better scheduling and optimization. gcc/ChangeLog: 2021-01-15 Jonathan Wright <jonathan.wright@arm.com> * config/aarch64/aarch64-simd-builtins.def: Add mls_n builtin generator macro. * config/aarch64/aarch64-simd.md (*aarch64_mls_elt_merge<mode>): Rename to... (aarch64_mls_n<mode>): This. * config/aarch64/arm_neon.h (vmls_n_s16): Use RTL builtin instead of asm. (vmls_n_s32): Likewise. (vmls_n_u16): Likewise. (vmls_n_u32): Likewise. (vmlsq_n_s16): Likewise. (vmlsq_n_s32): Likewise. (vmlsq_n_u16): Likewise. (vmlsq_n_u32): Likewise.
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Jonathan Wright
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@ -185,6 +185,8 @@
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/* Implemented by aarch64_mls<mode>. */
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BUILTIN_VDQ_BHSI (TERNOP, mls, 0, NONE)
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/* Implemented by aarch64_mls_n<mode>. */
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BUILTIN_VDQHS (TERNOP, mls_n, 0, NONE)
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/* Implemented by aarch64_<su>mlsl<mode>. */
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BUILTIN_VD_BHSI (TERNOP, smlsl, 0, NONE)
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@ -1443,15 +1443,16 @@
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[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
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)
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(define_insn "*aarch64_mls_elt_merge<mode>"
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(define_insn "aarch64_mls_n<mode>"
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[(set (match_operand:VDQHS 0 "register_operand" "=w")
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(minus:VDQHS
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(match_operand:VDQHS 1 "register_operand" "0")
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(mult:VDQHS (vec_duplicate:VDQHS
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(match_operand:<VEL> 2 "register_operand" "<h_con>"))
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(match_operand:VDQHS 3 "register_operand" "w"))))]
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(mult:VDQHS
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(vec_duplicate:VDQHS
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(match_operand:<VEL> 3 "register_operand" "<h_con>"))
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(match_operand:VDQHS 2 "register_operand" "w"))))]
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"TARGET_SIMD"
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"mls\t%0.<Vtype>, %3.<Vtype>, %2.<Vetype>[0]"
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"mls\t%0.<Vtype>, %2.<Vtype>, %3.<Vetype>[0]"
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[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
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)
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@ -7840,48 +7840,32 @@ __extension__ extern __inline int16x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmls_n_s16 (int16x4_t __a, int16x4_t __b, int16_t __c)
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{
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int16x4_t __result;
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__asm__ ("mls %0.4h, %2.4h, %3.h[0]"
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: "=w"(__result)
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: "0"(__a), "w"(__b), "x"(__c)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_mls_nv4hi (__a, __b, __c);
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}
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__extension__ extern __inline int32x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmls_n_s32 (int32x2_t __a, int32x2_t __b, int32_t __c)
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{
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int32x2_t __result;
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__asm__ ("mls %0.2s, %2.2s, %3.s[0]"
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: "=w"(__result)
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: "0"(__a), "w"(__b), "w"(__c)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_mls_nv2si (__a, __b, __c);
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}
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__extension__ extern __inline uint16x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmls_n_u16 (uint16x4_t __a, uint16x4_t __b, uint16_t __c)
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{
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uint16x4_t __result;
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__asm__ ("mls %0.4h, %2.4h, %3.h[0]"
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: "=w"(__result)
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: "0"(__a), "w"(__b), "x"(__c)
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: /* No clobbers */);
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return __result;
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return (uint16x4_t) __builtin_aarch64_mls_nv4hi ((int16x4_t) __a,
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(int16x4_t) __b,
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(int16_t) __c);
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}
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__extension__ extern __inline uint32x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmls_n_u32 (uint32x2_t __a, uint32x2_t __b, uint32_t __c)
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{
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uint32x2_t __result;
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__asm__ ("mls %0.2s, %2.2s, %3.s[0]"
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: "=w"(__result)
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: "0"(__a), "w"(__b), "w"(__c)
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: /* No clobbers */);
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return __result;
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return (uint32x2_t) __builtin_aarch64_mls_nv2si ((int32x2_t) __a,
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(int32x2_t) __b,
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(int32_t) __c);
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}
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__extension__ extern __inline int8x8_t
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@ -8353,48 +8337,32 @@ __extension__ extern __inline int16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmlsq_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c)
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{
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int16x8_t __result;
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__asm__ ("mls %0.8h, %2.8h, %3.h[0]"
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: "=w"(__result)
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: "0"(__a), "w"(__b), "x"(__c)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_mls_nv8hi (__a, __b, __c);
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}
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__extension__ extern __inline int32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmlsq_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c)
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{
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int32x4_t __result;
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__asm__ ("mls %0.4s, %2.4s, %3.s[0]"
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: "=w"(__result)
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: "0"(__a), "w"(__b), "w"(__c)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_mls_nv4si (__a, __b, __c);
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}
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__extension__ extern __inline uint16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmlsq_n_u16 (uint16x8_t __a, uint16x8_t __b, uint16_t __c)
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{
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uint16x8_t __result;
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__asm__ ("mls %0.8h, %2.8h, %3.h[0]"
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: "=w"(__result)
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: "0"(__a), "w"(__b), "x"(__c)
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: /* No clobbers */);
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return __result;
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return (uint16x8_t) __builtin_aarch64_mls_nv8hi ((int16x8_t) __a,
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(int16x8_t) __b,
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(int16_t) __c);
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}
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__extension__ extern __inline uint32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmlsq_n_u32 (uint32x4_t __a, uint32x4_t __b, uint32_t __c)
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{
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uint32x4_t __result;
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__asm__ ("mls %0.4s, %2.4s, %3.s[0]"
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: "=w"(__result)
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: "0"(__a), "w"(__b), "w"(__c)
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: /* No clobbers */);
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return __result;
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return (uint32x4_t) __builtin_aarch64_mls_nv4si ((int32x4_t) __a,
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(int32x4_t) __b,
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(int32_t) __c);
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}
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__extension__ extern __inline int8x16_t
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