msp430.c (msp430_expand_epilogue): Fix compile time warning message.
* config/msp430/msp430.c (msp430_expand_epilogue): Fix compile time warning message. (msp430_print_operand_raw): Delete unused letter parameter. (TARGET_PRINT_OPERAND_ADDRESS): Define. (msp430_print_operand_address): New function. (msp430_print_operand): Move address printing code from here to new function. * config/msp430/msp430.md (movsipsi2): Add comment in generated assembler. (zero_extendpsisi2): Likewise. (extendpsisi2): New pattern. (andneghi3): New pattern. From-SVN: r202941
This commit is contained in:
Nick Clifton
Nick Clifton
parent
38e8f66392
commit
40ada30a79
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@ -1,3 +1,18 @@
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2013-09-26 Nick Clifton <nickc@redhat.com>
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* config/msp430/msp430.c (msp430_expand_epilogue): Fix compile
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time warning message.
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(msp430_print_operand_raw): Delete unused letter parameter.
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(TARGET_PRINT_OPERAND_ADDRESS): Define.
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(msp430_print_operand_address): New function.
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(msp430_print_operand): Move address printing code from here to
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new function.
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* config/msp430/msp430.md (movsipsi2): Add comment in generated
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assembler.
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(zero_extendpsisi2): Likewise.
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(extendpsisi2): New pattern.
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(andneghi3): New pattern.
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2013-09-26 Yvan Roux <yvan.roux@linaro.org>
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* config/aarch64/aarch64.opt (mlra): New option.
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@ -1291,7 +1291,7 @@ msp430_expand_epilogue (int is_eh)
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if (cfun->machine->need_to_save [10])
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{
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/* Check for a helper function. */
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helper_n = 7; /* for when the loop below never sees a match. */
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helper_n = 7; /* For when the loop below never sees a match. */
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for (i = 9; i >= 4; i--)
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if (!cfun->machine->need_to_save [i])
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{
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@ -1354,7 +1354,7 @@ msp430_expand_epilogue (int is_eh)
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&& ! is_critical_func ()
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&& crtl->args.pretend_args_size == 0
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/* Calling the helper takes as many bytes as the POP;RET sequence. */
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&& helper_n != 1
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&& helper_n > 1
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&& !is_eh)
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{
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emit_insn (gen_epilogue_helper (GEN_INT (helper_n)));
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@ -1494,7 +1494,7 @@ msp430_expand_helper (rtx *operands, const char *helper_name, bool const_variant
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/* Note that the INTVAL is limited in value and length by the conditional above. */
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int len = strlen (helper_name) + 4;
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helper_const = (char *) xmalloc (len);
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snprintf (helper_const, len, "%s_%ld", helper_name, (int) INTVAL (operands[2]));
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snprintf (helper_const, len, "%s_%d", helper_name, (int) INTVAL (operands[2]));
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}
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emit_move_insn (gen_rtx_REG (arg1mode, 12),
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@ -1722,12 +1722,10 @@ msp430_output_labelref (FILE *file, const char *name)
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fputs (name, file);
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}
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#undef TARGET_PRINT_OPERAND
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#define TARGET_PRINT_OPERAND msp430_print_operand
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/* Common code for msp430_print_operand... */
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/* Common code for msp430_print_operand(). */
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static void
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msp430_print_operand_raw (FILE * file, rtx op, int letter ATTRIBUTE_UNUSED)
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msp430_print_operand_raw (FILE * file, rtx op)
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{
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int i;
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@ -1759,6 +1757,45 @@ msp430_print_operand_raw (FILE * file, rtx op, int letter ATTRIBUTE_UNUSED)
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}
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}
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#undef TARGET_PRINT_OPERAND_ADDRESS
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#define TARGET_PRINT_OPERAND_ADDRESS msp430_print_operand_addr
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/* Output to stdio stream FILE the assembler syntax for an
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instruction operand that is a memory reference whose address
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is ADDR. */
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static void
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msp430_print_operand_addr (FILE * file, rtx addr)
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{
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switch (GET_CODE (addr))
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{
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case PLUS:
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msp430_print_operand_raw (file, XEXP (addr, 1));
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gcc_assert (REG_P (XEXP (addr, 0)));
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fprintf (file, "(%s)", reg_names [REGNO (XEXP (addr, 0))]);
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return;
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case REG:
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fprintf (file, "@");
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break;
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case CONST:
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case CONST_INT:
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case SYMBOL_REF:
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case LABEL_REF:
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fprintf (file, "&");
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break;
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default:
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break;
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}
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msp430_print_operand_raw (file, addr);
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}
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#undef TARGET_PRINT_OPERAND
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#define TARGET_PRINT_OPERAND msp430_print_operand
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static void
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msp430_print_operand (FILE * file, rtx op, int letter)
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{
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@ -1803,7 +1840,7 @@ msp430_print_operand (FILE * file, rtx op, int letter)
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case GT: fprintf (file, "GE"); break;
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case LE: fprintf (file, "L"); break;
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default:
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msp430_print_operand_raw (file, op, letter);
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msp430_print_operand_raw (file, op);
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break;
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}
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return;
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@ -1815,7 +1852,7 @@ msp430_print_operand (FILE * file, rtx op, int letter)
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case GT: fprintf (file, "L"); break;
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case LE: fprintf (file, "GE"); break;
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default:
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msp430_print_operand_raw (file, op, letter);
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msp430_print_operand_raw (file, op);
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break;
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}
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return;
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@ -1897,38 +1934,18 @@ msp430_print_operand (FILE * file, rtx op, int letter)
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fprintf (file, "%d",
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msp430_initial_elimination_offset (ARG_POINTER_REGNUM, STACK_POINTER_REGNUM)
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- 2);
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return ;
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return;
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}
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switch (GET_CODE (op))
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{
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case REG:
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msp430_print_operand_raw (file, op, letter);
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msp430_print_operand_raw (file, op);
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break;
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case MEM:
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addr = XEXP (op, 0);
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switch (GET_CODE (addr))
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{
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case REG:
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fprintf (file, "@%s", reg_names [REGNO (addr)]);
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break;
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case PLUS:
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msp430_print_operand_raw (file, XEXP (addr, 1), letter);
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fprintf (file, "(%s)", reg_names [REGNO (XEXP (addr, 0))]);
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break;
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case CONST:
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case CONST_INT:
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case SYMBOL_REF:
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case LABEL_REF:
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fprintf (file, "&");
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msp430_print_operand_raw (file, addr, letter);
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break;
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default:
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print_rtl (file, addr);
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break;
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}
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msp430_print_operand_addr (file, addr);
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break;
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case CONST_INT:
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@ -1937,7 +1954,7 @@ msp430_print_operand (FILE * file, rtx op, int letter)
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case LABEL_REF:
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if (letter == 0)
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fprintf (file, "#");
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msp430_print_operand_raw (file, op, letter);
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msp430_print_operand_raw (file, op);
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break;
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case EQ: fprintf (file, "EQ"); break;
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@ -1951,7 +1968,6 @@ msp430_print_operand (FILE * file, rtx op, int letter)
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print_rtl (file, op);
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break;
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}
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}
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@ -190,8 +190,8 @@
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)
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(define_expand "movsi"
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[(set (match_operand:SI 0 "nonimmediate_operand" "")
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(match_operand:SI 1 "general_operand" ""))]
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[(set (match_operand:SI 0 "nonimmediate_operand")
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(match_operand:SI 1 "general_operand"))]
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""
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""
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)
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@ -230,7 +230,7 @@
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[(set (match_operand:PSI 0 "register_operand" "=r")
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(subreg:PSI (match_operand:SI 1 "register_operand" "r") 0))]
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"TARGET_LARGE"
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"PUSH.W %H1 { PUSH.W %1 { POPM.A #1, %0"
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"PUSH.W\t%H1 { PUSH.W %L1 { POPM.A #1, %0 ; Move reg-pair %L1:%H1 into pointer %0"
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)
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;;------------------------------------------------------------
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@ -326,8 +326,8 @@
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]
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""
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"@
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ADD %2, %1 ; cy
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ADD%X0 %2, %1 ; cy"
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ADD\t%2, %1 ; cy
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ADD%X0\t%2, %1 ; cy"
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)
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(define_insn "addhi3_cy_i"
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@ -341,8 +341,8 @@
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]
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""
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"@
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ADD %2, %1 ; cy
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ADD%X0 %2, %1 ; cy"
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ADD\t%2, %1 ; cy
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ADD%X0\t%2, %1 ; cy"
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)
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; Version of addhi that adds the carry, for SImode adds.
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@ -354,8 +354,8 @@
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]
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""
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"@
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ADDC %2, %1
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ADDC%X0 %2, %1"
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ADDC\t%2, %1
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ADDC%X0\t%2, %1"
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)
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; Split an SImode add into two HImode adds, keeping track of the carry
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@ -621,9 +621,30 @@
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stored in the stack slot will be the value *after* the
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stack pointer has been decremented. So allow for that
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here. */
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return \"PUSHM.A #1, %1 { ADDX.W #4, @r1 { POPX.W %0 { POPX.W %H0\";
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return \"PUSHM.A\t#1, %1 { ADDX.W #4, @r1 { POPX.W %L0 { POPX.W %H0 ; get stack pointer into %L0:%H0\";
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else
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return \"PUSHM.A #1, %1 { POPX.W %0 { POPX.W %H0\";
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return \"PUSHM.A\t#1, %1 { POPX.W %L0 { POPX.W %H0 ; move pointer in %1 into reg-pair %L0:%H0\";
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"
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)
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;; We also need to be able to sign-extend pointer types (eg ptrdiff_t).
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;; Since (we assume) pushing a 20-bit value onto the stack zero-extends
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;; it, we use a different method here.
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(define_insn "extendpsisi2"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(sign_extend:SI (match_operand:PSI 1 "register_operand" "r")))]
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"TARGET_LARGE"
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"*
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/* The intention here is that we copy the bottom 16-bits of
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%1 into %L0 (zeroing the top four bits). Then we copy the
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entire 20-bits of %1 into %H0 and then arithmetically shift
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it right by 16 bits, to get the top four bits of the pointer
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sign-extended in %H0. */
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if (REGNO (operands[0]) == REGNO (operands[1]))
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return \"MOVX.A\t%1, %H0 { MOV.W %1, %L0 { RPT #16 { RRAX.A %H0 ; sign extend pointer in %1 into %L0:%H0\";
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else
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return \"MOV.W \t%1, %L0 { MOVX.A %1, %H0 { RPT #16 { RRAX.A %H0 ; sign extend pointer in %1 into %L0:%H0\";
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"
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)
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@ -926,7 +947,7 @@
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(define_expand "call"
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[(call:HI (match_operand 0 "")
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(match_operand 1 ""))]
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(match_operand 1 ""))]
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""
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""
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)
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@ -966,7 +987,7 @@
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;; placeholder should get expanded into a regular-type epilogue that
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;; also does the EH return.
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(define_expand "eh_return"
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[(match_operand:HI 0 "" "")]
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[(match_operand:HI 0 "")]
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""
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"msp430_expand_eh_return (operands[0]);
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emit_jump_insn (gen_msp430_eh_epilogue ());
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@ -1272,3 +1293,19 @@
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""
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"BIS.W\t%0, %O0(SP)"
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)
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;; For some reason GCC is generating (set (reg) (and (neg (reg)) (int)))
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;; very late on in the compilation and not splitting it into separate
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;; instructions, so we provide a pattern to support it here.
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(define_insn "andneghi3"
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[(set (match_operand:HI 0 "register_operand" "=r")
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(and:HI (neg:HI (match_operand:HI 1 "register_operand" "r"))
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(match_operand 2 "immediate_operand" "n")))]
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""
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"*
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if (REGNO (operands[0]) != REGNO (operands[1]))
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return \"MOV.W\t%1, %0 { SUB.W #0, %0 { AND.W %2, %0\";
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else
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return \"SUB.W\t#0, %0 { AND.W %2, %0\";
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"
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)
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