constraints.md (Yv): New constraint.
* config/i386/constraints.md (Yv): New constraint. * config/i386/i386.h (VALID_AVX512VL_128_REG_MODE): Allow TFmode and V1TImode in xmm16+ registers for TARGET_AVX512VL. * config/i386/i386.md (avx512fvecmode): New mode attr. (*pushtf): Use v constraint instead of x. (*movtf_internal): Likewise. For TARGET_AVX512VL and xmm16+ registers, use vmovdqu64 or vmovdqa64 instructions. (*absneg<mode>2): Use Yv constraint instead of x constraint. (*absnegtf2_sse): Likewise. (copysign<mode>3_const, copysign<mode>3_var): Likewise. * config/i386/sse.md (*andnot<mode>3): Add avx512vl and avx512f alternatives. (*andnottf3, *<code><mode>3, *<code>tf3): Likewise. * gcc.target/i386/avx512dq-abs-copysign-1.c: New test. * gcc.target/i386/avx512vl-abs-copysign-1.c: New test. * gcc.target/i386/avx512vl-abs-copysign-2.c: New test. From-SVN: r236161
This commit is contained in:
Jakub Jelinek
Jakub Jelinek
parent
eb09cdcb1a
commit
40bd4bf95e
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@ -1,3 +1,19 @@
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2016-05-12 Jakub Jelinek <jakub@redhat.com>
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* config/i386/constraints.md (Yv): New constraint.
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* config/i386/i386.h (VALID_AVX512VL_128_REG_MODE): Allow
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TFmode and V1TImode in xmm16+ registers for TARGET_AVX512VL.
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* config/i386/i386.md (avx512fvecmode): New mode attr.
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(*pushtf): Use v constraint instead of x.
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(*movtf_internal): Likewise. For TARGET_AVX512VL and
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xmm16+ registers, use vmovdqu64 or vmovdqa64 instructions.
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(*absneg<mode>2): Use Yv constraint instead of x constraint.
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(*absnegtf2_sse): Likewise.
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(copysign<mode>3_const, copysign<mode>3_var): Likewise.
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* config/i386/sse.md (*andnot<mode>3): Add avx512vl and
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avx512f alternatives.
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(*andnottf3, *<code><mode>3, *<code>tf3): Likewise.
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2016-05-12 Richard Biener <rguenther@suse.de>
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PR tree-optimization/71060
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@ -145,6 +145,10 @@
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"TARGET_SSE ? (X86_TUNE_AVOID_4BYTE_PREFIXES ? NO_REX_SSE_REGS : ALL_SSE_REGS) : NO_REGS"
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"@internal Lower SSE register when avoiding REX prefix and all SSE registers otherwise.")
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(define_register_constraint "Yv"
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"TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS"
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"@internal For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), otherwise any SSE register.")
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;; We use the B prefix to denote any number of internal operands:
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;; f FLAGS_REG
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;; g GOT memory operand.
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@ -1126,7 +1126,8 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
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#define VALID_AVX512VL_128_REG_MODE(MODE) \
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((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \
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|| (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode)
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|| (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode \
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|| (MODE) == TFmode || (MODE) == V1TImode)
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#define VALID_SSE2_REG_MODE(MODE) \
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((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
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@ -1168,6 +1168,10 @@
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(define_mode_attr ssevecmodelower
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[(QI "v16qi") (HI "v8hi") (SI "v4si") (DI "v2di") (SF "v4sf") (DF "v2df")])
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;; AVX512F vector mode corresponding to a scalar mode
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(define_mode_attr avx512fvecmode
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[(QI "V64QI") (HI "V32HI") (SI "V16SI") (DI "V8DI") (SF "V16SF") (DF "V8DF")])
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;; Instruction suffix for REX 64bit operators.
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(define_mode_attr rex64suffix [(SI "") (DI "{q}")])
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@ -2928,7 +2932,7 @@
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(define_insn "*pushtf"
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[(set (match_operand:TF 0 "push_operand" "=<,<")
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(match_operand:TF 1 "general_no_elim_operand" "x,*roF"))]
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(match_operand:TF 1 "general_no_elim_operand" "v,*roF"))]
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"TARGET_64BIT || TARGET_SSE"
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{
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/* This insn should be already split before reg-stack. */
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@ -3103,8 +3107,8 @@
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"ix86_expand_move (<MODE>mode, operands); DONE;")
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(define_insn "*movtf_internal"
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[(set (match_operand:TF 0 "nonimmediate_operand" "=x,x ,m,?*r ,!o")
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(match_operand:TF 1 "general_operand" "C ,xm,x,*roF,*rC"))]
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[(set (match_operand:TF 0 "nonimmediate_operand" "=v,v ,m,?*r ,!o")
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(match_operand:TF 1 "general_operand" "C ,vm,v,*roF,*rC"))]
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"(TARGET_64BIT || TARGET_SSE)
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&& !(MEM_P (operands[0]) && MEM_P (operands[1]))
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&& (!can_create_pseudo_p ()
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@ -3129,6 +3133,10 @@
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{
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if (get_attr_mode (insn) == MODE_V4SF)
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return "%vmovups\t{%1, %0|%0, %1}";
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else if (TARGET_AVX512VL
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&& (EXT_REX_SSE_REG_P (operands[0])
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|| EXT_REX_SSE_REG_P (operands[1])))
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return "vmovdqu64\t{%1, %0|%0, %1}";
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else
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return "%vmovdqu\t{%1, %0|%0, %1}";
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}
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@ -3136,6 +3144,10 @@
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{
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if (get_attr_mode (insn) == MODE_V4SF)
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return "%vmovaps\t{%1, %0|%0, %1}";
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else if (TARGET_AVX512VL
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&& (EXT_REX_SSE_REG_P (operands[0])
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|| EXT_REX_SSE_REG_P (operands[1])))
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return "vmovdqa64\t{%1, %0|%0, %1}";
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else
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return "%vmovdqa\t{%1, %0|%0, %1}";
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}
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@ -9228,10 +9240,10 @@
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"ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
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(define_insn "*absneg<mode>2"
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[(set (match_operand:MODEF 0 "register_operand" "=x,x,f,!r")
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[(set (match_operand:MODEF 0 "register_operand" "=Yv,Yv,f,!r")
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(match_operator:MODEF 3 "absneg_operator"
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[(match_operand:MODEF 1 "register_operand" "0,x,0,0")]))
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(use (match_operand:<ssevecmode> 2 "nonimmediate_operand" "xm,0,X,X"))
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[(match_operand:MODEF 1 "register_operand" "0,Yv,0,0")]))
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(use (match_operand:<ssevecmode> 2 "nonimmediate_operand" "Yvm,0,X,X"))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
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"#"
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@ -9263,10 +9275,10 @@
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"ix86_expand_fp_absneg_operator (<CODE>, TFmode, operands); DONE;")
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(define_insn "*absnegtf2_sse"
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[(set (match_operand:TF 0 "register_operand" "=x,x")
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[(set (match_operand:TF 0 "register_operand" "=Yv,Yv")
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(match_operator:TF 3 "absneg_operator"
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[(match_operand:TF 1 "register_operand" "0,x")]))
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(use (match_operand:TF 2 "nonimmediate_operand" "xm,0"))
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[(match_operand:TF 1 "register_operand" "0,Yv")]))
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(use (match_operand:TF 2 "nonimmediate_operand" "Yvm,0"))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_SSE"
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"#")
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@ -9446,11 +9458,11 @@
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"ix86_expand_copysign (operands); DONE;")
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(define_insn_and_split "copysign<mode>3_const"
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[(set (match_operand:CSGNMODE 0 "register_operand" "=x")
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[(set (match_operand:CSGNMODE 0 "register_operand" "=Yv")
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(unspec:CSGNMODE
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[(match_operand:<CSGNVMODE> 1 "vector_move_operand" "xmC")
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[(match_operand:<CSGNVMODE> 1 "vector_move_operand" "YvmC")
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(match_operand:CSGNMODE 2 "register_operand" "0")
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(match_operand:<CSGNVMODE> 3 "nonimmediate_operand" "xm")]
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(match_operand:<CSGNVMODE> 3 "nonimmediate_operand" "Yvm")]
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UNSPEC_COPYSIGN))]
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"(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
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|| (TARGET_SSE && (<MODE>mode == TFmode))"
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@ -9460,14 +9472,16 @@
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"ix86_split_copysign_const (operands); DONE;")
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(define_insn "copysign<mode>3_var"
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[(set (match_operand:CSGNMODE 0 "register_operand" "=x,x,x,x,x")
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[(set (match_operand:CSGNMODE 0 "register_operand" "=Yv,Yv,Yv,Yv,Yv")
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(unspec:CSGNMODE
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[(match_operand:CSGNMODE 2 "register_operand" "x,0,0,x,x")
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(match_operand:CSGNMODE 3 "register_operand" "1,1,x,1,x")
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(match_operand:<CSGNVMODE> 4 "nonimmediate_operand" "X,xm,xm,0,0")
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(match_operand:<CSGNVMODE> 5 "nonimmediate_operand" "0,xm,1,xm,1")]
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[(match_operand:CSGNMODE 2 "register_operand" "Yv,0,0,Yv,Yv")
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(match_operand:CSGNMODE 3 "register_operand" "1,1,Yv,1,Yv")
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(match_operand:<CSGNVMODE> 4
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"nonimmediate_operand" "X,Yvm,Yvm,0,0")
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(match_operand:<CSGNVMODE> 5
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"nonimmediate_operand" "0,Yvm,1,Yvm,1")]
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UNSPEC_COPYSIGN))
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(clobber (match_scratch:<CSGNVMODE> 1 "=x,x,x,x,x"))]
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(clobber (match_scratch:<CSGNVMODE> 1 "=Yv,Yv,Yv,Yv,Yv"))]
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"(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
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|| (TARGET_SSE && (<MODE>mode == TFmode))"
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"#")
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@ -3020,11 +3020,11 @@
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;; because the native instructions read the full 128-bits.
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(define_insn "*andnot<mode>3"
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[(set (match_operand:MODEF 0 "register_operand" "=x,x")
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[(set (match_operand:MODEF 0 "register_operand" "=x,x,v,v")
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(and:MODEF
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(not:MODEF
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(match_operand:MODEF 1 "register_operand" "0,x"))
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(match_operand:MODEF 2 "register_operand" "x,x")))]
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(match_operand:MODEF 1 "register_operand" "0,x,v,v"))
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(match_operand:MODEF 2 "register_operand" "x,x,v,v")))]
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"SSE_FLOAT_MODE_P (<MODE>mode)"
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{
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static char buf[32];
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@ -3040,6 +3040,24 @@
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case 1:
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ops = "vandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
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break;
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case 2:
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if (TARGET_AVX512DQ)
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ops = "vandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
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else
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{
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suffix = <MODE>mode == DFmode ? "q" : "d";
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ops = "vpandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
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}
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break;
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case 3:
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if (TARGET_AVX512DQ)
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ops = "vandn%s\t{%%g2, %%g1, %%g0|%%g0, %%g1, %%g2}";
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else
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{
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suffix = <MODE>mode == DFmode ? "q" : "d";
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ops = "vpandn%s\t{%%g2, %%g1, %%g0|%%g0, %%g1, %%g2}";
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}
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break;
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default:
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gcc_unreachable ();
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}
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@ -3047,11 +3065,19 @@
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snprintf (buf, sizeof (buf), ops, suffix);
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return buf;
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}
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[(set_attr "isa" "noavx,avx")
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[(set_attr "isa" "noavx,avx,avx512vl,avx512f")
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(set_attr "type" "sselog")
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(set_attr "prefix" "orig,vex")
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(set_attr "prefix" "orig,vex,evex,evex")
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(set (attr "mode")
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(cond [(and (match_test "<MODE_SIZE> == 16")
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(cond [(eq_attr "alternative" "2")
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(if_then_else (match_test "TARGET_AVX512DQ")
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(const_string "<ssevecmode>")
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(const_string "TI"))
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(eq_attr "alternative" "3")
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(if_then_else (match_test "TARGET_AVX512DQ")
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(const_string "<avx512fvecmode>")
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(const_string "XI"))
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(and (match_test "<MODE_SIZE> == 16")
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(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL"))
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(const_string "V4SF")
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(match_test "TARGET_AVX")
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@ -3062,16 +3088,17 @@
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(const_string "<ssevecmode>")))])
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(define_insn "*andnottf3"
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[(set (match_operand:TF 0 "register_operand" "=x,x")
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[(set (match_operand:TF 0 "register_operand" "=x,x,v,v")
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(and:TF
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(not:TF (match_operand:TF 1 "register_operand" "0,x"))
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(match_operand:TF 2 "vector_operand" "xBm,xm")))]
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(not:TF (match_operand:TF 1 "register_operand" "0,x,v,v"))
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(match_operand:TF 2 "vector_operand" "xBm,xm,vm,v")))]
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"TARGET_SSE"
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{
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static char buf[32];
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const char *ops;
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const char *tmp
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= (get_attr_mode (insn) == MODE_V4SF) ? "andnps" : "pandn";
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= (which_alternative >= 2 ? "pandnq"
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: get_attr_mode (insn) == MODE_V4SF ? "andnps" : "pandn");
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switch (which_alternative)
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{
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@ -3079,8 +3106,12 @@
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ops = "%s\t{%%2, %%0|%%0, %%2}";
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break;
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case 1:
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case 2:
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ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
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break;
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case 3:
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ops = "v%s\t{%%g2, %%g1, %%g0|%%g0, %%g1, %%g2}";
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break;
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default:
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gcc_unreachable ();
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}
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@ -3088,7 +3119,7 @@
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snprintf (buf, sizeof (buf), ops, tmp);
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return buf;
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}
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[(set_attr "isa" "noavx,avx")
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[(set_attr "isa" "noavx,avx,avx512vl,avx512f")
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(set_attr "type" "sselog")
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(set (attr "prefix_data16")
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(if_then_else
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@ -3096,9 +3127,13 @@
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(eq_attr "mode" "TI"))
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(const_string "1")
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(const_string "*")))
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(set_attr "prefix" "orig,vex")
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(set_attr "prefix" "orig,vex,evex,evex")
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(set (attr "mode")
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(cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
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(cond [(eq_attr "alternative" "2")
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(const_string "TI")
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(eq_attr "alternative" "3")
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(const_string "XI")
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(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
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(const_string "V4SF")
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(match_test "TARGET_AVX")
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(const_string "TI")
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@ -3109,10 +3144,10 @@
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(const_string "TI")))])
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(define_insn "*<code><mode>3"
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[(set (match_operand:MODEF 0 "register_operand" "=x,x")
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[(set (match_operand:MODEF 0 "register_operand" "=x,x,v,v")
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(any_logic:MODEF
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(match_operand:MODEF 1 "register_operand" "%0,x")
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(match_operand:MODEF 2 "register_operand" "x,x")))]
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(match_operand:MODEF 1 "register_operand" "%0,x,v,v")
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(match_operand:MODEF 2 "register_operand" "x,x,v,v")))]
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"SSE_FLOAT_MODE_P (<MODE>mode)"
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{
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static char buf[32];
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@ -3125,9 +3160,26 @@
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case 0:
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ops = "<logic>%s\t{%%2, %%0|%%0, %%2}";
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break;
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case 2:
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if (!TARGET_AVX512DQ)
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{
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suffix = <MODE>mode == DFmode ? "q" : "d";
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ops = "vp<logic>%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
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break;
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}
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/* FALLTHRU */
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case 1:
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ops = "v<logic>%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
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break;
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case 3:
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if (TARGET_AVX512DQ)
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ops = "v<logic>%s\t{%%g2, %%g1, %%g0|%%g0, %%g1, %%g2}";
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else
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{
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suffix = <MODE>mode == DFmode ? "q" : "d";
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ops = "vp<logic>%s\t{%%g2, %%g1, %%g0|%%g0, %%g1, %%g2}";
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}
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break;
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default:
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gcc_unreachable ();
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}
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@ -3135,11 +3187,19 @@
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snprintf (buf, sizeof (buf), ops, suffix);
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return buf;
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}
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[(set_attr "isa" "noavx,avx")
|
||||
[(set_attr "isa" "noavx,avx,avx512vl,avx512f")
|
||||
(set_attr "type" "sselog")
|
||||
(set_attr "prefix" "orig,vex")
|
||||
(set_attr "prefix" "orig,vex,evex,evex")
|
||||
(set (attr "mode")
|
||||
(cond [(and (match_test "<MODE_SIZE> == 16")
|
||||
(cond [(eq_attr "alternative" "2")
|
||||
(if_then_else (match_test "TARGET_AVX512DQ")
|
||||
(const_string "<ssevecmode>")
|
||||
(const_string "TI"))
|
||||
(eq_attr "alternative" "3")
|
||||
(if_then_else (match_test "TARGET_AVX512DQ")
|
||||
(const_string "<avx512fvecmode>")
|
||||
(const_string "XI"))
|
||||
(and (match_test "<MODE_SIZE> == 16")
|
||||
(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL"))
|
||||
(const_string "V4SF")
|
||||
(match_test "TARGET_AVX")
|
||||
|
|
@ -3158,17 +3218,18 @@
|
|||
"ix86_fixup_binary_operands_no_copy (<CODE>, TFmode, operands);")
|
||||
|
||||
(define_insn "*<code>tf3"
|
||||
[(set (match_operand:TF 0 "register_operand" "=x,x")
|
||||
[(set (match_operand:TF 0 "register_operand" "=x,x,v,v")
|
||||
(any_logic:TF
|
||||
(match_operand:TF 1 "vector_operand" "%0,x")
|
||||
(match_operand:TF 2 "vector_operand" "xBm,xm")))]
|
||||
(match_operand:TF 1 "vector_operand" "%0,x,v,v")
|
||||
(match_operand:TF 2 "vector_operand" "xBm,xm,vm,v")))]
|
||||
"TARGET_SSE
|
||||
&& ix86_binary_operator_ok (<CODE>, TFmode, operands)"
|
||||
{
|
||||
static char buf[32];
|
||||
const char *ops;
|
||||
const char *tmp
|
||||
= (get_attr_mode (insn) == MODE_V4SF) ? "<logic>ps" : "p<logic>";
|
||||
= (which_alternative >= 2 ? "p<logic>q"
|
||||
: get_attr_mode (insn) == MODE_V4SF ? "<logic>ps" : "p<logic>");
|
||||
|
||||
switch (which_alternative)
|
||||
{
|
||||
|
|
@ -3176,8 +3237,12 @@
|
|||
ops = "%s\t{%%2, %%0|%%0, %%2}";
|
||||
break;
|
||||
case 1:
|
||||
case 2:
|
||||
ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
|
||||
break;
|
||||
case 3:
|
||||
ops = "v%s\t{%%g2, %%g1, %%g0|%%g0, %%g1, %%g2}";
|
||||
break;
|
||||
default:
|
||||
gcc_unreachable ();
|
||||
}
|
||||
|
|
@ -3185,7 +3250,7 @@
|
|||
snprintf (buf, sizeof (buf), ops, tmp);
|
||||
return buf;
|
||||
}
|
||||
[(set_attr "isa" "noavx,avx")
|
||||
[(set_attr "isa" "noavx,avx,avx512vl,avx512f")
|
||||
(set_attr "type" "sselog")
|
||||
(set (attr "prefix_data16")
|
||||
(if_then_else
|
||||
|
|
@ -3193,9 +3258,13 @@
|
|||
(eq_attr "mode" "TI"))
|
||||
(const_string "1")
|
||||
(const_string "*")))
|
||||
(set_attr "prefix" "orig,vex")
|
||||
(set_attr "prefix" "orig,vex,evex,evex")
|
||||
(set (attr "mode")
|
||||
(cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
|
||||
(cond [(eq_attr "alternative" "2")
|
||||
(const_string "TI")
|
||||
(eq_attr "alternative" "3")
|
||||
(const_string "QI")
|
||||
(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
|
||||
(const_string "V4SF")
|
||||
(match_test "TARGET_AVX")
|
||||
(const_string "TI")
|
||||
|
|
|
|||
|
|
@ -1,3 +1,9 @@
|
|||
2016-05-12 Jakub Jelinek <jakub@redhat.com>
|
||||
|
||||
* gcc.target/i386/avx512dq-abs-copysign-1.c: New test.
|
||||
* gcc.target/i386/avx512vl-abs-copysign-1.c: New test.
|
||||
* gcc.target/i386/avx512vl-abs-copysign-2.c: New test.
|
||||
|
||||
2016-05-12 Richard Biener <rguenther@suse.de>
|
||||
|
||||
PR tree-optimization/70986
|
||||
|
|
|
|||
|
|
@ -0,0 +1,71 @@
|
|||
/* { dg-do compile { target { ! ia32 } } } */
|
||||
/* { dg-options "-Ofast -mavx512vl -mavx512dq" } */
|
||||
|
||||
void
|
||||
f1 (float x)
|
||||
{
|
||||
register float a __asm ("xmm16");
|
||||
a = x;
|
||||
asm volatile ("" : "+v" (a));
|
||||
a = __builtin_fabsf (a);
|
||||
asm volatile ("" : "+v" (a));
|
||||
}
|
||||
|
||||
void
|
||||
f2 (float x, float y)
|
||||
{
|
||||
register float a __asm ("xmm16"), b __asm ("xmm17");
|
||||
a = x;
|
||||
b = y;
|
||||
asm volatile ("" : "+v" (a), "+v" (b));
|
||||
a = __builtin_copysignf (a, b);
|
||||
asm volatile ("" : "+v" (a));
|
||||
}
|
||||
|
||||
void
|
||||
f3 (float x)
|
||||
{
|
||||
register float a __asm ("xmm16");
|
||||
a = x;
|
||||
asm volatile ("" : "+v" (a));
|
||||
a = -a;
|
||||
asm volatile ("" : "+v" (a));
|
||||
}
|
||||
|
||||
void
|
||||
f4 (double x)
|
||||
{
|
||||
register double a __asm ("xmm18");
|
||||
a = x;
|
||||
asm volatile ("" : "+v" (a));
|
||||
a = __builtin_fabs (a);
|
||||
asm volatile ("" : "+v" (a));
|
||||
}
|
||||
|
||||
void
|
||||
f5 (double x, double y)
|
||||
{
|
||||
register double a __asm ("xmm18"), b __asm ("xmm19");
|
||||
a = x;
|
||||
b = y;
|
||||
asm volatile ("" : "+v" (a), "+v" (b));
|
||||
a = __builtin_copysign (a, b);
|
||||
asm volatile ("" : "+v" (a));
|
||||
}
|
||||
|
||||
void
|
||||
f6 (double x)
|
||||
{
|
||||
register double a __asm ("xmm18");
|
||||
a = x;
|
||||
asm volatile ("" : "+v" (a));
|
||||
a = -a;
|
||||
asm volatile ("" : "+v" (a));
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vandps\[^\n\r\]*xmm16" } } */
|
||||
/* { dg-final { scan-assembler "vorps\[^\n\r\]*xmm16" } } */
|
||||
/* { dg-final { scan-assembler "vxorps\[^\n\r\]*xmm16" } } */
|
||||
/* { dg-final { scan-assembler "vandpd\[^\n\r\]*xmm18" } } */
|
||||
/* { dg-final { scan-assembler "vorpd\[^\n\r\]*xmm18" } } */
|
||||
/* { dg-final { scan-assembler "vxorpd\[^\n\r\]*xmm18" } } */
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
/* { dg-do compile { target { ! ia32 } } } */
|
||||
/* { dg-options "-Ofast -mavx512vl -mno-avx512dq" } */
|
||||
|
||||
void
|
||||
f1 (float x)
|
||||
{
|
||||
register float a __asm ("xmm16");
|
||||
a = x;
|
||||
asm volatile ("" : "+v" (a));
|
||||
a = __builtin_fabsf (a);
|
||||
asm volatile ("" : "+v" (a));
|
||||
}
|
||||
|
||||
void
|
||||
f2 (float x, float y)
|
||||
{
|
||||
register float a __asm ("xmm16"), b __asm ("xmm17");
|
||||
a = x;
|
||||
b = y;
|
||||
asm volatile ("" : "+v" (a), "+v" (b));
|
||||
a = __builtin_copysignf (a, b);
|
||||
asm volatile ("" : "+v" (a));
|
||||
}
|
||||
|
||||
void
|
||||
f3 (float x)
|
||||
{
|
||||
register float a __asm ("xmm16");
|
||||
a = x;
|
||||
asm volatile ("" : "+v" (a));
|
||||
a = -a;
|
||||
asm volatile ("" : "+v" (a));
|
||||
}
|
||||
|
||||
void
|
||||
f4 (double x)
|
||||
{
|
||||
register double a __asm ("xmm18");
|
||||
a = x;
|
||||
asm volatile ("" : "+v" (a));
|
||||
a = __builtin_fabs (a);
|
||||
asm volatile ("" : "+v" (a));
|
||||
}
|
||||
|
||||
void
|
||||
f5 (double x, double y)
|
||||
{
|
||||
register double a __asm ("xmm18"), b __asm ("xmm19");
|
||||
a = x;
|
||||
b = y;
|
||||
asm volatile ("" : "+v" (a), "+v" (b));
|
||||
a = __builtin_copysign (a, b);
|
||||
asm volatile ("" : "+v" (a));
|
||||
}
|
||||
|
||||
void
|
||||
f6 (double x)
|
||||
{
|
||||
register double a __asm ("xmm18");
|
||||
a = x;
|
||||
asm volatile ("" : "+v" (a));
|
||||
a = -a;
|
||||
asm volatile ("" : "+v" (a));
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vpandd\[^\n\r\]*xmm16" } } */
|
||||
/* { dg-final { scan-assembler "vpord\[^\n\r\]*xmm16" } } */
|
||||
/* { dg-final { scan-assembler "vpxord\[^\n\r\]*xmm16" } } */
|
||||
/* { dg-final { scan-assembler "vpandq\[^\n\r\]*xmm18" } } */
|
||||
/* { dg-final { scan-assembler "vporq\[^\n\r\]*xmm18" } } */
|
||||
/* { dg-final { scan-assembler "vpxorq\[^\n\r\]*xmm18" } } */
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/* { dg-do compile { target { ! ia32 } } } */
|
||||
/* { dg-options "-Ofast -mavx512vl" } */
|
||||
|
||||
void
|
||||
f1 (__float128 x)
|
||||
{
|
||||
register __float128 a __asm ("xmm16");
|
||||
a = x;
|
||||
asm volatile ("" : "+v" (a));
|
||||
a = __builtin_fabsq (a);
|
||||
asm volatile ("" : "+v" (a));
|
||||
}
|
||||
|
||||
void
|
||||
f2 (__float128 x, __float128 y)
|
||||
{
|
||||
register __float128 a __asm ("xmm16"), b __asm ("xmm17");
|
||||
a = x;
|
||||
b = y;
|
||||
asm volatile ("" : "+v" (a), "+v" (b));
|
||||
a = __builtin_copysignq (a, b);
|
||||
asm volatile ("" : "+v" (a));
|
||||
}
|
||||
|
||||
void
|
||||
f3 (__float128 x)
|
||||
{
|
||||
register __float128 a __asm ("xmm16");
|
||||
a = x;
|
||||
asm volatile ("" : "+v" (a));
|
||||
a = -a;
|
||||
asm volatile ("" : "+v" (a));
|
||||
}
|
||||
|
||||
__int128_t
|
||||
f4 (void)
|
||||
{
|
||||
register __int128_t a __asm ("xmm16");
|
||||
register __int128_t __attribute__((vector_size (16))) b __asm ("xmm17");
|
||||
a = 1;
|
||||
asm volatile ("" : "+v" (a));
|
||||
b[0] = a;
|
||||
asm volatile ("" : "+v" (b));
|
||||
return b[0];
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vpandq\[^\n\r\]*xmm16" } } */
|
||||
/* { dg-final { scan-assembler "vporq\[^\n\r\]*xmm16" } } */
|
||||
/* { dg-final { scan-assembler "vpxorq\[^\n\r\]*xmm16" } } */
|
||||
Loading…
Reference in New Issue