[ARC] Automatic context save/restore for regular interrupts.
The AUX_IRQ_CTRL register controls the behavior of automated register save and restore or prologue and epilogue sequences during a non-fast interrupt entry and exit, and context save and restore instructions. A user passes to the compiler the configuration of the AUX_IRQ_CTRL register via mirq-ctrl-saved option. This option, specifies gneral-purposes registers that the processor saves/restores on interrupt entry and exit, and it is only valid for ARC EM and ARC HS cores. gcc/ 2017-05-09 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.c (irq_ctrl_saved): New variable. (ARC_AUTOBLINK_IRQ_P): Define. (ARC_AUTOFP_IRQ_P): Likewise. (ARC_AUTO_IRQ_P): Likewise. (irq_range): New function. (arc_must_save_register): Likewise. (arc_must_save_return_addr): Likewise. (arc_dwarf_emit_irq_save_regs): Likewise. (arc_override_options): Handle deferred options. (MUST_SAVE_REGISTER): Deleted, replaced by arc_must_save_register. (MUST_SAVE_RETURN_ADDR): Deleted, replaced by arc_must_save_return_addr. (arc_compute_frame_size): Handle automated save and restore of registers. (arc_expand_prologue): Likewise. (arc_expand_epilogue): Likewise. * config/arc/arc.md (stack_irq_dwarf): New unspec instruction. * config/arc/arc.opt (mirq-ctrl-saved): New option. * doc/invoke.texi (mirq-ctrl-saved): Document option. testsuite/ 2017-05-09 Claudiu Zissulescu <claziss@synopsys.com> * gcc.target/arc/interrupt-5.c: Newfile. * gcc.target/arc/interrupt-6.c: Likewise. * gcc.target/arc/interrupt-7.c: Likewise. * gcc.target/arc/interrupt-8.c: Likewise. * gcc.target/arc/interrupt-9.c: Likewise. From-SVN: r247795
This commit is contained in:
Claudiu Zissulescu
Claudiu Zissulescu
parent
019bd543a9
commit
4145318390
22
ChangeLog
22
ChangeLog
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@ -1,3 +1,25 @@
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2017-05-09 Claudiu Zissulescu <claziss@synopsys.com>
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* config/arc/arc.c (irq_ctrl_saved): New variable.
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(ARC_AUTOBLINK_IRQ_P): Define.
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(ARC_AUTOFP_IRQ_P): Likewise.
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(ARC_AUTO_IRQ_P): Likewise.
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(irq_range): New function.
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(arc_must_save_register): Likewise.
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(arc_must_save_return_addr): Likewise.
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(arc_dwarf_emit_irq_save_regs): Likewise.
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(arc_override_options): Handle deferred options.
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(MUST_SAVE_REGISTER): Deleted, replaced by arc_must_save_register.
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(MUST_SAVE_RETURN_ADDR): Deleted, replaced by
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arc_must_save_return_addr.
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(arc_compute_frame_size): Handle automated save and restore of
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registers.
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(arc_expand_prologue): Likewise.
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(arc_expand_epilogue): Likewise.
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* config/arc/arc.md (stack_irq_dwarf): New unspec instruction.
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* config/arc/arc.opt (mirq-ctrl-saved): New option.
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* doc/invoke.texi (mirq-ctrl-saved): Document option.
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2017-04-19 Thomas Koenig <tkoenig@gcc.gnu.org>
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Tobias Burnus <tobias.burnus@physik.fu-berlin.de>
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@ -63,6 +63,7 @@ along with GCC; see the file COPYING3. If not see
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#include "builtins.h"
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#include "rtl-iter.h"
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#include "alias.h"
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#include "opts.h"
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/* Which cpu we're compiling for (ARC600, ARC601, ARC700). */
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static char arc_cpu_name[10] = "";
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@ -111,6 +112,29 @@ struct GTY (()) arc_ccfsm
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int target_label;
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};
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/* Status of the IRQ_CTRL_AUX register. */
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typedef struct irq_ctrl_saved_t
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{
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/* Last register number used by IRQ_CTRL_SAVED aux_reg. */
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short irq_save_last_reg;
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/* True if BLINK is automatically saved. */
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bool irq_save_blink;
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/* True if LPCOUNT is automatically saved. */
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bool irq_save_lpcount;
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} irq_ctrl_saved_t;
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static irq_ctrl_saved_t irq_ctrl_saved;
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#define ARC_AUTOBLINK_IRQ_P(FNTYPE) \
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(ARC_INTERRUPT_P (FNTYPE) && irq_ctrl_saved.irq_save_blink)
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#define ARC_AUTOFP_IRQ_P(FNTYPE) \
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(ARC_INTERRUPT_P (FNTYPE) && (irq_ctrl_saved.irq_save_last_reg > 26))
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#define ARC_AUTO_IRQ_P(FNTYPE) \
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(ARC_INTERRUPT_P (FNTYPE) \
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&& (irq_ctrl_saved.irq_save_blink \
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|| (irq_ctrl_saved.irq_save_last_reg >= 0)))
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#define arc_ccfsm_current cfun->machine->ccfsm_current
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#define ARC_CCFSM_BRANCH_DELETED_P(STATE) \
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@ -806,11 +830,110 @@ arc_init (void)
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}
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}
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/* Parse -mirq-ctrl-saved=RegisterRange, blink, lp_copunt. The
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register range is specified as two registers separated by a dash.
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It always starts with r0, and its upper limit is fp register.
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blink and lp_count registers are optional. */
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static void
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irq_range (const char *cstr)
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{
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int i, first, last, blink, lpcount, xreg;
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char *str, *dash, *comma;
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i = strlen (cstr);
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str = (char *) alloca (i + 1);
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memcpy (str, cstr, i + 1);
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blink = -1;
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lpcount = -1;
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dash = strchr (str, '-');
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if (!dash)
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{
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warning (0, "value of -mirq-ctrl-saved must have form R0-REGx");
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return;
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}
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*dash = '\0';
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comma = strchr (dash + 1, ',');
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if (comma)
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*comma = '\0';
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first = decode_reg_name (str);
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if (first != 0)
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{
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warning (0, "first register must be R0");
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return;
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}
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/* At this moment we do not have the register names initialized
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accordingly. */
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if (!strcmp (dash + 1, "ilink"))
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last = 29;
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else
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last = decode_reg_name (dash + 1);
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if (last < 0)
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{
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warning (0, "unknown register name: %s", dash + 1);
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return;
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}
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if (!(last & 0x01))
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{
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warning (0, "last register name %s must be an odd register", dash + 1);
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return;
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}
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*dash = '-';
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if (first > last)
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{
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warning (0, "%s-%s is an empty range", str, dash + 1);
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return;
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}
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while (comma)
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{
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*comma = ',';
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str = comma + 1;
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comma = strchr (str, ',');
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if (comma)
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*comma = '\0';
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xreg = decode_reg_name (str);
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switch (xreg)
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{
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case 31:
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blink = 31;
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break;
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case 60:
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lpcount = 60;
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break;
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default:
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warning (0, "unknown register name: %s", str);
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return;
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}
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}
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irq_ctrl_saved.irq_save_last_reg = last;
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irq_ctrl_saved.irq_save_blink = (blink == 31) || (last == 31);
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irq_ctrl_saved.irq_save_lpcount = (lpcount == 60);
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}
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/* Check ARC options, generate derived target attributes. */
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static void
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arc_override_options (void)
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{
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unsigned int i;
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cl_deferred_option *opt;
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vec<cl_deferred_option> *vopt
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= (vec<cl_deferred_option> *) arc_deferred_options;
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if (arc_cpu == PROCESSOR_NONE)
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arc_cpu = TARGET_CPU_DEFAULT;
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@ -839,6 +962,28 @@ arc_override_options (void)
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gcc_unreachable ();
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}
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irq_ctrl_saved.irq_save_last_reg = -1;
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irq_ctrl_saved.irq_save_blink = false;
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irq_ctrl_saved.irq_save_lpcount = false;
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/* Handle the deferred options. */
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if (vopt)
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FOR_EACH_VEC_ELT (*vopt, i, opt)
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{
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switch (opt->opt_index)
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{
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case OPT_mirq_ctrl_saved_:
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if (TARGET_V2)
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irq_range (opt->arg);
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else
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warning (0, "option -mirq-ctrl-saved valid only for ARC v2 processors");
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break;
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default:
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gcc_unreachable();
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}
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}
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/* Set cpu flags accordingly to architecture/selected cpu. The cpu
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specific flags are set in arc-common.c. The architecture forces
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the default hardware configurations in, regardless what command
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@ -2235,14 +2380,52 @@ arc_compute_function_type (struct function *fun)
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FIXME: This will not be needed if we used some arbitrary register
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instead of r26.
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*/
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#define MUST_SAVE_REGISTER(regno, interrupt_p) \
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(((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
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&& (df_regs_ever_live_p (regno) && (!call_used_regs[regno] || interrupt_p))) \
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|| (flag_pic && crtl->uses_pic_offset_table \
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&& regno == PIC_OFFSET_TABLE_REGNUM) )
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#define MUST_SAVE_RETURN_ADDR \
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(cfun->machine->frame_info.save_return_addr)
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static bool
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arc_must_save_register (int regno, struct function *func)
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{
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enum arc_function_type fn_type = arc_compute_function_type (func);
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bool irq_auto_save_p = ((irq_ctrl_saved.irq_save_last_reg >= regno)
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&& ARC_INTERRUPT_P (fn_type));
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if ((regno) != RETURN_ADDR_REGNUM
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&& (regno) != FRAME_POINTER_REGNUM
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&& df_regs_ever_live_p (regno)
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&& (!call_used_regs[regno]
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|| ARC_INTERRUPT_P (fn_type))
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/* Do not emit code for auto saved regs. */
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&& !irq_auto_save_p)
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return true;
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if (flag_pic && crtl->uses_pic_offset_table
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&& regno == PIC_OFFSET_TABLE_REGNUM)
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return true;
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return false;
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}
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/* Return true if the return address must be saved in the current function,
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otherwise return false. */
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static bool
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arc_must_save_return_addr (struct function *func)
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{
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if (func->machine->frame_info.save_return_addr)
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return true;
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return false;
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}
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/* Helper function to wrap FRAME_POINTER_NEEDED. We do this as
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FRAME_POINTER_NEEDED will not be true until the IRA (Integrated
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Register Allocator) pass, while we want to get the frame size
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correct earlier than the IRA pass. */
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static bool
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arc_frame_pointer_needed (void)
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{
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return (frame_pointer_needed);
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}
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/* Return non-zero if there are registers to be saved or loaded using
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millicode thunks. We can only use consecutive sequences starting
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@ -2286,8 +2469,6 @@ arc_compute_frame_size (int size) /* size = # of var. bytes allocated. */
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unsigned int total_size, var_size, args_size, pretend_size, extra_size;
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unsigned int reg_size, reg_offset;
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unsigned int gmask;
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enum arc_function_type fn_type;
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int interrupt_p;
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struct arc_frame_info *frame_info = &cfun->machine->frame_info;
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size = ARC_STACK_ALIGN (size);
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@ -2306,15 +2487,13 @@ arc_compute_frame_size (int size) /* size = # of var. bytes allocated. */
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reg_size = 0;
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gmask = 0;
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fn_type = arc_compute_function_type (cfun);
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interrupt_p = ARC_INTERRUPT_P (fn_type);
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for (regno = 0; regno <= 31; regno++)
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{
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if (MUST_SAVE_REGISTER (regno, interrupt_p))
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if (arc_must_save_register (regno, cfun))
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{
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reg_size += UNITS_PER_WORD;
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gmask |= 1 << regno;
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gmask |= 1L << regno;
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}
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}
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@ -2330,9 +2509,9 @@ arc_compute_frame_size (int size) /* size = # of var. bytes allocated. */
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}
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extra_size = 0;
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if (MUST_SAVE_RETURN_ADDR)
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if (arc_must_save_return_addr (cfun))
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extra_size = 4;
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if (frame_pointer_needed)
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if (arc_frame_pointer_needed ())
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extra_size += 4;
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/* 5) Space for variable arguments passed in registers */
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@ -2357,7 +2536,7 @@ arc_compute_frame_size (int size) /* size = # of var. bytes allocated. */
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Frame: pretend_size <blink> reg_size <fp> var_size args_size <--sp
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*/
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reg_offset = (total_size - (pretend_size + reg_size + extra_size)
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+ (frame_pointer_needed ? 4 : 0));
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+ (arc_frame_pointer_needed () ? 4 : 0));
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/* Save computed information. */
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frame_info->total_size = total_size;
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@ -2548,6 +2727,77 @@ arc_save_restore (rtx base_reg,
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int arc_return_address_regs[4]
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= {0, RETURN_ADDR_REGNUM, ILINK1_REGNUM, ILINK2_REGNUM};
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/* Build dwarf information when the context is saved via AUX_IRQ_CTRL
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mechanism. */
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static void
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arc_dwarf_emit_irq_save_regs (void)
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{
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rtx tmp, par, insn, reg;
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int i, offset, j;
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par = gen_rtx_SEQUENCE (VOIDmode,
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rtvec_alloc (irq_ctrl_saved.irq_save_last_reg + 1
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+ irq_ctrl_saved.irq_save_blink
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+ irq_ctrl_saved.irq_save_lpcount
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+ 1));
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/* Build the stack adjustment note for unwind info. */
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j = 0;
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offset = UNITS_PER_WORD * (irq_ctrl_saved.irq_save_last_reg + 1
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+ irq_ctrl_saved.irq_save_blink
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+ irq_ctrl_saved.irq_save_lpcount);
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tmp = plus_constant (Pmode, stack_pointer_rtx, -1 * offset);
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tmp = gen_rtx_SET (stack_pointer_rtx, tmp);
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RTX_FRAME_RELATED_P (tmp) = 1;
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XVECEXP (par, 0, j++) = tmp;
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offset -= UNITS_PER_WORD;
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/* 1st goes LP_COUNT. */
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if (irq_ctrl_saved.irq_save_lpcount)
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{
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reg = gen_rtx_REG (SImode, 60);
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tmp = plus_constant (Pmode, stack_pointer_rtx, offset);
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tmp = gen_frame_mem (SImode, tmp);
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tmp = gen_rtx_SET (tmp, reg);
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RTX_FRAME_RELATED_P (tmp) = 1;
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XVECEXP (par, 0, j++) = tmp;
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offset -= UNITS_PER_WORD;
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}
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/* 2nd goes BLINK. */
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if (irq_ctrl_saved.irq_save_blink)
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{
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reg = gen_rtx_REG (SImode, 31);
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tmp = plus_constant (Pmode, stack_pointer_rtx, offset);
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tmp = gen_frame_mem (SImode, tmp);
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tmp = gen_rtx_SET (tmp, reg);
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RTX_FRAME_RELATED_P (tmp) = 1;
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XVECEXP (par, 0, j++) = tmp;
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offset -= UNITS_PER_WORD;
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}
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/* Build the parallel of the remaining registers recorded as saved
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for unwind. */
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for (i = irq_ctrl_saved.irq_save_last_reg; i >= 0; i--)
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{
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reg = gen_rtx_REG (SImode, i);
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tmp = plus_constant (Pmode, stack_pointer_rtx, offset);
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tmp = gen_frame_mem (SImode, tmp);
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tmp = gen_rtx_SET (tmp, reg);
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RTX_FRAME_RELATED_P (tmp) = 1;
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XVECEXP (par, 0, j++) = tmp;
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offset -= UNITS_PER_WORD;
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}
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/* Dummy insn used to anchor the dwarf info. */
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insn = emit_insn (gen_stack_irq_dwarf());
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add_reg_note (insn, REG_FRAME_RELATED_EXPR, par);
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RTX_FRAME_RELATED_P (insn) = 1;
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}
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/* Set up the stack and frame pointer (if desired) for the function. */
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void
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@ -2561,6 +2811,7 @@ arc_expand_prologue (void)
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Change the stack layout so that we rather store a high register with the
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PRE_MODIFY, thus enabling more short insn generation.) */
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int first_offset = 0;
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enum arc_function_type fn_type = arc_compute_function_type (cfun);
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size = ARC_STACK_ALIGN (size);
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@ -2588,16 +2839,25 @@ arc_expand_prologue (void)
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frame_size_to_allocate -= cfun->machine->frame_info.pretend_size;
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}
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/* IRQ using automatic save mechanism will save the register before
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anything we do. */
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if (ARC_AUTO_IRQ_P (fn_type))
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{
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arc_dwarf_emit_irq_save_regs ();
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}
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/* The home-grown ABI says link register is saved first. */
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if (MUST_SAVE_RETURN_ADDR)
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if (arc_must_save_return_addr (cfun)
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&& !ARC_AUTOBLINK_IRQ_P (fn_type))
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{
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rtx ra = gen_rtx_REG (SImode, RETURN_ADDR_REGNUM);
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rtx mem = gen_frame_mem (Pmode, gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
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rtx mem = gen_frame_mem (Pmode,
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gen_rtx_PRE_DEC (Pmode,
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stack_pointer_rtx));
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frame_move_inc (mem, ra, stack_pointer_rtx, 0);
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frame_size_to_allocate -= UNITS_PER_WORD;
|
||||
|
||||
} /* MUST_SAVE_RETURN_ADDR */
|
||||
}
|
||||
|
||||
/* Save any needed call-saved regs (and call-used if this is an
|
||||
interrupt handler) for ARCompact ISA. */
|
||||
|
|
@ -2609,9 +2869,10 @@ arc_expand_prologue (void)
|
|||
frame_size_to_allocate -= cfun->machine->frame_info.reg_size;
|
||||
}
|
||||
|
||||
|
||||
/* Save frame pointer if needed. */
|
||||
if (frame_pointer_needed)
|
||||
/* Save frame pointer if needed. First save the FP on stack, if not
|
||||
autosaved. */
|
||||
if (arc_frame_pointer_needed ()
|
||||
&& !ARC_AUTOFP_IRQ_P (fn_type))
|
||||
{
|
||||
rtx addr = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
|
||||
GEN_INT (-UNITS_PER_WORD + first_offset));
|
||||
|
|
@ -2621,6 +2882,11 @@ arc_expand_prologue (void)
|
|||
frame_move_inc (mem, frame_pointer_rtx, stack_pointer_rtx, 0);
|
||||
frame_size_to_allocate -= UNITS_PER_WORD;
|
||||
first_offset = 0;
|
||||
}
|
||||
|
||||
/* Emit mov fp,sp. */
|
||||
if (arc_frame_pointer_needed ())
|
||||
{
|
||||
frame_move (frame_pointer_rtx, stack_pointer_rtx);
|
||||
}
|
||||
|
||||
|
|
@ -2675,13 +2941,13 @@ arc_expand_epilogue (int sibcall_p)
|
|||
sp, but don't restore sp if we don't have to. */
|
||||
|
||||
if (!can_trust_sp_p)
|
||||
gcc_assert (frame_pointer_needed);
|
||||
gcc_assert (arc_frame_pointer_needed ());
|
||||
|
||||
/* Restore stack pointer to the beginning of saved register area for
|
||||
ARCompact ISA. */
|
||||
if (frame_size)
|
||||
{
|
||||
if (frame_pointer_needed)
|
||||
if (arc_frame_pointer_needed ())
|
||||
frame_move (stack_pointer_rtx, frame_pointer_rtx);
|
||||
else
|
||||
first_offset = frame_size;
|
||||
|
|
@ -2692,7 +2958,8 @@ arc_expand_epilogue (int sibcall_p)
|
|||
|
||||
|
||||
/* Restore any saved registers. */
|
||||
if (frame_pointer_needed)
|
||||
if (arc_frame_pointer_needed ()
|
||||
&& !ARC_AUTOFP_IRQ_P (fn_type))
|
||||
{
|
||||
rtx addr = gen_rtx_POST_INC (Pmode, stack_pointer_rtx);
|
||||
|
||||
|
|
@ -2730,14 +2997,15 @@ arc_expand_epilogue (int sibcall_p)
|
|||
: satisfies_constraint_C2a (GEN_INT (first_offset))))
|
||||
/* Also do this if we have both gprs and return
|
||||
address to restore, and they both would need a LIMM. */
|
||||
|| (MUST_SAVE_RETURN_ADDR
|
||||
&& !SMALL_INT ((cfun->machine->frame_info.reg_size + first_offset) >> 2)
|
||||
&& cfun->machine->frame_info.gmask))
|
||||
|| (arc_must_save_return_addr (cfun)
|
||||
&& !SMALL_INT ((cfun->machine->frame_info.reg_size + first_offset) >> 2)
|
||||
&& cfun->machine->frame_info.gmask))
|
||||
{
|
||||
frame_stack_add (first_offset);
|
||||
first_offset = 0;
|
||||
}
|
||||
if (MUST_SAVE_RETURN_ADDR)
|
||||
if (arc_must_save_return_addr (cfun)
|
||||
&& !ARC_AUTOBLINK_IRQ_P (fn_type))
|
||||
{
|
||||
rtx ra = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
|
||||
int ra_offs = cfun->machine->frame_info.reg_size + first_offset;
|
||||
|
|
@ -2802,7 +3070,6 @@ arc_expand_epilogue (int sibcall_p)
|
|||
& ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), 1, &first_offset);
|
||||
}
|
||||
|
||||
|
||||
/* The rest of this function does the following:
|
||||
ARCompact : handle epilogue_delay, restore sp (phase-2), return
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -6241,6 +6241,14 @@
|
|||
[(set (zero_extract:SI (match_dup 3) (match_dup 1) (match_dup 2))
|
||||
(zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2)))])
|
||||
|
||||
;; Dummy pattern used as a place holder for automatically saved
|
||||
;; registers.
|
||||
(define_insn "stack_irq_dwarf"
|
||||
[(unspec_volatile [(const_int 1)] VUNSPEC_ARC_STACK_IRQ)]
|
||||
""
|
||||
""
|
||||
[(set_attr "length" "0")])
|
||||
|
||||
;; include the arc-FPX instructions
|
||||
(include "fpx.md")
|
||||
|
||||
|
|
|
|||
|
|
@ -486,3 +486,7 @@ Enable use of NPS400 xld/xst extension.
|
|||
munaligned-access
|
||||
Target Report Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT)
|
||||
Enable unaligned word and halfword accesses to packed data.
|
||||
|
||||
mirq-ctrl-saved=
|
||||
Target RejectNegative Joined Var(arc_deferred_options) Defer
|
||||
Specifies the registers that the processor saves on an interrupt entry and exit.
|
||||
|
|
|
|||
|
|
@ -606,7 +606,7 @@ Objective-C and Objective-C++ Dialects}.
|
|||
-mnorm -mspfp -mspfp-compact -mspfp-fast -msimd -msoft-float -mswap @gol
|
||||
-mcrc -mdsp-packa -mdvbf -mlock -mmac-d16 -mmac-24 -mrtsc -mswape @gol
|
||||
-mtelephony -mxy -misize -mannotate-align -marclinux -marclinux_prof @gol
|
||||
-mlong-calls -mmedium-calls -msdata @gol
|
||||
-mlong-calls -mmedium-calls -msdata -mirq-ctrl-saved @gol
|
||||
-mvolatile-cache -mtp-regno=@var{regno} @gol
|
||||
-malign-call -mauto-modify-reg -mbbit-peephole -mno-brcc @gol
|
||||
-mcase-vector-pcrel -mcompact-casesi -mno-cond-exec -mearly-cbranchsi @gol
|
||||
|
|
@ -14547,6 +14547,15 @@ hardware extensions. Not available for ARC EM@.
|
|||
|
||||
@end table
|
||||
|
||||
@item -mirq-ctrl-saved=@var{register-range}, @var{blink}, @var{lp_count}
|
||||
@opindex mirq-ctrl-saved
|
||||
Specifies general-purposes registers that the processor automatically
|
||||
saves/restores on interrupt entry and exit. @var{register-range} is
|
||||
specified as two registers separated by a dash. The register range
|
||||
always starts with @code{r0}, the upper limit is @code{fp} register.
|
||||
@var{blink} and @var{lp_count} are optional. This option is only
|
||||
valid for ARC EM and ARC HS cores.
|
||||
|
||||
@end table
|
||||
|
||||
The following options are passed through to the assembler, and also
|
||||
|
|
|
|||
|
|
@ -1,3 +1,11 @@
|
|||
2017-05-09 Claudiu Zissulescu <claziss@synopsys.com>
|
||||
|
||||
* gcc.target/arc/interrupt-5.c: Newfile.
|
||||
* gcc.target/arc/interrupt-6.c: Likewise.
|
||||
* gcc.target/arc/interrupt-7.c: Likewise.
|
||||
* gcc.target/arc/interrupt-8.c: Likewise.
|
||||
* gcc.target/arc/interrupt-9.c: Likewise.
|
||||
|
||||
2017-05-09 Richard Biener <rguenther@suse.de>
|
||||
|
||||
* gcc.dg/vect/vect-44.c: Add --param vect-max-peeling-for-alignment=0
|
||||
|
|
|
|||
|
|
@ -0,0 +1,19 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-skip-if "Not available for ARCv1" { arc700 || arc6xx } } */
|
||||
/* { dg-options "-O2 -mirq-ctrl-saved=r0-r3,blink" } */
|
||||
|
||||
/* Check if the registers R0-R3,blink are automatically saved. */
|
||||
|
||||
extern int bar (void *);
|
||||
|
||||
void __attribute__ ((interrupt("ilink")))
|
||||
foo(void)
|
||||
{
|
||||
bar (0);
|
||||
__asm__ volatile ( "" : : : "r0","r1","r2","r3");
|
||||
}
|
||||
/* { dg-final { scan-assembler-not "st.*r0,\\\[sp" } } */
|
||||
/* { dg-final { scan-assembler-not "st.*r1,\\\[sp" } } */
|
||||
/* { dg-final { scan-assembler-not "st.*r2,\\\[sp" } } */
|
||||
/* { dg-final { scan-assembler-not "st.*r3,\\\[sp" } } */
|
||||
/* { dg-final { scan-assembler-not "push_s blink" } } */
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-skip-if "Not available for ARCv1" { arc700 || arc6xx } } */
|
||||
/* { dg-options "-O2 -mirq-ctrl-saved=r0-ilink" } */
|
||||
|
||||
#include <alloca.h>
|
||||
|
||||
/* Check if ilink is recognized. Check how FP and BLINK are saved.
|
||||
BLINK is saved last on the stack because the IRQ autosave will do
|
||||
first r0-ilink. To avoid this ABI exception, one needs to autosave
|
||||
always blink when using the IRQ autosave feature. */
|
||||
|
||||
extern int bar (void *);
|
||||
|
||||
void __attribute__ ((interrupt("ilink")))
|
||||
foo(void)
|
||||
{
|
||||
int *p = alloca (10);
|
||||
bar (p);
|
||||
}
|
||||
/* { dg-final { scan-assembler-not ".*fp,\\\[sp" } } */
|
||||
/* { dg-final { scan-assembler "ld.*blink,\\\[sp\\\]" } } */
|
||||
/* { dg-final { scan-assembler "push_s.*blink" } } */
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-skip-if "Not available for ARCv1" { arc700 || arc6xx } } */
|
||||
/* { dg-options "-O2 -mirq-ctrl-saved=r0-r17,blink" } */
|
||||
|
||||
/* Check if the registers R0-R17,blink are automatically saved. */
|
||||
|
||||
void __attribute__ ((interrupt("ilink")))
|
||||
foo(void)
|
||||
{
|
||||
__asm__ volatile ( "" : : : "r13","r14","r15","r16");
|
||||
}
|
||||
/* { dg-final { scan-assembler-not "st.*r13,\\\[sp" } } */
|
||||
/* { dg-final { scan-assembler-not "st.*r14,\\\[sp" } } */
|
||||
/* { dg-final { scan-assembler-not "st.*r15,\\\[sp" } } */
|
||||
/* { dg-final { scan-assembler-not "st.*r16,\\\[sp" } } */
|
||||
/* { dg-final { scan-assembler-not "push_s blink" } } */
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-skip-if "Not available for ARCv1" { arc700 || arc6xx } } */
|
||||
/* { dg-options "-O2 -mirq-ctrl-saved=r0-r17" } */
|
||||
|
||||
/* Check if the registers R0-R17 are automatically saved. GP is saved
|
||||
by the compiler. */
|
||||
|
||||
int a;
|
||||
|
||||
void __attribute__ ((interrupt("ilink")))
|
||||
foo(void)
|
||||
{
|
||||
__asm__ volatile ( "" : : : "r0","r1","r2","r3");
|
||||
__asm__ volatile ( "" : : : "r13","r14","r15","r16");
|
||||
a++;
|
||||
}
|
||||
/* { dg-final { scan-assembler-not "st.*r13,\\\[sp" } } */
|
||||
/* { dg-final { scan-assembler-not "st.*r14,\\\[sp" } } */
|
||||
/* { dg-final { scan-assembler-not "st.*r15,\\\[sp" } } */
|
||||
/* { dg-final { scan-assembler-not "st.*r16,\\\[sp" } } */
|
||||
/* { dg-final { scan-assembler "st.*gp,\\\[sp,-4\\\]" } } */
|
||||
/* { dg-final { scan-assembler "ld.*gp,\\\[sp\\\]" } } */
|
||||
/* { dg-final { scan-assembler-not "st.*r0,\\\[sp" } } */
|
||||
/* { dg-final { scan-assembler-not "st.*r1,\\\[sp" } } */
|
||||
/* { dg-final { scan-assembler-not "st.*r2,\\\[sp" } } */
|
||||
/* { dg-final { scan-assembler-not "st.*r3,\\\[sp" } } */
|
||||
/* { dg-final { scan-assembler "rtie" } } */
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target archs }*/
|
||||
/* { dg-options "-O0 -mirq-ctrl-saved=r0-fp" } */
|
||||
|
||||
/* Check if we get the move operation between fp and sp. */
|
||||
|
||||
void __attribute__ ((interrupt("ilink")))
|
||||
handler1 (void)
|
||||
{
|
||||
asm (""
|
||||
:
|
||||
:
|
||||
: "r0", "r1", "r2", "r3", "r4",
|
||||
"r5", "r6", "r7", "r8", "r9");
|
||||
}
|
||||
/* { dg-final { scan-assembler "mov.*fp,sp" } } */
|
||||
/* { dg-final { scan-assembler-not ".*fp,\\\[sp" } } */
|
||||
Loading…
Reference in New Issue