invoke.texi (SH Options): Undocument SH5/SH64 related options.
gcc/ * doc/invoke.texi (SH Options): Undocument SH5/SH64 related options. From-SVN: r227959
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Oleg Endo
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@ -1,3 +1,7 @@
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2015-09-21 Oleg Endo <olegendo@gcc.gnu.org>
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* doc/invoke.texi (SH Options): Undocument SH5/SH64 related options.
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2015-09-21 Oleg Endo <olegendo@gcc.gnu.org>
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PR target/67126
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@ -983,16 +983,12 @@ See RS/6000 and PowerPC Options.
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-m3 -m3e @gol
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-m4-nofpu -m4-single-only -m4-single -m4 @gol
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-m4a-nofpu -m4a-single-only -m4a-single -m4a -m4al @gol
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-m5-64media -m5-64media-nofpu @gol
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-m5-32media -m5-32media-nofpu @gol
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-m5-compact -m5-compact-nofpu @gol
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-mb -ml -mdalign -mrelax @gol
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-mbigtable -mfmovd -mhitachi -mrenesas -mno-renesas -mnomacsave @gol
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-mbigtable -mfmovd -mrenesas -mno-renesas -mnomacsave @gol
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-mieee -mno-ieee -mbitops -misize -minline-ic_invalidate -mpadstruct @gol
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-mspace -mprefergot -musermode -multcost=@var{number} -mdiv=@var{strategy} @gol
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-mdivsi3_libfunc=@var{name} -mfixed-range=@var{register-range} @gol
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-mindexed-addressing -mgettrcost=@var{number} -mpt-fixed @gol
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-maccumulate-outgoing-args -minvalid-symbols @gol
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-maccumulate-outgoing-args @gol
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-matomic-model=@var{atomic-model} @gol
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-mbranch-cost=@var{num} -mzdcbranch -mno-zdcbranch @gol
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-mcbranch-force-delay-slot @gol
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@ -20805,33 +20801,6 @@ Same as @option{-m4a-nofpu}, except that it implicitly passes
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@option{-dsp} to the assembler. GCC doesn't generate any DSP
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instructions at the moment.
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@item -m5-32media
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@opindex m5-32media
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Generate 32-bit code for SHmedia.
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@item -m5-32media-nofpu
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@opindex m5-32media-nofpu
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Generate 32-bit code for SHmedia in such a way that the
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floating-point unit is not used.
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@item -m5-64media
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@opindex m5-64media
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Generate 64-bit code for SHmedia.
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@item -m5-64media-nofpu
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@opindex m5-64media-nofpu
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Generate 64-bit code for SHmedia in such a way that the
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floating-point unit is not used.
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@item -m5-compact
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@opindex m5-compact
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Generate code for SHcompact.
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@item -m5-compact-nofpu
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@opindex m5-compact-nofpu
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Generate code for SHcompact in such a way that the
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floating-point unit is not used.
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@item -mb
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@opindex mb
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Compile code for the processor in big-endian mode.
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@ -21006,65 +20975,7 @@ Set the cost to assume for a multiply insn.
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@item -mdiv=@var{strategy}
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@opindex mdiv=@var{strategy}
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Set the division strategy to be used for integer division operations.
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For SHmedia @var{strategy} can be one of:
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@table @samp
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@item fp
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Performs the operation in floating point. This has a very high latency,
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but needs only a few instructions, so it might be a good choice if
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your code has enough easily-exploitable ILP to allow the compiler to
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schedule the floating-point instructions together with other instructions.
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Division by zero causes a floating-point exception.
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@item inv
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Uses integer operations to calculate the inverse of the divisor,
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and then multiplies the dividend with the inverse. This strategy allows
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CSE and hoisting of the inverse calculation. Division by zero calculates
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an unspecified result, but does not trap.
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@item inv:minlat
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A variant of @samp{inv} where, if no CSE or hoisting opportunities
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have been found, or if the entire operation has been hoisted to the same
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place, the last stages of the inverse calculation are intertwined with the
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final multiply to reduce the overall latency, at the expense of using a few
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more instructions, and thus offering fewer scheduling opportunities with
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other code.
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@item call
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Calls a library function that usually implements the @samp{inv:minlat}
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strategy.
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This gives high code density for @code{m5-*media-nofpu} compilations.
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@item call2
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Uses a different entry point of the same library function, where it
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assumes that a pointer to a lookup table has already been set up, which
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exposes the pointer load to CSE and code hoisting optimizations.
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@item inv:call
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@itemx inv:call2
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@itemx inv:fp
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Use the @samp{inv} algorithm for initial
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code generation, but if the code stays unoptimized, revert to the @samp{call},
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@samp{call2}, or @samp{fp} strategies, respectively. Note that the
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potentially-trapping side effect of division by zero is carried by a
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separate instruction, so it is possible that all the integer instructions
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are hoisted out, but the marker for the side effect stays where it is.
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A recombination to floating-point operations or a call is not possible
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in that case.
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@item inv20u
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@itemx inv20l
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Variants of the @samp{inv:minlat} strategy. In the case
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that the inverse calculation is not separated from the multiply, they speed
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up division where the dividend fits into 20 bits (plus sign where applicable)
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by inserting a test to skip a number of operations in this case; this test
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slows down the case of larger dividends. @samp{inv20u} assumes the case of a such
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a small dividend to be unlikely, and @samp{inv20l} assumes it to be likely.
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@end table
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For targets other than SHmedia @var{strategy} can be one of:
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@var{strategy} can be one of:
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@table @samp
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@ -21104,9 +21015,9 @@ needed for unwinding to avoid changing the stack frame around conditional code.
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@opindex mdivsi3_libfunc=@var{name}
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Set the name of the library function used for 32-bit signed division to
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@var{name}.
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This only affects the name used in the @samp{call} and @samp{inv:call}
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division strategies, and the compiler still expects the same
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sets of input/output/clobbered registers as if this option were not present.
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This only affects the name used in the @samp{call} division strategies, and
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the compiler still expects the same sets of input/output/clobbered registers as
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if this option were not present.
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@item -mfixed-range=@var{register-range}
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@opindex mfixed-range
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@ -21116,57 +21027,6 @@ useful when compiling kernel code. A register range is specified as
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two registers separated by a dash. Multiple register ranges can be
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specified separated by a comma.
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@item -mindexed-addressing
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@opindex mindexed-addressing
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Enable the use of the indexed addressing mode for SHmedia32/SHcompact.
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This is only safe if the hardware and/or OS implement 32-bit wrap-around
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semantics for the indexed addressing mode. The architecture allows the
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implementation of processors with 64-bit MMU, which the OS could use to
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get 32-bit addressing, but since no current hardware implementation supports
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this or any other way to make the indexed addressing mode safe to use in
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the 32-bit ABI, the default is @option{-mno-indexed-addressing}.
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@item -mgettrcost=@var{number}
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@opindex mgettrcost=@var{number}
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Set the cost assumed for the @code{gettr} instruction to @var{number}.
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The default is 2 if @option{-mpt-fixed} is in effect, 100 otherwise.
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@item -mpt-fixed
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@opindex mpt-fixed
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Assume @code{pt*} instructions won't trap. This generally generates
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better-scheduled code, but is unsafe on current hardware.
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The current architecture
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definition says that @code{ptabs} and @code{ptrel} trap when the target
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anded with 3 is 3.
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This has the unintentional effect of making it unsafe to schedule these
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instructions before a branch, or hoist them out of a loop. For example,
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@code{__do_global_ctors}, a part of @file{libgcc}
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that runs constructors at program
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startup, calls functions in a list which is delimited by @minus{}1. With the
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@option{-mpt-fixed} option, the @code{ptabs} is done before testing against @minus{}1.
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That means that all the constructors run a bit more quickly, but when
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the loop comes to the end of the list, the program crashes because @code{ptabs}
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loads @minus{}1 into a target register.
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Since this option is unsafe for any
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hardware implementing the current architecture specification, the default
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is @option{-mno-pt-fixed}. Unless specified explicitly with
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@option{-mgettrcost}, @option{-mno-pt-fixed} also implies @option{-mgettrcost=100};
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this deters register allocation from using target registers for storing
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ordinary integers.
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@item -minvalid-symbols
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@opindex minvalid-symbols
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Assume symbols might be invalid. Ordinary function symbols generated by
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the compiler are always valid to load with
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@code{movi}/@code{shori}/@code{ptabs} or
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@code{movi}/@code{shori}/@code{ptrel},
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but with assembler and/or linker tricks it is possible
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to generate symbols that cause @code{ptabs} or @code{ptrel} to trap.
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This option is only meaningful when @option{-mno-pt-fixed} is in effect.
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It prevents cross-basic-block CSE, hoisting and most scheduling
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of symbol loads. The default is @option{-mno-invalid-symbols}.
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@item -mbranch-cost=@var{num}
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@opindex mbranch-cost=@var{num}
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Assume @var{num} to be the cost for a branch instruction. Higher numbers
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