Introduce support for PKU instructions.
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_PKU_SET): New. (OPTION_MASK_ISA_PKU_UNSET): Ditto. (ix86_handle_option): Handle OPT_mpku. * config.gcc: Add pkuintrin.h to i[34567]86-*-* and x86_64-*-* targets. * config/i386/cpuid.h (host_detect_local_cpu): Detect PKU feature. * config/i386/i386-c.c (ix86_target_macros_internal): Handle PKU ISA flag. * config/i386/i386.c (ix86_target_string): Add "-mpku" to ix86_target_opts. (ix86_option_override_internal): Define PTA_PKU, mention new key in skylake-avx512. Handle new ISA bits. (ix86_valid_target_attribute_inner_p): Add "pku". (enum ix86_builtins): Add IX86_BUILTIN_RDPKRU and IX86_BUILTIN_WRPKRU. (builtin_description bdesc_special_args[]): Add new built-ins. * config/i386/i386.h (define TARGET_PKU): New. (define TARGET_PKU_P): Ditto. * config/i386/i386.md (define_c_enum "unspecv"): Add UNSPEC_PKU. (define_expand "rdpkru"): New. (define_insn "*rdpkru"): Ditto. (define_expand "wrpkru"): Ditto. (define_insn "*wrpkru"): Ditto. * config/i386/i386.opt (mpku): Ditto. * config/i386/pkuintrin.h: New file. * config/i386/x86intrin.h: Include pkuintrin.h * doc/extend.texi: Describe new built-ins. * doc/invoke.texi: Describe new switches. gcc/testsuite/ * g++.dg/other/i386-2.C: Add -mpku. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/rdpku-1.c: New test. * gcc.target/i386/sse-12.c: Add -mpku. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-33.c: Ditto. * gcc.target/i386/wrpku-1.c: New test. From-SVN: r231944
This commit is contained in:
Kirill Yukhin
Kirill Yukhin
parent
6549bdc6be
commit
41a4ef2243
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@ -1,3 +1,33 @@
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2015-12-24 Kirill Yukhin <kirill.yukhin@intel.com>
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* common/config/i386/i386-common.c (OPTION_MASK_ISA_PKU_SET): New.
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(OPTION_MASK_ISA_PKU_UNSET): Ditto.
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(ix86_handle_option): Handle OPT_mpku.
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* config.gcc: Add pkuintrin.h to i[34567]86-*-* and x86_64-*-*
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targets.
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* config/i386/cpuid.h (host_detect_local_cpu): Detect PKU feature.
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* config/i386/i386-c.c (ix86_target_macros_internal): Handle PKU ISA
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flag.
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* config/i386/i386.c (ix86_target_string): Add "-mpku" to
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ix86_target_opts.
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(ix86_option_override_internal): Define PTA_PKU, mention new key
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in skylake-avx512. Handle new ISA bits.
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(ix86_valid_target_attribute_inner_p): Add "pku".
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(enum ix86_builtins): Add IX86_BUILTIN_RDPKRU and IX86_BUILTIN_WRPKRU.
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(builtin_description bdesc_special_args[]): Add new built-ins.
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* config/i386/i386.h (define TARGET_PKU): New.
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(define TARGET_PKU_P): Ditto.
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* config/i386/i386.md (define_c_enum "unspecv"): Add UNSPEC_PKU.
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(define_expand "rdpkru"): New.
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(define_insn "*rdpkru"): Ditto.
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(define_expand "wrpkru"): Ditto.
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(define_insn "*wrpkru"): Ditto.
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* config/i386/i386.opt (mpku): Ditto.
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* config/i386/pkuintrin.h: New file.
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* config/i386/x86intrin.h: Include pkuintrin.h
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* doc/extend.texi: Describe new built-ins.
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* doc/invoke.texi: Describe new switches.
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2015-12-23 Richard Henderson <rth@redhat.com>
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PR ipa/67811
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@ -129,6 +129,7 @@ along with GCC; see the file COPYING3. If not see
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(OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
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#define OPTION_MASK_ISA_MWAITX_SET OPTION_MASK_ISA_MWAITX
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#define OPTION_MASK_ISA_CLZERO_SET OPTION_MASK_ISA_CLZERO
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#define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
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/* Define a set of ISAs which aren't available when a given ISA is
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disabled. MMX and SSE ISAs are handled separately. */
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@ -190,6 +191,7 @@ along with GCC; see the file COPYING3. If not see
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#define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
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#define OPTION_MASK_ISA_MWAITX_UNSET OPTION_MASK_ISA_MWAITX
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#define OPTION_MASK_ISA_CLZERO_UNSET OPTION_MASK_ISA_CLZERO
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#define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
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/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
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as -mno-sse4.1. */
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@ -962,6 +964,19 @@ ix86_handle_option (struct gcc_options *opts,
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}
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return true;
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case OPT_mpku:
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if (value)
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{
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opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU_SET;
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opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_SET;
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}
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else
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{
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opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PKU_UNSET;
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opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_UNSET;
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}
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return true;
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/* Comes from final.c -- no real reason to change it. */
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#define MAX_CODE_ALIGN 16
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@ -374,7 +374,8 @@ i[34567]86-*-*)
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xsavesintrin.h avx512dqintrin.h avx512bwintrin.h
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avx512vlintrin.h avx512vlbwintrin.h avx512vldqintrin.h
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avx512ifmaintrin.h avx512ifmavlintrin.h avx512vbmiintrin.h
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avx512vbmivlintrin.h clwbintrin.h pcommitintrin.h mwaitxintrin.h clzerointrin.h"
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avx512vbmivlintrin.h clwbintrin.h pcommitintrin.h
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mwaitxintrin.h clzerointrin.h pkuintrin.h"
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;;
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x86_64-*-*)
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cpu_type=i386
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@ -395,7 +396,8 @@ x86_64-*-*)
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xsavesintrin.h avx512dqintrin.h avx512bwintrin.h
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avx512vlintrin.h avx512vlbwintrin.h avx512vldqintrin.h
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avx512ifmaintrin.h avx512ifmavlintrin.h avx512vbmiintrin.h
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avx512vbmivlintrin.h clwbintrin.h pcommitintrin.h mwaitxintrin.h clzerointrin.h"
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avx512vbmivlintrin.h clwbintrin.h pcommitintrin.h
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mwaitxintrin.h clzerointrin.h pkuintrin.h"
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;;
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ia64-*-*)
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extra_headers=ia64intrin.h
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@ -95,6 +95,8 @@
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/* %ecx */
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#define bit_PREFETCHWT1 (1 << 0)
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#define bit_AVX512VBMI (1 << 1)
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#define bit_PKU (1 << 3)
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#define bit_OSPKE (1 << 4)
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/* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */
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#define bit_BNDREGS (1 << 3)
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@ -414,7 +414,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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unsigned int has_avx512dq = 0, has_avx512bw = 0, has_avx512vl = 0;
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unsigned int has_avx512vbmi = 0, has_avx512ifma = 0, has_clwb = 0;
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unsigned int has_pcommit = 0, has_mwaitx = 0;
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unsigned int has_clzero = 0;
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unsigned int has_clzero = 0, has_pku = 0;
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bool arch;
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@ -501,7 +501,8 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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has_avx512vl = ebx & bit_AVX512IFMA;
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has_prefetchwt1 = ecx & bit_PREFETCHWT1;
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has_avx512vl = ecx & bit_AVX512VBMI;
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has_avx512vbmi = ecx & bit_AVX512VBMI;
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has_pku = ecx & bit_OSPKE;
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}
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if (max_level >= 13)
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@ -971,6 +972,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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const char *pcommit = has_pcommit ? " -mpcommit" : " -mno-pcommit";
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const char *mwaitx = has_mwaitx ? " -mmwaitx" : " -mno-mwaitx";
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const char *clzero = has_clzero ? " -mclzero" : " -mno-clzero";
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const char *pku = has_pku ? " -mpku" : " -mno-pku";
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options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
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sse4a, cx16, sahf, movbe, aes, sha, pclmul,
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popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
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@ -980,7 +982,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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avx512cd, avx512pf, prefetchwt1, clflushopt,
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xsavec, xsaves, avx512dq, avx512bw, avx512vl,
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avx512ifma, avx512vbmi, clwb, pcommit, mwaitx,
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clzero, NULL);
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clzero, pku, NULL);
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}
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done:
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@ -439,6 +439,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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def_or_undef (parse_in, "__CLWB__");
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if (isa_flag & OPTION_MASK_ISA_MWAITX)
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def_or_undef (parse_in, "__MWAITX__");
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if (isa_flag & OPTION_MASK_ISA_PKU)
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def_or_undef (parse_in, "__PKU__");
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if (TARGET_IAMCU)
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{
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def_or_undef (parse_in, "__iamcu");
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@ -3755,6 +3755,7 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch,
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{ "-mpcommit", OPTION_MASK_ISA_PCOMMIT },
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{ "-mmwaitx", OPTION_MASK_ISA_MWAITX },
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{ "-mclzero", OPTION_MASK_ISA_CLZERO },
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{ "-mpku", OPTION_MASK_ISA_PKU },
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};
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/* Flag options. */
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@ -4310,6 +4311,7 @@ ix86_option_override_internal (bool main_args_p,
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#define PTA_MWAITX (HOST_WIDE_INT_1 << 57)
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#define PTA_CLZERO (HOST_WIDE_INT_1 << 58)
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#define PTA_NO_80387 (HOST_WIDE_INT_1 << 59)
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#define PTA_PKU (HOST_WIDE_INT_1 << 60)
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#define PTA_CORE2 \
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(PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
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@ -4331,7 +4333,7 @@ ix86_option_override_internal (bool main_args_p,
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(PTA_BROADWELL | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES)
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#define PTA_SKYLAKE_AVX512 \
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(PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL \
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| PTA_AVX512BW | PTA_AVX512DQ)
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| PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU)
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#define PTA_KNL \
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(PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
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#define PTA_BONNELL \
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@ -4934,6 +4936,9 @@ ix86_option_override_internal (bool main_args_p,
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if (processor_alias_table[i].flags & PTA_MWAITX
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&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_MWAITX))
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opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MWAITX;
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if (processor_alias_table[i].flags & PTA_PKU
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&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PKU))
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opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU;
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if (!(opts_set->x_target_flags & MASK_80387))
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{
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@ -5930,6 +5935,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[],
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IX86_ATTR_ISA ("pcommit", OPT_mpcommit),
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IX86_ATTR_ISA ("mwaitx", OPT_mmwaitx),
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IX86_ATTR_ISA ("clzero", OPT_mclzero),
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IX86_ATTR_ISA ("pku", OPT_mpku),
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/* enum options */
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IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
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@ -32286,6 +32292,10 @@ enum ix86_builtins
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IX86_BUILTIN_READ_FLAGS,
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IX86_BUILTIN_WRITE_FLAGS,
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/* PKU instructions. */
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IX86_BUILTIN_RDPKRU,
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IX86_BUILTIN_WRPKRU,
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IX86_BUILTIN_MAX
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};
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@ -32791,6 +32801,10 @@ static const struct builtin_description bdesc_special_args[] =
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/* PCOMMIT. */
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{ OPTION_MASK_ISA_PCOMMIT, CODE_FOR_pcommit, "__builtin_ia32_pcommit", IX86_BUILTIN_PCOMMIT, UNKNOWN, (int) VOID_FTYPE_VOID },
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/* RDPKRU and WRPKRU. */
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{ OPTION_MASK_ISA_PKU, CODE_FOR_rdpkru, "__builtin_ia32_rdpkru", IX86_BUILTIN_RDPKRU, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
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{ OPTION_MASK_ISA_PKU, CODE_FOR_wrpkru, "__builtin_ia32_wrpkru", IX86_BUILTIN_WRPKRU, UNKNOWN, (int) VOID_FTYPE_UNSIGNED }
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};
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/* Builtins with variable number of arguments. */
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@ -158,6 +158,9 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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#define TARGET_CLWB_P(x) TARGET_ISA_CLWB_P(x)
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#define TARGET_MWAITX TARGET_ISA_MWAITX
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#define TARGET_MWAITX_P(x) TARGET_ISA_MWAITX_P(x)
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#define TARGET_PKU TARGET_ISA_PKU
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#define TARGET_PKU_P(x) TARGET_ISA_PKU_P(x)
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#define TARGET_LP64 TARGET_ABI_64
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#define TARGET_LP64_P(x) TARGET_ABI_64_P(x)
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@ -268,6 +268,8 @@
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;; For CLZERO support
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UNSPECV_CLZERO
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;; For RDPKRU and WRPKRU support
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UNSPECV_PKU
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])
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;; Constants to represent rounding modes in the ROUND instruction
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@ -19320,6 +19322,48 @@
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[(set_attr "type" "imov")
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(set_attr "mode" "<MODE>")])
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;; RDPKRU and WRPKRU
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(define_expand "rdpkru"
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[(parallel
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[(set (match_operand:SI 0 "register_operand")
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(unspec_volatile:SI [(match_dup 1)] UNSPECV_PKU))
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(set (match_dup 2) (const_int 0))])]
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"TARGET_PKU"
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{
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operands[1] = force_reg (SImode, const0_rtx);
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operands[2] = gen_reg_rtx (SImode);
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})
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(define_insn "*rdpkru"
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[(set (match_operand:SI 0 "register_operand" "=a")
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(unspec_volatile:SI [(match_operand:SI 2 "register_operand" "c")]
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UNSPECV_PKU))
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(set (match_operand:SI 1 "register_operand" "=d")
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(const_int 0))]
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"TARGET_PKU"
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"rdpkru"
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[(set_attr "type" "other")])
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(define_expand "wrpkru"
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[(unspec_volatile:SI
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[(match_operand:SI 0 "register_operand")
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(match_dup 1) (match_dup 2)] UNSPECV_PKU)]
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"TARGET_PKU"
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{
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operands[1] = force_reg (SImode, const0_rtx);
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operands[2] = force_reg (SImode, const0_rtx);
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})
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(define_insn "*wrpkru"
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[(unspec_volatile:SI
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[(match_operand:SI 0 "register_operand" "a")
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(match_operand:SI 1 "register_operand" "d")
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(match_operand:SI 2 "register_operand" "c")] UNSPECV_PKU)]
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"TARGET_PKU"
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"wrpkru"
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[(set_attr "type" "other")])
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(include "mmx.md")
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(include "sse.md")
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(include "sync.md")
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@ -876,6 +876,10 @@ mclzero
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Target Report Mask(ISA_CLZERO) Var(ix86_isa_flags) Save
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Support CLZERO built-in functions and code generation.
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mpku
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Target Report Mask(ISA_PKU) Var(ix86_isa_flags) Save
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Support PKU built-in functions and code generation.
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mstack-protector-guard=
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Target RejectNegative Joined Enum(stack_protector_guard) Var(ix86_stack_protector_guard) Init(SSP_TLS)
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Use given stack-protector guard.
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@ -95,6 +95,8 @@
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#include <clzerointrin.h>
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#include <pkuintrin.h>
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#endif /* __iamcu__ */
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#endif /* _X86INTRIN_H_INCLUDED */
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@ -18343,6 +18343,13 @@ All of them generate the machine instruction that is part of the name.
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void __builtin_i32_clzero (void *)
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@end smallexample
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The following built-in functions are available when @option{-mpku} is used.
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They generate reads and writes to PKRU.
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@smallexample
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void __builtin_ia32_wrpkru (unsigned int)
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unsigned int __builtin_ia32_rdpkru ()
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@end smallexample
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@node x86 transactional memory intrinsics
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@subsection x86 Transactional Memory Intrinsics
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@ -1103,7 +1103,8 @@ See RS/6000 and PowerPC Options.
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-mpclmul -mfsgsbase -mrdrnd -mf16c -mfma @gol
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-mprefetchwt1 -mclflushopt -mxsavec -mxsaves @gol
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-msse4a -m3dnow -mpopcnt -mabm -mbmi -mtbm -mfma4 -mxop -mlzcnt @gol
|
||||
-mbmi2 -mfxsr -mxsave -mxsaveopt -mrtm -mlwp -mmpx -mmwaitx -mclzero -mthreads @gol
|
||||
-mbmi2 -mfxsr -mxsave -mxsaveopt -mrtm -mlwp -mmpx -mmwaitx -mclzero
|
||||
-mpku -mthreads @gol
|
||||
-mms-bitfields -mno-align-stringops -minline-all-stringops @gol
|
||||
-minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol
|
||||
-mmemcpy-strategy=@var{strategy} -mmemset-strategy=@var{strategy} @gol
|
||||
|
|
@ -22625,7 +22626,7 @@ AVX512CD instruction set support.
|
|||
|
||||
@item skylake-avx512
|
||||
Intel Skylake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
|
||||
SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
|
||||
SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
|
||||
BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
|
||||
AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support.
|
||||
|
||||
|
|
@ -23247,11 +23248,13 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
|
|||
@need 200
|
||||
@itemx -mclzero
|
||||
@opindex mclzero
|
||||
@itemx -mpku
|
||||
@opindex mpku
|
||||
These switches enable the use of instructions in the MMX, SSE,
|
||||
SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD,
|
||||
SHA, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM,
|
||||
AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA AVX512VBMI, BMI, BMI2, FXSR,
|
||||
XSAVE, XSAVEOPT, LZCNT, RTM, MPX, MWAITX or 3DNow!@:
|
||||
XSAVE, XSAVEOPT, LZCNT, RTM, MPX, MWAITX, PKU or 3DNow!@:
|
||||
extended instruction sets. Each has a corresponding @option{-mno-} option
|
||||
to disable use of these instructions.
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,14 @@
|
|||
2015-12-24 Kirill Yukhin <kirill.yukhin@intel.com>
|
||||
|
||||
* g++.dg/other/i386-2.C: Add -mpku.
|
||||
* g++.dg/other/i386-3.C: Ditto.
|
||||
* gcc.target/i386/rdpku-1.c: New test.
|
||||
* gcc.target/i386/sse-12.c: Add -mpku.
|
||||
* gcc.target/i386/sse-13.c: Ditto.
|
||||
* gcc.target/i386/sse-22.c: Ditto.
|
||||
* gcc.target/i386/sse-33.c: Ditto.
|
||||
* gcc.target/i386/wrpku-1.c: New test.
|
||||
|
||||
2015-12-23 Martin Sebor <msebor@redhat.com>
|
||||
|
||||
PR c++/69023
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
|
||||
/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mclwb -mpcommit -mmwaitx -mclzero" } */
|
||||
/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mclwb -mpcommit -mmwaitx -mclzero -mpku" } */
|
||||
|
||||
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
|
||||
xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
|
||||
popcntintrin.h, fmaintrin.h and mm_malloc.h.h are usable with
|
||||
popcntintrin.h, fmaintrin.h, pkuintrin.h and mm_malloc.h.h are usable with
|
||||
-O -pedantic-errors. */
|
||||
|
||||
#include <x86intrin.h>
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
|
||||
/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mclwb -mpcommit -mmwaitx -mclzero" } */
|
||||
/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mclwb -mpcommit -mmwaitx -mclzero -mpku" } */
|
||||
|
||||
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
|
||||
xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
|
||||
popcntintrin.h, fmaintrin.h and mm_malloc.h are usable with
|
||||
popcntintrin.h, fmaintrin.h, pkuintrin.h and mm_malloc.h are usable with
|
||||
-O -fkeep-inline-functions. */
|
||||
|
||||
#include <x86intrin.h>
|
||||
|
|
|
|||
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mpku -O2" } */
|
||||
/* { dg-final { scan-assembler "rdpkru\n" } } */
|
||||
|
||||
#include <x86intrin.h>
|
||||
|
||||
unsigned extern
|
||||
rdpku_test (void)
|
||||
{
|
||||
return _rdpkru_u32 ();
|
||||
}
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
popcntintrin.h and mm_malloc.h are usable
|
||||
with -O -std=c89 -pedantic-errors. */
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512ifma -mclwb -mpcommit -mmwaitx -mclzero" } */
|
||||
/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512ifma -mclwb -mpcommit -mmwaitx -mclzero -mpku" } */
|
||||
|
||||
#include <x86intrin.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512ifma -mclwb -mpcommit -mmwaitx -mclzero" } */
|
||||
/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512ifma -mclwb -mpcommit -mmwaitx -mclzero -mpku" } */
|
||||
|
||||
#include <mm_malloc.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -699,7 +699,7 @@ test_2 (_mm_clmulepi64_si128, __m128i, __m128i, __m128i, 1)
|
|||
|
||||
/* x86intrin.h (FMA4/XOP/LWP/BMI/BMI2/TBM/LZCNT/FMA). */
|
||||
#ifdef DIFFERENT_PRAGMAS
|
||||
#pragma GCC target ("fma4,xop,lwp,bmi,bmi2,tbm,lzcnt,fma,rdseed,prfchw,adx,fxsr,xsaveopt,xsavec,xsaves,clflushopt,clwb,pcommit")
|
||||
#pragma GCC target ("fma4,xop,lwp,bmi,bmi2,tbm,lzcnt,fma,rdseed,prfchw,adx,fxsr,xsaveopt,xsavec,xsaves,clflushopt,clwb,pcommit,pku")
|
||||
#endif
|
||||
#include <x86intrin.h>
|
||||
/* xopintrin.h */
|
||||
|
|
|
|||
|
|
@ -594,6 +594,6 @@
|
|||
#define __builtin_ia32_extracti64x2_256_mask(A, E, C, D) __builtin_ia32_extracti64x2_256_mask(A, 1, C, D)
|
||||
#define __builtin_ia32_extractf64x2_256_mask(A, E, C, D) __builtin_ia32_extractf64x2_256_mask(A, 1, C, D)
|
||||
|
||||
#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,clwb,pcommit,mwaitx,clzero")
|
||||
#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,clwb,pcommit,mwaitx,clzero,pku")
|
||||
|
||||
#include <x86intrin.h>
|
||||
|
|
|
|||
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-mpku -O2" } */
|
||||
/* { dg-final { scan-assembler "wrpkru\n" } } */
|
||||
|
||||
#include <x86intrin.h>
|
||||
|
||||
void extern
|
||||
wrpku_test (unsigned int key)
|
||||
{
|
||||
_wrpkru (key);
|
||||
}
|
||||
Loading…
Reference in New Issue