c-tree.texi (RDIV_EXPR): Fix typo.
* doc/c-tree.texi (RDIV_EXPR): Fix typo. * doc/rtl.texi (post_modify): Remove misplaced text, remove "not implemented" note. * doc/md.texi (IP2K): Move machine-specific constraints before MIPS for alphabetic order. * doc/tm.texi (TARGET_FLOAT_FORMAT): Update description for VAX_FLOAT_FORMAT. Remove reference to HOST_FLOAT_FORMAT. (VAX_HALFWORD_ORDER): Document. (LARGEST_EXPONENT_IS_NORMAL): Remove note about being only for IEEE float format. (TARGET_SCHED_ISSUE_RATE): Reword reference to MAX_DFA_ISSUE_RATE. (ASM_OUTPUT_LABEL_REF): Fix font. (CASE_VECTOR_SHORTEN_MODE): Ditto. From-SVN: r56687
This commit is contained in:
parent
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@ -1,3 +1,19 @@
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2002-08-30 Paul Koning <pkoning@equallogic.com>
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* doc/c-tree.texi (RDIV_EXPR): Fix typo.
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* doc/rtl.texi (post_modify): Remove misplaced text, remove "not
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implemented" note.
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* doc/md.texi (IP2K): Move machine-specific constraints before MIPS
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for alphabetic order.
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* doc/tm.texi (TARGET_FLOAT_FORMAT): Update description for
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VAX_FLOAT_FORMAT. Remove reference to HOST_FLOAT_FORMAT.
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(VAX_HALFWORD_ORDER): Document.
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(LARGEST_EXPONENT_IS_NORMAL): Remove note about being only for
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IEEE float format.
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(TARGET_SCHED_ISSUE_RATE): Reword reference to MAX_DFA_ISSUE_RATE.
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(ASM_OUTPUT_LABEL_REF): Fix font.
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(CASE_VECTOR_SHORTEN_MODE): Ditto.
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2002-08-30 Denis Chertykov <denisc@overta.ru>
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* config/ip2k/ip2k.c (ip2k_set_compare): Remove all const_double
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@ -2063,7 +2063,7 @@ integral type.
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The result of a @code{TRUNC_DIV_EXPR} is always rounded towards zero.
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The @code{TRUNC_MOD_EXPR} of two operands @code{a} and @code{b} is
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always @code{a - a/b} where the division is as if computed by a
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always @code{a - (a/b)*b} where the division is as if computed by a
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@code{TRUNC_DIV_EXPR}.
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@item ARRAY_REF
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128
gcc/doc/md.texi
128
gcc/doc/md.texi
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@ -1744,70 +1744,6 @@ Integer constant in the range 1 to 4 for @code{shladd} instruction
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Memory operand except postincrement and postdecrement
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@end table
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@item MIPS---@file{mips.h}
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@table @code
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@item d
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General-purpose integer register
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@item f
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Floating-point register (if available)
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@item h
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@samp{Hi} register
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@item l
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@samp{Lo} register
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@item x
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@samp{Hi} or @samp{Lo} register
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@item y
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General-purpose integer register
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@item z
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Floating-point status register
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@item I
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Signed 16-bit constant (for arithmetic instructions)
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@item J
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Zero
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@item K
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Zero-extended 16-bit constant (for logic instructions)
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@item L
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Constant with low 16 bits zero (can be loaded with @code{lui})
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@item M
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32-bit constant which requires two instructions to load (a constant
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which is not @samp{I}, @samp{K}, or @samp{L})
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@item N
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Negative 16-bit constant
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@item O
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Exact power of two
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@item P
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Positive 16-bit constant
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@item G
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Floating point zero
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@item Q
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Memory reference that can be loaded with more than one instruction
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(@samp{m} is preferable for @code{asm} statements)
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@item R
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Memory reference that can be loaded with one instruction
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(@samp{m} is preferable for @code{asm} statements)
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@item S
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Memory reference in external OSF/rose PIC format
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(@samp{m} is preferable for @code{asm} statements)
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@end table
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@item IP2K---@file{ip2k.h}
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@table @code
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@item a
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@ -1878,6 +1814,70 @@ Zero
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Integers from 0 to 255
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@end table
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@item MIPS---@file{mips.h}
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@table @code
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@item d
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General-purpose integer register
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@item f
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Floating-point register (if available)
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@item h
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@samp{Hi} register
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@item l
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@samp{Lo} register
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@item x
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@samp{Hi} or @samp{Lo} register
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@item y
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General-purpose integer register
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@item z
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Floating-point status register
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@item I
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Signed 16-bit constant (for arithmetic instructions)
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@item J
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Zero
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@item K
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Zero-extended 16-bit constant (for logic instructions)
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@item L
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Constant with low 16 bits zero (can be loaded with @code{lui})
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@item M
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32-bit constant which requires two instructions to load (a constant
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which is not @samp{I}, @samp{K}, or @samp{L})
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@item N
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Negative 16-bit constant
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@item O
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Exact power of two
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@item P
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Positive 16-bit constant
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@item G
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Floating point zero
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@item Q
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Memory reference that can be loaded with more than one instruction
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(@samp{m} is preferable for @code{asm} statements)
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@item R
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Memory reference that can be loaded with one instruction
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(@samp{m} is preferable for @code{asm} statements)
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@item S
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Memory reference in external OSF/rose PIC format
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(@samp{m} is preferable for @code{asm} statements)
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@end table
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@item Motorola 680x0---@file{m68k.h}
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@table @code
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@item a
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@ -2577,9 +2577,6 @@ Represents the side effect of setting @var{x} to @var{y} and
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represents @var{x} before @var{x} is modified. @var{x} must be a
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@code{reg} or @code{mem}, but most machines allow only a @code{reg}.
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@var{m} must be the machine mode for pointers on the machine in use.
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The amount @var{x} is decremented by is the length in bytes of the
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machine mode of the containing memory reference of which this expression
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serves as the address. Note that this is not currently implemented.
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The expression @var{y} must be one of three forms:
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@table @code
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@ -1320,7 +1320,8 @@ need to define this macro when the format is IEEE@.
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@findex VAX_FLOAT_FORMAT
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@item VAX_FLOAT_FORMAT
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This code indicates the ``D float'' format used on the VAX@.
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This code indicates the ``F float'' (for @code{float}) and ``D float''
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or ``G float'' formats (for @code{double}) used on the VAX and PDP-11@.
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@findex IBM_FLOAT_FORMAT
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@item IBM_FLOAT_FORMAT
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This code indicates any other format.
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@end table
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The value of this macro is compared with @code{HOST_FLOAT_FORMAT}, which
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is defined by the @command{configure} script, to determine whether the
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target machine has the same format as the host machine. If any other
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If any other
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formats are actually in use on supported machines, new codes should be
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defined for them.
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The ordering of the component words of floating point values stored in
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memory is controlled by @code{FLOAT_WORDS_BIG_ENDIAN}.
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@findex VAX_HALFWORD_ORDER
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@item VAX_HALFWORD_ORDER
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This macro is only used if @code{TARGET_FLOAT_FORMAT} is
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@code{VAX_FLOAT_FORMAT}. If defaulted or defined as 1, the halfwords of
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the generated floating point data are in the order used by the VAX. If
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defined as 0, they are reversed, which is used by the PDP-11 target.
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@findex MODE_HAS_NANS
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@item MODE_HAS_NANS (@var{mode})
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When defined, this macro should be true if @var{mode} has a NaN
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@findex LARGEST_EXPONENT_IS_NORMAL
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@item LARGEST_EXPONENT_IS_NORMAL (@var{size})
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This macro should only be defined when the target float format is
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described as IEEE@. It should return true if floats with @var{size}
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This macro should return true if floats with @var{size}
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bits do not have a NaN or infinity representation, but use the largest
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exponent for normal numbers instead.
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it to vary depending on what the instructions are, you must use
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@samp{TARGET_SCHED_VARIABLE_ISSUE}.
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You could use the value of macro @samp{MAX_DFA_ISSUE_RATE} to return
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the value of the hook @samp{TARGET_SCHED_ISSUE_RATE} for the automaton
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based pipeline interface.
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For the automaton based pipeline interface, you could define this hook
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to return the value of the macro @code{MAX_DFA_ISSUE_RATE}.
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@end deftypefn
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@deftypefn {Target Hook} int TARGET_SCHED_VARIABLE_ISSUE (FILE *@var{file}, int @var{verbose}, rtx @var{insn}, int @var{more})
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@findex ASM_OUTPUT_LABEL_REF
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@item ASM_OUTPUT_LABEL_REF (@var{stream}, @var{buf})
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A C statement (sans semicolon) to output a reference to @var{buf}, the
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result of ASM_GENERATE_INTERNAL_LABEL. If not defined,
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result of @code{ASM_GENERATE_INTERNAL_LABEL}. If not defined,
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@code{assemble_name} will be used to output the name of the symbol.
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This macro is not used by @code{output_asm_label}, or the @code{%l}
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specifier that calls it; the intention is that this macro should be set
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when it is necessary to output a label differently when its address
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is being taken.
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when it is necessary to output a label differently when its address is
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being taken.
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@findex ASM_OUTPUT_INTERNAL_LABEL
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@item ASM_OUTPUT_INTERNAL_LABEL (@var{stream}, @var{prefix}, @var{num})
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Optional: return the preferred mode for an @code{addr_diff_vec}
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when the minimum and maximum offset are known. If you define this,
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it enables extra code in branch shortening to deal with @code{addr_diff_vec}.
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To make this work, you also have to define INSN_ALIGN and
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To make this work, you also have to define @code{INSN_ALIGN} and
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make the alignment for @code{addr_diff_vec} explicit.
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The @var{body} argument is provided so that the offset_unsigned and scale
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flags can be updated.
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