re PR target/37191 (ICE in inline_secondary_memory_needed, at config/i386/i386.c:21849)
PR target/37191 * config/i386/sse.md (*vec_extract_v4sf_mem): Avoid combining registers from different units in a single alternative. From-SVN: r180560
This commit is contained in:
Uros Bizjak
parent
f6497cc6b5
commit
424c83890f
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@ -1,3 +1,9 @@
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2011-08-27 Uros Bizjak <ubizjak@gmail.com>
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PR target/37191
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* config/i386/sse.md (*vec_extract_v4sf_mem): Avoid combining registers
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from different units in a single alternative.
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2011-10-26 David S. Miller <davem@davemloft.net>
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* config/sparc/sparc.c (emit_scc_insn): Force attempt of v9 sequences
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@ -114,8 +120,7 @@
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2011-10-26 Richard Guenther <rguenther@suse.de>
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PR lto/41844
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* Makefile.in (lto-wrapper): Depend on and link against
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opts-common.o.
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* Makefile.in (lto-wrapper): Depend on and link against opts-common.o.
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(lto-wrapper.o): Depend on $(OPTS_H) and $(OPTIONS_H).
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* lto-wrapper.c (get_options_from_collect_gcc_options): New function.
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(run_gcc): Use it. Filter out language specific options.
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@ -223,8 +228,7 @@
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2011-10-25 Dodji Seketeli <dodji@redhat.com>
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* input.c (expand_location): Rewrite using
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linemap_resolve_location and linemap_expand_location. Add a
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comment.
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linemap_resolve_location and linemap_expand_location. Add a comment.
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2011-10-25 Jakub Jelinek <jakub@redhat.com>
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@ -265,8 +269,8 @@
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to MASK_LITTLE_ENDIAN.
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* config/sparc/sparc.opt (Mask(LITTLE_ENDIAN)): Delete.
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* config/sparc/sparc.md: Only use F, G, and C constraints in FP
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insns. Only use D, Y, and Z constraints in vector insns.
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* config/sparc/sparc.md: Only use F, G, and C constraints in FP insns.
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Only use D, Y, and Z constraints in vector insns.
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* config/sparc/sparc.md (cpu_feature, enabled): New attributes.
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(*movsi_insn_novis3, *movsi_insn_vis3): Consolidate into one pattern
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@ -343,7 +347,7 @@
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2011-10-24 Julian Brown <julian@codesourcery.com>
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* config/m68k/m68k.c (notice_update_cc): Tighten condition for
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setting CC_REVERSED for FP comparisons.
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setting CC_REVERSED for FP comparisons.
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2011-10-24 Richard Guenther <rguenther@suse.de>
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@ -396,14 +400,12 @@
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float and integer regs.
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(sparc_register_move_cost): Adjust to account for VIS3 moves.
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(sparc_preferred_reload_class): On 32-bit with VIS3 when moving an
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integer reg to a class containing EXTRA_FP_REGS, constrain to
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FP_REGS.
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integer reg to a class containing EXTRA_FP_REGS, constrain to FP_REGS.
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(sparc_secondary_reload): On 32-bit with VIS3 when moving between
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float and integer regs we sometimes need a FP_REGS class
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intermediate move to satisfy the reload. When this happens
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specify an extra cost of 2.
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(*movsi_insn): Rename to have "_novis3" suffix and add !VIS3
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guard.
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(*movsi_insn): Rename to have "_novis3" suffix and add !VIS3 guard.
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(*movdi_insn_sp32_v9): Likewise.
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(*movdi_insn_sp64): Likewise.
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(*movsf_insn): Likewise.
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@ -429,8 +431,7 @@
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(*mov<VM64:mode>_insn_sp32_vis3): New insn.
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(VM64 reg<-->reg split): New spliiter for 32-bit.
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* config/sparc/sparc.c (sparc_split_regreg_legitimate): New
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function.
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* config/sparc/sparc.c (sparc_split_regreg_legitimate): New function.
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* config/sparc/sparc-protos.h (sparc_split_regreg_legitimate):
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Declare it.
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* config/sparc/sparc.md (DImode reg/reg split): Use it.
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@ -3866,6 +3866,62 @@
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DONE;
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})
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(define_insn_and_split "*sse4_1_extractps"
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[(set (match_operand:SF 0 "nonimmediate_operand" "=rm,x,x")
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(vec_select:SF
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(match_operand:V4SF 1 "register_operand" "x,0,x")
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(parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n,n")])))]
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"TARGET_SSE4_1"
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"@
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%vextractps\t{%2, %1, %0|%0, %1, %2}
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#
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#"
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"&& reload_completed && SSE_REG_P (operands[0])"
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[(const_int 0)]
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{
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rtx dest = gen_rtx_REG (V4SFmode, REGNO (operands[0]));
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switch (INTVAL (operands[2]))
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{
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case 1:
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case 3:
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emit_insn (gen_sse_shufps_v4sf (dest, operands[1], operands[1],
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operands[2], operands[2],
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GEN_INT (INTVAL (operands[2]) + 4),
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GEN_INT (INTVAL (operands[2]) + 4)));
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break;
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case 2:
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emit_insn (gen_vec_interleave_highv4sf (dest, operands[1], operands[1]));
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break;
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default:
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/* 0 should be handled by the *vec_extractv4sf_0 pattern above. */
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gcc_unreachable ();
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}
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DONE;
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}
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[(set_attr "isa" "*,noavx,avx")
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(set_attr "type" "sselog,*,*")
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(set_attr "prefix_data16" "1,*,*")
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(set_attr "prefix_extra" "1,*,*")
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(set_attr "length_immediate" "1,*,*")
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(set_attr "prefix" "maybe_vex,*,*")
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(set_attr "mode" "V4SF,*,*")])
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(define_insn_and_split "*vec_extract_v4sf_mem"
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[(set (match_operand:SF 0 "register_operand" "=x,*r,f")
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(vec_select:SF
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(match_operand:V4SF 1 "memory_operand" "o,o,o")
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(parallel [(match_operand 2 "const_0_to_3_operand" "n,n,n")])))]
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"TARGET_SSE"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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int i = INTVAL (operands[2]);
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emit_move_insn (operands[0], adjust_address (operands[1], SFmode, i*4));
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DONE;
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})
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(define_expand "avx_vextractf128<mode>"
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[(match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "")
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(match_operand:V_256 1 "register_operand" "")
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@ -4044,62 +4100,6 @@
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(set_attr "prefix" "vex")
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(set_attr "mode" "OI")])
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(define_insn_and_split "*sse4_1_extractps"
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[(set (match_operand:SF 0 "nonimmediate_operand" "=rm,x,x")
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(vec_select:SF
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(match_operand:V4SF 1 "register_operand" "x,0,x")
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(parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n,n")])))]
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"TARGET_SSE4_1"
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"@
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%vextractps\t{%2, %1, %0|%0, %1, %2}
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#
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#"
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"&& reload_completed && SSE_REG_P (operands[0])"
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[(const_int 0)]
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{
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rtx dest = gen_rtx_REG (V4SFmode, REGNO (operands[0]));
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switch (INTVAL (operands[2]))
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{
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case 1:
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case 3:
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emit_insn (gen_sse_shufps_v4sf (dest, operands[1], operands[1],
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operands[2], operands[2],
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GEN_INT (INTVAL (operands[2]) + 4),
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GEN_INT (INTVAL (operands[2]) + 4)));
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break;
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case 2:
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emit_insn (gen_vec_interleave_highv4sf (dest, operands[1], operands[1]));
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break;
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default:
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/* 0 should be handled by the *vec_extractv4sf_0 pattern above. */
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gcc_unreachable ();
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}
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DONE;
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}
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[(set_attr "isa" "*,noavx,avx")
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(set_attr "type" "sselog,*,*")
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(set_attr "prefix_data16" "1,*,*")
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(set_attr "prefix_extra" "1,*,*")
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(set_attr "length_immediate" "1,*,*")
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(set_attr "prefix" "maybe_vex,*,*")
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(set_attr "mode" "V4SF,*,*")])
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(define_insn_and_split "*vec_extract_v4sf_mem"
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[(set (match_operand:SF 0 "register_operand" "=x*rf")
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(vec_select:SF
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(match_operand:V4SF 1 "memory_operand" "o")
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(parallel [(match_operand 2 "const_0_to_3_operand" "n")])))]
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"TARGET_SSE"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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int i = INTVAL (operands[2]);
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emit_move_insn (operands[0], adjust_address (operands[1], SFmode, i*4));
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DONE;
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})
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;; Modes handled by vec_extract patterns.
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(define_mode_iterator VEC_EXTRACT_MODE
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[(V32QI "TARGET_AVX") V16QI
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