re PR target/84154 (PowerPC GCC 7 and 8 have regression in converting fp to short/char and returning it)
[gcc] 2018-02-07 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/84154 * config/rs6000/rs6000.md (fix_trunc<SFDF:mode><QHI:mode>2): Convert from define_expand to be define_insn_and_split. Rework float/double/_Float128 conversions to QI/HI/SImode to work with both ISA 2.07 (power8) or ISA 3.0 (power9). Fix regression where conversions to QI/HImode types did a store and then a load to truncate the value. For conversions to VSX registers, don't split the insn, instead emit the code directly. Use the code iterator any_fix to combine signed and unsigned conversions. (fix<uns>_trunc<SFDF:mode>si2_p8): Likewise. (fixuns_trunc<SFDF:mode><QHI:mode>2): Likewise. (fix_trunc<IEEE128:mode><QHI:mode>2): Likewise. (fix<uns>_trunc<SFDF:mode><QHI:mode>2): Likewise. (fix_<mode>di2_hw): Likewise. (fixuns_<mode>di2_hw): Likewise. (fix_<mode>si2_hw): Likewise. (fixuns_<mode>si2_hw): Likewise. (fix<uns>_<IEEE128:mode><SDI:mode>2_hw): Likewise. (fix<uns>_trunc<IEEE128:mode><QHI:mode>2): Likewise. (fctiw<u>z_<mode>_smallint): Rename fctiw<u>z_<mode>_smallint to fix<uns>_trunc<SFDF:mode>si2_p8. (fix_trunc<SFDF:mode><QHI:mode>2_internal): Delete, no longer used. (fixuns_trunc<SFDF:mode><QHI:mode>2_internal): Likewise. (fix<uns>_<mode>_mem): Likewise. (fctiw<u>z_<mode>_mem): Likewise. (fix<uns>_<mode>_mem): Likewise. (fix<uns>_trunc<SFDF:mode><QHSI:mode>2_mem): On ISA 3.0, prevent the register allocator from doing a direct move to the GPRs to do a store, and instead use the ISA 3.0 store byte/half-word from vector register instruction. For IEEE 128-bit floating point, also optimize stores of 32-bit ints. (fix<uns>_trunc<IEEE128:mode><QHSI:mode>2_mem): Likewise. [gcc/testsuite] 2018-02-07 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/84154 * gcc.target/powerpc/pr84154-1.c: New tests. * gcc.target/powerpc/pr84154-2.c: Likewise. * gcc.target/powerpc/pr84154-3.c: Likewise. From-SVN: r257470
This commit is contained in:
Michael Meissner
Michael Meissner
parent
54af445d3c
commit
4253435eca
@ -1,3 +1,39 @@
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2018-02-07 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/84154
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* config/rs6000/rs6000.md (fix_trunc<SFDF:mode><QHI:mode>2):
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Convert from define_expand to be define_insn_and_split. Rework
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float/double/_Float128 conversions to QI/HI/SImode to work with
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both ISA 2.07 (power8) or ISA 3.0 (power9). Fix regression where
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conversions to QI/HImode types did a store and then a load to
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truncate the value. For conversions to VSX registers, don't split
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the insn, instead emit the code directly. Use the code iterator
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any_fix to combine signed and unsigned conversions.
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(fix<uns>_trunc<SFDF:mode>si2_p8): Likewise.
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(fixuns_trunc<SFDF:mode><QHI:mode>2): Likewise.
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(fix_trunc<IEEE128:mode><QHI:mode>2): Likewise.
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(fix<uns>_trunc<SFDF:mode><QHI:mode>2): Likewise.
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(fix_<mode>di2_hw): Likewise.
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(fixuns_<mode>di2_hw): Likewise.
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(fix_<mode>si2_hw): Likewise.
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(fixuns_<mode>si2_hw): Likewise.
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(fix<uns>_<IEEE128:mode><SDI:mode>2_hw): Likewise.
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(fix<uns>_trunc<IEEE128:mode><QHI:mode>2): Likewise.
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(fctiw<u>z_<mode>_smallint): Rename fctiw<u>z_<mode>_smallint to
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fix<uns>_trunc<SFDF:mode>si2_p8.
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(fix_trunc<SFDF:mode><QHI:mode>2_internal): Delete, no longer
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used.
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(fixuns_trunc<SFDF:mode><QHI:mode>2_internal): Likewise.
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(fix<uns>_<mode>_mem): Likewise.
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(fctiw<u>z_<mode>_mem): Likewise.
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(fix<uns>_<mode>_mem): Likewise.
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(fix<uns>_trunc<SFDF:mode><QHSI:mode>2_mem): On ISA 3.0, prevent
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the register allocator from doing a direct move to the GPRs to do
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a store, and instead use the ISA 3.0 store byte/half-word from
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vector register instruction. For IEEE 128-bit floating point,
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also optimize stores of 32-bit ints.
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(fix<uns>_trunc<IEEE128:mode><QHSI:mode>2_mem): Likewise.
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2018-02-07 Alan Hayward <alan.hayward@arm.com>
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* genextract.c (push_pathstr_operand): New function to support
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@ -5700,43 +5700,59 @@
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xscvdpsxds %x0,%x1"
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[(set_attr "type" "fp")])
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(define_expand "fix_trunc<SFDF:mode><QHI:mode>2"
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[(parallel [(set (match_operand:<QHI:MODE> 0 "nonimmediate_operand")
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(fix:QHI (match_operand:SFDF 1 "gpc_reg_operand")))
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(clobber (match_scratch:DI 2))])]
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"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
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;; If we have ISA 3.0, QI/HImode values can go in both VSX registers and GPR
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;; registers. If we have ISA 2.07, we don't allow QI/HImode values in the
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;; vector registers, so we need to do direct moves to the GPRs, but SImode
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;; values can go in VSX registers. Keeping the direct move part through
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;; register allocation prevents the register allocator from doing a direct move
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;; of the SImode value to a GPR, and then a store/load.
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(define_insn_and_split "fix<uns>_trunc<SFDF:mode><QHI:mode>2"
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[(set (match_operand:<QHI:MODE> 0 "gpc_reg_operand" "=wJ,wJwK,r")
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(any_fix:QHI (match_operand:SFDF 1 "gpc_reg_operand" "wJ,wJwK,wa")))
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(clobber (match_scratch:SI 2 "=X,X,wi"))]
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"TARGET_DIRECT_MOVE"
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"@
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fctiw<u>z %0,%1
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xscvdp<su>xws %x0,%x1
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#"
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"&& reload_completed && int_reg_operand (operands[0], <QHI:MODE>mode)"
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[(set (match_dup 2)
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(any_fix:SI (match_dup 1)))
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(set (match_dup 3)
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(match_dup 2))]
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{
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if (MEM_P (operands[0]))
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operands[0] = rs6000_address_for_fpconvert (operands[0]);
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})
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operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]));
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}
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[(set_attr "length" "4,4,8")
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(set_attr "type" "fp")])
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(define_insn_and_split "*fix_trunc<SFDF:mode><QHI:mode>2_internal"
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[(set (match_operand:<QHI:MODE> 0 "reg_or_indexed_operand" "=wIwJ,rZ")
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(fix:QHI
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(match_operand:SFDF 1 "gpc_reg_operand" "<SFDF:Fv>,<SFDF:Fv>")))
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(clobber (match_scratch:DI 2 "=X,wi"))]
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"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
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(define_insn "*fix<uns>_trunc<SFDF:mode>si2_p8"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=d,wa")
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(any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")))]
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"TARGET_DIRECT_MOVE"
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"@
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fctiw<u>z %0,%1
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xscvdp<su>xws %x0,%x1"
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[(set_attr "type" "fp")])
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;; Keep the convert and store together through register allocation to prevent
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;; the register allocator from getting clever and doing a direct move to a GPR
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;; and then store for reg+offset stores.
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(define_insn_and_split "*fix<uns>_trunc<SFDF:mode><QHSI:mode>2_mem"
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[(set (match_operand:QHSI 0 "memory_operand" "=Z")
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(any_fix:QHSI (match_operand:SFDF 1 "gpc_reg_operand" "wa")))
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(clobber (match_scratch:SI 2 "=wa"))]
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"(<QHSI:MODE>mode == SImode && TARGET_P8_VECTOR) || TARGET_P9_VECTOR"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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[(set (match_dup 2)
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(any_fix:SI (match_dup 1)))
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(set (match_dup 0)
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(match_dup 3))]
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{
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rtx dest = operands[0];
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rtx src = operands[1];
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if (vsx_register_operand (dest, <QHI:MODE>mode))
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{
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rtx di_dest = gen_rtx_REG (DImode, REGNO (dest));
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emit_insn (gen_fix_trunc<SFDF:mode>di2 (di_dest, src));
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}
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else
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{
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rtx tmp = operands[2];
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rtx tmp2 = gen_rtx_REG (<QHI:MODE>mode, REGNO (tmp));
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emit_insn (gen_fix_trunc<SFDF:mode>di2 (tmp, src));
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emit_move_insn (dest, tmp2);
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}
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DONE;
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operands[3] = (<QHSI:MODE>mode == SImode
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? operands[2]
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: gen_rtx_REG (<QHSI:MODE>mode, REGNO (operands[2])));
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})
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(define_expand "fixuns_trunc<mode>si2"
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@ -5803,71 +5819,6 @@
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xscvdpuxds %x0,%x1"
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[(set_attr "type" "fp")])
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(define_expand "fixuns_trunc<SFDF:mode><QHI:mode>2"
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[(parallel [(set (match_operand:<QHI:MODE> 0 "nonimmediate_operand")
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(unsigned_fix:QHI (match_operand:SFDF 1 "gpc_reg_operand")))
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(clobber (match_scratch:DI 2))])]
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"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
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{
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if (MEM_P (operands[0]))
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operands[0] = rs6000_address_for_fpconvert (operands[0]);
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})
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(define_insn_and_split "*fixuns_trunc<SFDF:mode><QHI:mode>2_internal"
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[(set (match_operand:<QHI:MODE> 0 "reg_or_indexed_operand" "=wIwJ,rZ")
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(unsigned_fix:QHI
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(match_operand:SFDF 1 "gpc_reg_operand" "<SFDF:Fv>,<SFDF:Fv>")))
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(clobber (match_scratch:DI 2 "=X,wi"))]
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"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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rtx dest = operands[0];
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rtx src = operands[1];
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if (vsx_register_operand (dest, <QHI:MODE>mode))
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{
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rtx di_dest = gen_rtx_REG (DImode, REGNO (dest));
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emit_insn (gen_fixuns_trunc<SFDF:mode>di2 (di_dest, src));
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}
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else
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{
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rtx tmp = operands[2];
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rtx tmp2 = gen_rtx_REG (<QHI:MODE>mode, REGNO (tmp));
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emit_insn (gen_fixuns_trunc<SFDF:mode>di2 (tmp, src));
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emit_move_insn (dest, tmp2);
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}
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DONE;
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})
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;; If -mvsx-small-integer, we can represent the FIX operation directly. On
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;; older machines, we have to use an UNSPEC to produce a SImode and move it
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;; to another location, since SImode is not allowed in vector registers.
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(define_insn "*fctiw<u>z_<mode>_smallint"
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[(set (match_operand:SI 0 "vsx_register_operand" "=d,wi")
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(any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
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"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_P8_VECTOR"
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"@
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fctiw<u>z %0,%1
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xscvdp<su>xws %x0,%x1"
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[(set_attr "type" "fp")])
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;; Combiner pattern to prevent moving the result of converting a floating point
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;; value to 32-bit integer to GPR in order to save it.
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(define_insn_and_split "*fctiw<u>z_<mode>_mem"
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[(set (match_operand:SI 0 "memory_operand" "=Z")
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(any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "wa")))
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(clobber (match_scratch:SI 2 "=wa"))]
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"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_P8_VECTOR"
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"#"
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"&& reload_completed"
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[(set (match_dup 2)
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(any_fix:SI (match_dup 1)))
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(set (match_dup 0)
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(match_dup 2))])
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;; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
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;; rather than (set (subreg:SI (reg)) (fix:SI ...))
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;; because the first makes it clear that operand 0 is not live
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@ -14362,49 +14313,45 @@
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(set_attr "length" "8")])
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;; Conversion between IEEE 128-bit and integer types
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(define_insn "fix_<mode>di2_hw"
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[(set (match_operand:DI 0 "altivec_register_operand" "=v")
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(fix:DI (match_operand:IEEE128 1 "altivec_register_operand" "v")))]
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"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
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"xscvqpsdz %0,%1"
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;; The fix function for DImode and SImode was declared earlier as a
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;; define_expand. It calls into rs6000_expand_float128_convert if we don't
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;; have IEEE 128-bit hardware support. QImode and HImode are not provided
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;; unless we have the IEEE 128-bit hardware.
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;;
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;; Unlike the code for converting SFmode/DFmode to QImode/HImode, we don't have
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;; to provide a GPR target that used direct move and a conversion in the GPR
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;; which works around QImode/HImode not being allowed in vector registers in
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;; ISA 2.07 (power8).
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(define_insn "fix<uns>_<IEEE128:mode><SDI:mode>2_hw"
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[(set (match_operand:SDI 0 "altivec_register_operand" "=v")
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(any_fix:SDI (match_operand:IEEE128 1 "altivec_register_operand" "v")))]
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"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
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"xscvqp<su><wd>z %0,%1"
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[(set_attr "type" "vecfloat")
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(set_attr "size" "128")])
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(define_insn "fixuns_<mode>di2_hw"
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[(set (match_operand:DI 0 "altivec_register_operand" "=v")
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(unsigned_fix:DI (match_operand:IEEE128 1 "altivec_register_operand" "v")))]
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"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
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"xscvqpudz %0,%1"
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(define_insn "fix<uns>_trunc<IEEE128:mode><QHI:mode>2"
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[(set (match_operand:QHI 0 "altivec_register_operand" "=v")
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(any_fix:QHI
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(match_operand:IEEE128 1 "altivec_register_operand" "v")))]
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"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
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"xscvqp<su>wz %0,%1"
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[(set_attr "type" "vecfloat")
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(set_attr "size" "128")])
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(define_insn "fix_<mode>si2_hw"
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[(set (match_operand:SI 0 "altivec_register_operand" "=v")
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(fix:SI (match_operand:IEEE128 1 "altivec_register_operand" "v")))]
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"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
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"xscvqpswz %0,%1"
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[(set_attr "type" "vecfloat")
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(set_attr "size" "128")])
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(define_insn "fixuns_<mode>si2_hw"
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[(set (match_operand:SI 0 "altivec_register_operand" "=v")
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(unsigned_fix:SI (match_operand:IEEE128 1 "altivec_register_operand" "v")))]
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"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
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"xscvqpuwz %0,%1"
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[(set_attr "type" "vecfloat")
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(set_attr "size" "128")])
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;; Combiner pattern to prevent moving the result of converting an IEEE 128-bit
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;; floating point value to 32-bit integer to GPR in order to save it.
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(define_insn_and_split "*fix<uns>_<mode>_mem"
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[(set (match_operand:SI 0 "memory_operand" "=Z")
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(any_fix:SI (match_operand:IEEE128 1 "altivec_register_operand" "v")))
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(clobber (match_scratch:SI 2 "=v"))]
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;; Combiner patterns to prevent moving the result of converting an IEEE 128-bit
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;; floating point value to 8/16/32-bit integer to GPR in order to save it.
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(define_insn_and_split "*fix<uns>_trunc<IEEE128:mode><QHSI:mode>2_mem"
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[(set (match_operand:QHSI 0 "memory_operand" "=Z")
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(any_fix:QHSI
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(match_operand:IEEE128 1 "altivec_register_operand" "v")))
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(clobber (match_scratch:QHSI 2 "=v"))]
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"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
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"#"
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"&& reload_completed"
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[(set (match_dup 2)
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(any_fix:SI (match_dup 1)))
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(any_fix:QHSI (match_dup 1)))
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(set (match_dup 0)
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(match_dup 2))])
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@ -1,3 +1,10 @@
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2018-02-07 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/84154
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* gcc.target/powerpc/pr84154-1.c: New tests.
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* gcc.target/powerpc/pr84154-2.c: Likewise.
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* gcc.target/powerpc/pr84154-3.c: Likewise.
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2018-02-07 Will Schmidt <will_schmidt@vnet.ibm.com>
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* gcc.target/powerpc/builtins-mergew-mergeow.c: Update dg-requires.
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55
gcc/testsuite/gcc.target/powerpc/pr84154-1.c
Normal file
55
gcc/testsuite/gcc.target/powerpc/pr84154-1.c
Normal file
@ -0,0 +1,55 @@
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/* { dg-do compile { target { powerpc*-*-* } } } */
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/* { dg-skip-if "" { powerpc*-*-darwin* } } */
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/* { dg-require-effective-target powerpc_p8vector_ok } */
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/* { dg-options "-mpower8-vector -O2" } */
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/* PR target/84154. Make sure conversion to char/short does not generate a
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store and a load on ISA 2.07 and newer systems. */
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unsigned char
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double_to_uc (double x)
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{
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return x;
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}
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signed char
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double_to_sc (double x)
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{
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return x;
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}
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unsigned short
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double_to_us (double x)
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{
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return x;
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}
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||||
|
||||
short
|
||||
double_to_ss (double x)
|
||||
{
|
||||
return x;
|
||||
}
|
||||
|
||||
unsigned int
|
||||
double_to_ui (double x)
|
||||
{
|
||||
return x;
|
||||
}
|
||||
|
||||
int
|
||||
double_to_si (double x)
|
||||
{
|
||||
return x;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mextsb\M} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\mextsh\M} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\mmfvsrwz\M} 6 } } */
|
||||
/* { dg-final { scan-assembler-times {\mrlwinm\M} 2 } } */
|
||||
/* { dg-final { scan-assembler-not {\mlbz\M} } } */
|
||||
/* { dg-final { scan-assembler-not {\mlhz\M} } } */
|
||||
/* { dg-final { scan-assembler-not {\mlha\M} } } */
|
||||
/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
|
||||
/* { dg-final { scan-assembler-not {\mstw\M} } } */
|
||||
58
gcc/testsuite/gcc.target/powerpc/pr84154-2.c
Normal file
58
gcc/testsuite/gcc.target/powerpc/pr84154-2.c
Normal file
@ -0,0 +1,58 @@
|
||||
/* { dg-do compile { target { powerpc*-*-* } } } */
|
||||
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
|
||||
/* { dg-require-effective-target powerpc_p8vector_ok } */
|
||||
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
|
||||
/* { dg-options "-mcpu=power8 -O2" } */
|
||||
|
||||
/* PR target/84154. Make sure on ISA 2.07 (power8) that we store the result of
|
||||
a conversion to char/short using an offsettable address does not generate
|
||||
direct moves for storing 32-bit integers, but does do a direct move for
|
||||
8/16-bit integers. */
|
||||
|
||||
void
|
||||
double_to_uc (double x, unsigned char *p)
|
||||
{
|
||||
p[3] = x;
|
||||
}
|
||||
|
||||
void
|
||||
double_to_sc (double x, signed char *p)
|
||||
{
|
||||
p[3] = x;
|
||||
}
|
||||
|
||||
void
|
||||
double_to_us (double x, unsigned short *p)
|
||||
{
|
||||
p[3] = x;
|
||||
}
|
||||
|
||||
void
|
||||
double_to_ss (double x, short *p)
|
||||
{
|
||||
p[3] = x;
|
||||
}
|
||||
|
||||
void
|
||||
double_to_ui (double x, unsigned int *p)
|
||||
{
|
||||
p[3] = x;
|
||||
}
|
||||
|
||||
void
|
||||
double_to_si (double x, int *p)
|
||||
{
|
||||
p[3] = x;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\mmfvsrwz\M} 4 } } */
|
||||
/* { dg-final { scan-assembler-times {\mstfiwx\M|\mstxsiwx\M} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\mstb\M} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\msth\M} 2 } } */
|
||||
/* { dg-final { scan-assembler-not {\mlbz\M} } } */
|
||||
/* { dg-final { scan-assembler-not {\mlhz\M} } } */
|
||||
/* { dg-final { scan-assembler-not {\mlha\M} } } */
|
||||
/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
|
||||
/* { dg-final { scan-assembler-not {\mstw\M} } } */
|
||||
60
gcc/testsuite/gcc.target/powerpc/pr84154-3.c
Normal file
60
gcc/testsuite/gcc.target/powerpc/pr84154-3.c
Normal file
@ -0,0 +1,60 @@
|
||||
/* { dg-do compile { target { powerpc*-*-* } } } */
|
||||
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
|
||||
/* { dg-require-effective-target powerpc_p9vector_ok } */
|
||||
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
|
||||
/* { dg-options "-mcpu=power9 -O2" } */
|
||||
|
||||
/* PR target/84154. Make sure on ISA 3.0 we store the result of a conversion
|
||||
to char/short using an offsettable address does not generate direct moves
|
||||
for storing 8/16/32-bit integers. */
|
||||
|
||||
void
|
||||
double_to_uc (double x, unsigned char *p)
|
||||
{
|
||||
p[3] = x;
|
||||
}
|
||||
|
||||
void
|
||||
double_to_sc (double x, signed char *p)
|
||||
{
|
||||
p[3] = x;
|
||||
}
|
||||
|
||||
void
|
||||
double_to_us (double x, unsigned short *p)
|
||||
{
|
||||
p[3] = x;
|
||||
}
|
||||
|
||||
void
|
||||
double_to_ss (double x, short *p)
|
||||
{
|
||||
p[3] = x;
|
||||
}
|
||||
|
||||
void
|
||||
double_to_ui (double x, unsigned int *p)
|
||||
{
|
||||
p[3] = x;
|
||||
}
|
||||
|
||||
void
|
||||
double_to_si (double x, int *p)
|
||||
{
|
||||
p[3] = x;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times {\maddi\M} 6 } } */
|
||||
/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\mstfiwx\M|\mstxsiwx\M} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\mstxsibx\M} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\mstxsihx\M} 2 } } */
|
||||
/* { dg-final { scan-assembler-not {\mlbz\M} } } */
|
||||
/* { dg-final { scan-assembler-not {\mlhz\M} } } */
|
||||
/* { dg-final { scan-assembler-not {\mlha\M} } } */
|
||||
/* { dg-final { scan-assembler-not {\mmfvsrwz\M} } } */
|
||||
/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
|
||||
/* { dg-final { scan-assembler-not {\mstw\M} } } */
|
||||
/* { dg-final { scan-assembler-not {\mstb\M} } } */
|
||||
/* { dg-final { scan-assembler-not {\msth\M} } } */
|
||||
Loading…
Reference in New Issue
Block a user