m68k.c (output_scc_di): Fix coding style.
2004-07-24 Roman Zippel <zippel@linux-m68k.org>
* config/m68k/m68k.c (output_scc_di): Fix coding style.
(symbolic_operand): Fix prototype.
* config/m68k/m68k.h (PREDICATE_CODES): Add symbolic_operand.
* config/m68k/m68k.md: Add constants for registers a0 and sp and
use them, change from the "{...}" syntax to the simpler {...}
syntax.
(*cfv4_extendqisi2): Fix destination predicate.
* config/m68k/m68k-protos.h: Remove various declarations also
generated via PREDICATE_CODES.
From-SVN: r85115
This commit is contained in:
Roman Zippel
Andreas Schwab
parent
0c6d842886
commit
428511bbd3
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@ -1,3 +1,15 @@
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2004-07-24 Roman Zippel <zippel@linux-m68k.org>
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* config/m68k/m68k.c (output_scc_di): Fix coding style.
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(symbolic_operand): Fix prototype.
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* config/m68k/m68k.h (PREDICATE_CODES): Add symbolic_operand.
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* config/m68k/m68k.md: Add constants for registers a0 and sp and
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use them, change from the "{...}" syntax to the simpler {...}
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syntax.
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(*cfv4_extendqisi2): Fix destination predicate.
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* config/m68k/m68k-protos.h: Remove various declarations also
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generated via PREDICATE_CODES.
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2004-07-23 Mike Stump <mrs@apple.com>
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* c-typeck.c (convert_for_assignment): Tightened up pointer converstions
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@ -41,24 +41,14 @@ extern const char *output_iorsi3 (rtx *);
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extern const char *output_xorsi3 (rtx *);
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extern void m68k_output_pic_call (rtx dest);
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extern void output_dbcc_and_branch (rtx *);
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extern int const_uint32_operand (rtx, enum machine_mode);
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extern int const_sint32_operand (rtx, enum machine_mode);
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extern int floating_exact_log2 (rtx);
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extern int not_sp_operand (rtx, enum machine_mode);
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extern int valid_dbcc_comparison_p (rtx, enum machine_mode);
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extern int extend_operator (rtx, enum machine_mode);
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extern bool strict_low_part_peephole_ok (enum machine_mode mode, rtx first_insn, rtx target);
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/* Functions from m68k.c used in macros. */
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extern bool symbolic_operand (rtx, enum machine_mode);
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extern int standard_68881_constant_p (rtx);
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extern void print_operand_address (FILE *, rtx);
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extern void print_operand (FILE *, rtx, int);
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extern void notice_update_cc (rtx, rtx);
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extern int general_src_operand (rtx, enum machine_mode);
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extern int nonimmediate_src_operand (rtx, enum machine_mode);
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extern int memory_src_operand (rtx, enum machine_mode);
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extern int pcrel_address (rtx, enum machine_mode);
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extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx);
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#endif /* RTX_CODE */
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@ -1118,7 +1118,7 @@ output_scc_di(rtx op, rtx operand1, rtx operand2, rtx dest)
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else
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loperands[3] = adjust_address (operand2, SImode, 4);
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}
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loperands[4] = gen_label_rtx();
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loperands[4] = gen_label_rtx ();
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if (operand2 != const0_rtx)
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{
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output_asm_insn (MOTOROLA ?
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@ -1160,7 +1160,7 @@ output_scc_di(rtx op, rtx operand1, rtx operand2, rtx dest)
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break;
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case GT:
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loperands[6] = gen_label_rtx();
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loperands[6] = gen_label_rtx ();
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output_asm_insn (MOTOROLA ?
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"shi %5\n\tjbra %l6" :
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"shi %5\n\tjra %l6",
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@ -1179,7 +1179,7 @@ output_scc_di(rtx op, rtx operand1, rtx operand2, rtx dest)
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break;
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case LT:
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loperands[6] = gen_label_rtx();
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loperands[6] = gen_label_rtx ();
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output_asm_insn (MOTOROLA ?
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"scs %5\n\tjbra %l6" :
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"scs %5\n\tjra %l6",
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@ -1198,7 +1198,7 @@ output_scc_di(rtx op, rtx operand1, rtx operand2, rtx dest)
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break;
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case GE:
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loperands[6] = gen_label_rtx();
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loperands[6] = gen_label_rtx ();
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output_asm_insn (MOTOROLA ?
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"scc %5\n\tjbra %l6" :
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"scc %5\n\tjra %l6",
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@ -1217,7 +1217,7 @@ output_scc_di(rtx op, rtx operand1, rtx operand2, rtx dest)
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break;
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case LE:
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loperands[6] = gen_label_rtx();
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loperands[6] = gen_label_rtx ();
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output_asm_insn (MOTOROLA ?
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"sls %5\n\tjbra %l6" :
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"sls %5\n\tjra %l6",
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@ -1283,7 +1283,7 @@ output_btst (rtx *operands, rtx countop, rtx dataop, rtx insn, int signpos)
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/* Returns true if OP is either a symbol reference or a sum of a symbol
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reference and a constant. */
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bool
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int
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symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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{
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switch (GET_CODE (op))
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@ -1270,4 +1270,5 @@ extern int m68k_last_compare_had_fp_operands;
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{"const_sint32_operand", {CONST_INT}}, \
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{"valid_dbcc_comparison_p", {EQ, NE, GTU, LTU, GEU, LEU, \
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GT, LT, GE, LE}}, \
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{"extend_operator", {SIGN_EXTEND, ZERO_EXTEND}},
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{"extend_operator", {SIGN_EXTEND, ZERO_EXTEND}}, \
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{"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}},
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@ -122,6 +122,12 @@
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(define_constants
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[(UNSPECV_BLOCKAGE 0)
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])
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;; Registers by name.
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(define_constants
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[(A0_REG 8)
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(SP_REG 15)
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])
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(define_insn ""
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[(set (match_operand:DF 0 "push_operand" "=m")
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@ -233,10 +239,9 @@
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[(set (cc0)
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(match_operand:SF 0 "general_operand" ""))]
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"TARGET_68881"
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"
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{
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m68k_last_compare_had_fp_operands = 1;
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}")
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})
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(define_insn ""
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[(set (cc0)
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@ -253,10 +258,9 @@
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[(set (cc0)
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(match_operand:DF 0 "general_operand" ""))]
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"TARGET_68881"
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"
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{
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m68k_last_compare_had_fp_operands = 1;
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}")
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})
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(define_insn ""
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[(set (cc0)
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@ -303,7 +307,6 @@
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(compare (match_operand:SI 0 "nonimmediate_operand" "")
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(match_operand:SI 1 "general_operand" "")))]
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""
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"
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{
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m68k_last_compare_had_fp_operands = 0;
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if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
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@ -315,7 +318,7 @@
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rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
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operands[1] = legitimize_pic_address (operands[1], SImode, temp);
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}
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}")
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})
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;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
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(define_insn ""
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@ -408,10 +411,9 @@
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(compare (match_operand:DF 0 "general_operand" "")
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(match_operand:DF 1 "general_operand" "")))]
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"TARGET_68881"
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"
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{
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m68k_last_compare_had_fp_operands = 1;
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}")
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})
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(define_insn ""
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[(set (cc0)
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@ -436,10 +438,9 @@
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(compare (match_operand:SF 0 "general_operand" "")
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(match_operand:SF 1 "general_operand" "")))]
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"TARGET_68881"
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"
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{
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m68k_last_compare_had_fp_operands = 1;
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}")
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})
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(define_insn ""
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[(set (cc0)
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@ -639,7 +640,6 @@
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[(set (match_operand:SI 0 "nonimmediate_operand" "")
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(match_operand:SI 1 "general_operand" ""))]
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""
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"
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{
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if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
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{
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@ -661,7 +661,7 @@
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operands[0] = gen_rtx_MEM (SImode,
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force_reg (SImode, XEXP (operands[0], 0)));
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}
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}")
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})
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;; General case of fullword move. The register constraints
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;; force integer constants in range for a moveq to be reloaded
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@ -774,8 +774,8 @@
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"* return output_move_strictqi (operands);")
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(define_expand "pushqi1"
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[(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int -2)))
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(set (mem:QI (plus:SI (reg:SI 15) (const_int 1)))
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[(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -2)))
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(set (mem:QI (plus:SI (reg:SI SP_REG) (const_int 1)))
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(match_operand:QI 0 "general_operand" ""))]
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"!TARGET_COLDFIRE"
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"")
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@ -899,7 +899,6 @@
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[(set (match_operand:XF 0 "nonimmediate_operand" "")
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(match_operand:XF 1 "general_operand" ""))]
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""
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"
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{
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/* We can't rewrite operands during reload. */
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if (! reload_in_progress)
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@ -920,7 +919,7 @@
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force_reg (SImode, XEXP (operands[0], 0)));
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}
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}
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}")
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})
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(define_insn ""
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[(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r")
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@ -1485,7 +1484,7 @@
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"")
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(define_insn "*cfv4_extendqisi2"
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[(set (match_operand:SI 0 "general_operand" "=d")
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[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
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(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rms")))]
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"TARGET_CFV4"
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"mvs%.b %1,%0")
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@ -2645,7 +2644,6 @@
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(const_int 32))))
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(clobber (match_dup 3))])]
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"TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
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"
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{
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operands[3] = gen_reg_rtx (SImode);
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@ -2659,7 +2657,7 @@
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operands[1], operands[2]));
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DONE;
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}
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}")
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})
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=d")
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@ -2693,7 +2691,6 @@
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(const_int 32))))
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(clobber (match_dup 3))])]
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"TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
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"
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{
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operands[3] = gen_reg_rtx (SImode);
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if (GET_CODE (operands[2]) == CONST_INT)
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@ -2703,7 +2700,7 @@
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operands[1], operands[2]));
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DONE;
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}
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}")
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})
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=d")
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@ -3153,9 +3150,9 @@
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&& GET_CODE (operands[2]) == CONST_INT)
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{
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if (INTVAL (operands[2]) == 0x000000ff)
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return \"mvz%.b %0,%0\";
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return "mvz%.b %0,%0";
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else if (INTVAL (operands[2]) == 0x0000ffff)
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return \"mvz%.w %0,%0\";
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return "mvz%.w %0,%0";
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}
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return output_andsi3 (operands);
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})
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@ -3553,14 +3550,13 @@
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[(set (match_operand:DI 0 "nonimmediate_operand" "")
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(neg:DI (match_operand:DI 1 "general_operand" "")))]
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""
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"
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{
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if (TARGET_COLDFIRE)
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emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
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else
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emit_insn (gen_negdi2_internal (operands[0], operands[1]));
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DONE;
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}")
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})
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(define_insn "negdi2_internal"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a")
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@ -3592,14 +3588,13 @@
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[(set (match_operand:SI 0 "nonimmediate_operand" "")
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(neg:SI (match_operand:SI 1 "general_operand" "")))]
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""
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"
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{
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if (TARGET_COLDFIRE)
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emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
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else
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emit_insn (gen_negsi2_internal (operands[0], operands[1]));
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DONE;
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}")
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})
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(define_insn "negsi2_internal"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
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@ -3643,7 +3638,6 @@
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[(set (match_operand:SF 0 "nonimmediate_operand" "")
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(neg:SF (match_operand:SF 1 "general_operand" "")))]
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""
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"
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{
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if (!TARGET_68881)
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{
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@ -3664,7 +3658,7 @@
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emit_move_insn (operands[0], operands[0]);
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DONE;
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}
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}")
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})
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(define_insn ""
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[(set (match_operand:SF 0 "nonimmediate_operand" "=f,d")
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@ -3685,7 +3679,6 @@
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[(set (match_operand:DF 0 "nonimmediate_operand" "")
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(neg:DF (match_operand:DF 1 "general_operand" "")))]
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""
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"
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{
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if (!TARGET_68881)
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{
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@ -3713,7 +3706,7 @@
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emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
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DONE;
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}
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}")
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})
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(define_insn ""
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[(set (match_operand:DF 0 "nonimmediate_operand" "=f,d")
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@ -3761,7 +3754,6 @@
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[(set (match_operand:SF 0 "nonimmediate_operand" "")
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(abs:SF (match_operand:SF 1 "general_operand" "")))]
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""
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"
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{
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if (!TARGET_68881)
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{
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@ -3782,7 +3774,7 @@
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emit_move_insn (operands[0], operands[0]);
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DONE;
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}
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}")
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})
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|
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(define_insn ""
|
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[(set (match_operand:SF 0 "nonimmediate_operand" "=f")
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|
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@ -3798,7 +3790,6 @@
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[(set (match_operand:DF 0 "nonimmediate_operand" "")
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(abs:DF (match_operand:DF 1 "general_operand" "")))]
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""
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"
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{
|
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if (!TARGET_68881)
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{
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@ -3826,7 +3817,7 @@
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emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
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DONE;
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}
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}")
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})
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|
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(define_insn ""
|
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[(set (match_operand:DF 0 "nonimmediate_operand" "=f")
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@ -3861,14 +3852,13 @@
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[(set (match_operand:SI 0 "nonimmediate_operand" "")
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(not:SI (match_operand:SI 1 "general_operand" "")))]
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""
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"
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{
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if (TARGET_COLDFIRE)
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emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
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else
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emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
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DONE;
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||||
}")
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})
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(define_insn "one_cmplsi2_internal"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
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|
|
@ -5059,14 +5049,13 @@
|
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[(set (match_operand:QI 0 "register_operand" "")
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(eq:QI (cc0) (const_int 0)))]
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""
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||||
"
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||||
{
|
||||
if (TARGET_68060 && m68k_last_compare_had_fp_operands)
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{
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m68k_last_compare_had_fp_operands = 0;
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FAIL;
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}
|
||||
}")
|
||||
})
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:QI 0 "register_operand" "=d")
|
||||
|
|
@ -5081,14 +5070,13 @@
|
|||
[(set (match_operand:QI 0 "register_operand" "")
|
||||
(ne:QI (cc0) (const_int 0)))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (TARGET_68060 && m68k_last_compare_had_fp_operands)
|
||||
{
|
||||
m68k_last_compare_had_fp_operands = 0;
|
||||
FAIL;
|
||||
}
|
||||
}")
|
||||
})
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:QI 0 "register_operand" "=d")
|
||||
|
|
@ -5103,14 +5091,13 @@
|
|||
[(set (match_operand:QI 0 "register_operand" "")
|
||||
(gt:QI (cc0) (const_int 0)))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (TARGET_68060 && m68k_last_compare_had_fp_operands)
|
||||
{
|
||||
m68k_last_compare_had_fp_operands = 0;
|
||||
FAIL;
|
||||
}
|
||||
}")
|
||||
})
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:QI 0 "register_operand" "=d")
|
||||
|
|
@ -5140,14 +5127,13 @@
|
|||
[(set (match_operand:QI 0 "register_operand" "")
|
||||
(lt:QI (cc0) (const_int 0)))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (TARGET_68060 && m68k_last_compare_had_fp_operands)
|
||||
{
|
||||
m68k_last_compare_had_fp_operands = 0;
|
||||
FAIL;
|
||||
}
|
||||
}")
|
||||
})
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:QI 0 "register_operand" "=d")
|
||||
|
|
@ -5177,14 +5163,13 @@
|
|||
[(set (match_operand:QI 0 "register_operand" "")
|
||||
(ge:QI (cc0) (const_int 0)))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (TARGET_68060 && m68k_last_compare_had_fp_operands)
|
||||
{
|
||||
m68k_last_compare_had_fp_operands = 0;
|
||||
FAIL;
|
||||
}
|
||||
}")
|
||||
})
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:QI 0 "register_operand" "=d")
|
||||
|
|
@ -5214,14 +5199,13 @@
|
|||
[(set (match_operand:QI 0 "register_operand" "")
|
||||
(le:QI (cc0) (const_int 0)))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (TARGET_68060 && m68k_last_compare_had_fp_operands)
|
||||
{
|
||||
m68k_last_compare_had_fp_operands = 0;
|
||||
FAIL;
|
||||
}
|
||||
}")
|
||||
})
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:QI 0 "register_operand" "=d")
|
||||
|
|
@ -6092,13 +6076,12 @@
|
|||
[(parallel [(set (pc) (match_operand 0 "" ""))
|
||||
(use (label_ref (match_operand 1 "" "")))])]
|
||||
""
|
||||
"
|
||||
{
|
||||
#ifdef CASE_VECTOR_PC_RELATIVE
|
||||
operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
|
||||
gen_rtx_SIGN_EXTEND (SImode, operands[0]));
|
||||
#endif
|
||||
}")
|
||||
})
|
||||
|
||||
;; Jump to variable address from dispatch table of absolute addresses.
|
||||
(define_insn ""
|
||||
|
|
@ -6298,11 +6281,10 @@
|
|||
;; Operand 1 not really used on the m68000.
|
||||
|
||||
""
|
||||
"
|
||||
{
|
||||
if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
|
||||
SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
|
||||
}")
|
||||
})
|
||||
|
||||
;; This is a normal call sequence.
|
||||
(define_insn ""
|
||||
|
|
@ -6340,11 +6322,10 @@
|
|||
(match_operand:SI 2 "general_operand" "")))]
|
||||
;; Operand 2 not really used on the m68000.
|
||||
""
|
||||
"
|
||||
{
|
||||
if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
|
||||
SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
|
||||
}")
|
||||
})
|
||||
|
||||
;; This is a normal call_value
|
||||
(define_insn ""
|
||||
|
|
@ -6381,7 +6362,6 @@
|
|||
(match_operand 1 "" "")
|
||||
(match_operand 2 "" "")])]
|
||||
"NEEDS_UNTYPED_CALL"
|
||||
"
|
||||
{
|
||||
int i;
|
||||
|
||||
|
|
@ -6400,7 +6380,7 @@
|
|||
emit_insn (gen_blockage ());
|
||||
|
||||
DONE;
|
||||
}")
|
||||
})
|
||||
|
||||
;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
|
||||
;; all of memory. This blocks insns from being moved across this point.
|
||||
|
|
@ -6464,7 +6444,7 @@
|
|||
;; But it is mainly intended to test the support for these optimizations.
|
||||
|
||||
(define_peephole
|
||||
[(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
|
||||
[(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
|
||||
(set (match_operand:DF 0 "register_operand" "=f")
|
||||
(match_operand:DF 1 "register_operand" "ad"))]
|
||||
"FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
|
||||
|
|
@ -6481,8 +6461,8 @@
|
|||
;; when there are consecutive library calls.
|
||||
|
||||
(define_peephole
|
||||
[(set (reg:SI 15) (plus:SI (reg:SI 15)
|
||||
(match_operand:SI 0 "const_int_operand" "n")))
|
||||
[(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
|
||||
(match_operand:SI 0 "const_int_operand" "n")))
|
||||
(set (match_operand:SF 1 "push_operand" "=m")
|
||||
(match_operand:SF 2 "general_operand" "rmfF"))]
|
||||
"INTVAL (operands[0]) >= 4
|
||||
|
|
@ -6525,8 +6505,8 @@
|
|||
;; Speed up stack adjust followed by a fullword fixedpoint push.
|
||||
|
||||
(define_peephole
|
||||
[(set (reg:SI 15) (plus:SI (reg:SI 15)
|
||||
(match_operand:SI 0 "const_int_operand" "n")))
|
||||
[(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
|
||||
(match_operand:SI 0 "const_int_operand" "n")))
|
||||
(set (match_operand:SI 1 "push_operand" "=m")
|
||||
(match_operand:SI 2 "general_operand" "g"))]
|
||||
"INTVAL (operands[0]) >= 4
|
||||
|
|
@ -6569,9 +6549,9 @@
|
|||
;; Speed up pushing a single byte but leaving four bytes of space.
|
||||
|
||||
(define_peephole
|
||||
[(set (mem:QI (pre_dec:SI (reg:SI 15)))
|
||||
[(set (mem:QI (pre_dec:SI (reg:SI SP_REG)))
|
||||
(match_operand:QI 1 "general_operand" "dami"))
|
||||
(set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
|
||||
(set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (const_int 2)))]
|
||||
"! reg_mentioned_p (stack_pointer_rtx, operands[1])"
|
||||
{
|
||||
rtx xoperands[4];
|
||||
|
|
@ -7026,7 +7006,6 @@
|
|||
[(set (match_operand:XF 0 "nonimmediate_operand" "")
|
||||
(neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (!TARGET_68881)
|
||||
{
|
||||
|
|
@ -7056,7 +7035,7 @@
|
|||
emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
|
||||
DONE;
|
||||
}
|
||||
}")
|
||||
})
|
||||
|
||||
(define_insn "negxf2_68881"
|
||||
[(set (match_operand:XF 0 "nonimmediate_operand" "=f")
|
||||
|
|
@ -7072,7 +7051,6 @@
|
|||
[(set (match_operand:XF 0 "nonimmediate_operand" "")
|
||||
(abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (!TARGET_68881)
|
||||
{
|
||||
|
|
@ -7102,7 +7080,7 @@
|
|||
emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
|
||||
DONE;
|
||||
}
|
||||
}")
|
||||
})
|
||||
|
||||
(define_insn "absxf2_68881"
|
||||
[(set (match_operand:XF 0 "nonimmediate_operand" "=f")
|
||||
|
|
|
|||
Loading…
Reference in New Issue