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m68k.c (output_scc_di): Fix coding style. 

2004-07-24  Roman Zippel  <zippel@linux-m68k.org>

	* config/m68k/m68k.c (output_scc_di): Fix coding style.
	(symbolic_operand): Fix prototype.
	* config/m68k/m68k.h (PREDICATE_CODES): Add symbolic_operand.
	* config/m68k/m68k.md: Add constants for registers a0 and sp and
	use them, change from the "{...}" syntax to the simpler {...}
	syntax.
	(*cfv4_extendqisi2): Fix destination predicate.
	* config/m68k/m68k-protos.h: Remove various declarations also
	generated via PREDICATE_CODES.

From-SVN: r85115
This commit is contained in:
Roman Zippel 2004-07-24 11:12:29 +00:00 committed by Andreas Schwab
parent 0c6d842886
commit 428511bbd3
5 changed files with 66 additions and 85 deletions
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12
gcc/ChangeLog
View File

@ -1,3 +1,15 @@
2004-07-24 Roman Zippel <zippel@linux-m68k.org>
* config/m68k/m68k.c (output_scc_di): Fix coding style.
(symbolic_operand): Fix prototype.
* config/m68k/m68k.h (PREDICATE_CODES): Add symbolic_operand.
* config/m68k/m68k.md: Add constants for registers a0 and sp and
use them, change from the "{...}" syntax to the simpler {...}
syntax.
(*cfv4_extendqisi2): Fix destination predicate.
* config/m68k/m68k-protos.h: Remove various declarations also
generated via PREDICATE_CODES.
2004-07-23 Mike Stump <mrs@apple.com> 2004-07-23 Mike Stump <mrs@apple.com>
* c-typeck.c (convert_for_assignment): Tightened up pointer converstions * c-typeck.c (convert_for_assignment): Tightened up pointer converstions

10
gcc/config/m68k/m68k-protos.h
View File

@ -41,24 +41,14 @@ extern const char *output_iorsi3 (rtx *);
extern const char *output_xorsi3 (rtx *); extern const char *output_xorsi3 (rtx *);
extern void m68k_output_pic_call (rtx dest); extern void m68k_output_pic_call (rtx dest);
extern void output_dbcc_and_branch (rtx *); extern void output_dbcc_and_branch (rtx *);
extern int const_uint32_operand (rtx, enum machine_mode);
extern int const_sint32_operand (rtx, enum machine_mode);
extern int floating_exact_log2 (rtx); extern int floating_exact_log2 (rtx);
extern int not_sp_operand (rtx, enum machine_mode);
extern int valid_dbcc_comparison_p (rtx, enum machine_mode);
extern int extend_operator (rtx, enum machine_mode);
extern bool strict_low_part_peephole_ok (enum machine_mode mode, rtx first_insn, rtx target); extern bool strict_low_part_peephole_ok (enum machine_mode mode, rtx first_insn, rtx target);
/* Functions from m68k.c used in macros. */ /* Functions from m68k.c used in macros. */
extern bool symbolic_operand (rtx, enum machine_mode);
extern int standard_68881_constant_p (rtx); extern int standard_68881_constant_p (rtx);
extern void print_operand_address (FILE *, rtx); extern void print_operand_address (FILE *, rtx);
extern void print_operand (FILE *, rtx, int); extern void print_operand (FILE *, rtx, int);
extern void notice_update_cc (rtx, rtx); extern void notice_update_cc (rtx, rtx);
extern int general_src_operand (rtx, enum machine_mode);
extern int nonimmediate_src_operand (rtx, enum machine_mode);
extern int memory_src_operand (rtx, enum machine_mode);
extern int pcrel_address (rtx, enum machine_mode);
extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx); extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx);
#endif /* RTX_CODE */ #endif /* RTX_CODE */

12
gcc/config/m68k/m68k.c
View File

@ -1118,7 +1118,7 @@ output_scc_di(rtx op, rtx operand1, rtx operand2, rtx dest)
else else
loperands[3] = adjust_address (operand2, SImode, 4); loperands[3] = adjust_address (operand2, SImode, 4);
} }
loperands[4] = gen_label_rtx(); loperands[4] = gen_label_rtx ();
if (operand2 != const0_rtx) if (operand2 != const0_rtx)
{ {
output_asm_insn (MOTOROLA ? output_asm_insn (MOTOROLA ?
@ -1160,7 +1160,7 @@ output_scc_di(rtx op, rtx operand1, rtx operand2, rtx dest)
break; break;
case GT: case GT:
loperands[6] = gen_label_rtx(); loperands[6] = gen_label_rtx ();
output_asm_insn (MOTOROLA ? output_asm_insn (MOTOROLA ?
"shi %5\n\tjbra %l6" : "shi %5\n\tjbra %l6" :
"shi %5\n\tjra %l6", "shi %5\n\tjra %l6",
@ -1179,7 +1179,7 @@ output_scc_di(rtx op, rtx operand1, rtx operand2, rtx dest)
break; break;
case LT: case LT:
loperands[6] = gen_label_rtx(); loperands[6] = gen_label_rtx ();
output_asm_insn (MOTOROLA ? output_asm_insn (MOTOROLA ?
"scs %5\n\tjbra %l6" : "scs %5\n\tjbra %l6" :
"scs %5\n\tjra %l6", "scs %5\n\tjra %l6",
@ -1198,7 +1198,7 @@ output_scc_di(rtx op, rtx operand1, rtx operand2, rtx dest)
break; break;
case GE: case GE:
loperands[6] = gen_label_rtx(); loperands[6] = gen_label_rtx ();
output_asm_insn (MOTOROLA ? output_asm_insn (MOTOROLA ?
"scc %5\n\tjbra %l6" : "scc %5\n\tjbra %l6" :
"scc %5\n\tjra %l6", "scc %5\n\tjra %l6",
@ -1217,7 +1217,7 @@ output_scc_di(rtx op, rtx operand1, rtx operand2, rtx dest)
break; break;
case LE: case LE:
loperands[6] = gen_label_rtx(); loperands[6] = gen_label_rtx ();
output_asm_insn (MOTOROLA ? output_asm_insn (MOTOROLA ?
"sls %5\n\tjbra %l6" : "sls %5\n\tjbra %l6" :
"sls %5\n\tjra %l6", "sls %5\n\tjra %l6",
@ -1283,7 +1283,7 @@ output_btst (rtx *operands, rtx countop, rtx dataop, rtx insn, int signpos)
/* Returns true if OP is either a symbol reference or a sum of a symbol /* Returns true if OP is either a symbol reference or a sum of a symbol
reference and a constant. */ reference and a constant. */
bool int
symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{ {
switch (GET_CODE (op)) switch (GET_CODE (op))

3
gcc/config/m68k/m68k.h
View File

@ -1270,4 +1270,5 @@ extern int m68k_last_compare_had_fp_operands;
{"const_sint32_operand", {CONST_INT}}, \ {"const_sint32_operand", {CONST_INT}}, \
{"valid_dbcc_comparison_p", {EQ, NE, GTU, LTU, GEU, LEU, \ {"valid_dbcc_comparison_p", {EQ, NE, GTU, LTU, GEU, LEU, \
GT, LT, GE, LE}}, \ GT, LT, GE, LE}}, \
{"extend_operator", {SIGN_EXTEND, ZERO_EXTEND}}, {"extend_operator", {SIGN_EXTEND, ZERO_EXTEND}}, \
{"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}},

114
gcc/config/m68k/m68k.md
View File

@ -122,6 +122,12 @@
(define_constants (define_constants
[(UNSPECV_BLOCKAGE 0) [(UNSPECV_BLOCKAGE 0)
]) ])
;; Registers by name.
(define_constants
[(A0_REG 8)
(SP_REG 15)
])
(define_insn "" (define_insn ""
[(set (match_operand:DF 0 "push_operand" "=m") [(set (match_operand:DF 0 "push_operand" "=m")
@ -233,10 +239,9 @@
[(set (cc0) [(set (cc0)
(match_operand:SF 0 "general_operand" ""))] (match_operand:SF 0 "general_operand" ""))]
"TARGET_68881" "TARGET_68881"
"
{ {
m68k_last_compare_had_fp_operands = 1; m68k_last_compare_had_fp_operands = 1;
}") })
(define_insn "" (define_insn ""
[(set (cc0) [(set (cc0)
@ -253,10 +258,9 @@
[(set (cc0) [(set (cc0)
(match_operand:DF 0 "general_operand" ""))] (match_operand:DF 0 "general_operand" ""))]
"TARGET_68881" "TARGET_68881"
"
{ {
m68k_last_compare_had_fp_operands = 1; m68k_last_compare_had_fp_operands = 1;
}") })
(define_insn "" (define_insn ""
[(set (cc0) [(set (cc0)
@ -303,7 +307,6 @@
(compare (match_operand:SI 0 "nonimmediate_operand" "") (compare (match_operand:SI 0 "nonimmediate_operand" "")
(match_operand:SI 1 "general_operand" "")))] (match_operand:SI 1 "general_operand" "")))]
"" ""
"
{ {
m68k_last_compare_had_fp_operands = 0; m68k_last_compare_had_fp_operands = 0;
if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode)) if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
@ -315,7 +318,7 @@
rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
operands[1] = legitimize_pic_address (operands[1], SImode, temp); operands[1] = legitimize_pic_address (operands[1], SImode, temp);
} }
}") })
;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes. ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
(define_insn "" (define_insn ""
@ -408,10 +411,9 @@
(compare (match_operand:DF 0 "general_operand" "") (compare (match_operand:DF 0 "general_operand" "")
(match_operand:DF 1 "general_operand" "")))] (match_operand:DF 1 "general_operand" "")))]
"TARGET_68881" "TARGET_68881"
"
{ {
m68k_last_compare_had_fp_operands = 1; m68k_last_compare_had_fp_operands = 1;
}") })
(define_insn "" (define_insn ""
[(set (cc0) [(set (cc0)
@ -436,10 +438,9 @@
(compare (match_operand:SF 0 "general_operand" "") (compare (match_operand:SF 0 "general_operand" "")
(match_operand:SF 1 "general_operand" "")))] (match_operand:SF 1 "general_operand" "")))]
"TARGET_68881" "TARGET_68881"
"
{ {
m68k_last_compare_had_fp_operands = 1; m68k_last_compare_had_fp_operands = 1;
}") })
(define_insn "" (define_insn ""
[(set (cc0) [(set (cc0)
@ -639,7 +640,6 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "") [(set (match_operand:SI 0 "nonimmediate_operand" "")
(match_operand:SI 1 "general_operand" ""))] (match_operand:SI 1 "general_operand" ""))]
"" ""
"
{ {
if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode)) if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
{ {
@ -661,7 +661,7 @@
operands[0] = gen_rtx_MEM (SImode, operands[0] = gen_rtx_MEM (SImode,
force_reg (SImode, XEXP (operands[0], 0))); force_reg (SImode, XEXP (operands[0], 0)));
} }
}") })
;; General case of fullword move. The register constraints ;; General case of fullword move. The register constraints
;; force integer constants in range for a moveq to be reloaded ;; force integer constants in range for a moveq to be reloaded
@ -774,8 +774,8 @@
"* return output_move_strictqi (operands);") "* return output_move_strictqi (operands);")
(define_expand "pushqi1" (define_expand "pushqi1"
[(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int -2))) [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -2)))
(set (mem:QI (plus:SI (reg:SI 15) (const_int 1))) (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int 1)))
(match_operand:QI 0 "general_operand" ""))] (match_operand:QI 0 "general_operand" ""))]
"!TARGET_COLDFIRE" "!TARGET_COLDFIRE"
"") "")
@ -899,7 +899,6 @@
[(set (match_operand:XF 0 "nonimmediate_operand" "") [(set (match_operand:XF 0 "nonimmediate_operand" "")
(match_operand:XF 1 "general_operand" ""))] (match_operand:XF 1 "general_operand" ""))]
"" ""
"
{ {
/* We can't rewrite operands during reload. */ /* We can't rewrite operands during reload. */
if (! reload_in_progress) if (! reload_in_progress)
@ -920,7 +919,7 @@
force_reg (SImode, XEXP (operands[0], 0))); force_reg (SImode, XEXP (operands[0], 0)));
} }
} }
}") })
(define_insn "" (define_insn ""
[(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r") [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r")
@ -1485,7 +1484,7 @@
"") "")
(define_insn "*cfv4_extendqisi2" (define_insn "*cfv4_extendqisi2"
[(set (match_operand:SI 0 "general_operand" "=d") [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rms")))] (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rms")))]
"TARGET_CFV4" "TARGET_CFV4"
"mvs%.b %1,%0") "mvs%.b %1,%0")
@ -2645,7 +2644,6 @@
(const_int 32)))) (const_int 32))))
(clobber (match_dup 3))])] (clobber (match_dup 3))])]
"TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
"
{ {
operands[3] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);
@ -2659,7 +2657,7 @@
operands[1], operands[2])); operands[1], operands[2]));
DONE; DONE;
} }
}") })
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
@ -2693,7 +2691,6 @@
(const_int 32)))) (const_int 32))))
(clobber (match_dup 3))])] (clobber (match_dup 3))])]
"TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
"
{ {
operands[3] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);
if (GET_CODE (operands[2]) == CONST_INT) if (GET_CODE (operands[2]) == CONST_INT)
@ -2703,7 +2700,7 @@
operands[1], operands[2])); operands[1], operands[2]));
DONE; DONE;
} }
}") })
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
@ -3153,9 +3150,9 @@
&& GET_CODE (operands[2]) == CONST_INT) && GET_CODE (operands[2]) == CONST_INT)
{ {
if (INTVAL (operands[2]) == 0x000000ff) if (INTVAL (operands[2]) == 0x000000ff)
return \"mvz%.b %0,%0\"; return "mvz%.b %0,%0";
else if (INTVAL (operands[2]) == 0x0000ffff) else if (INTVAL (operands[2]) == 0x0000ffff)
return \"mvz%.w %0,%0\"; return "mvz%.w %0,%0";
} }
return output_andsi3 (operands); return output_andsi3 (operands);
}) })
@ -3553,14 +3550,13 @@
[(set (match_operand:DI 0 "nonimmediate_operand" "") [(set (match_operand:DI 0 "nonimmediate_operand" "")
(neg:DI (match_operand:DI 1 "general_operand" "")))] (neg:DI (match_operand:DI 1 "general_operand" "")))]
"" ""
"
{ {
if (TARGET_COLDFIRE) if (TARGET_COLDFIRE)
emit_insn (gen_negdi2_5200 (operands[0], operands[1])); emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
else else
emit_insn (gen_negdi2_internal (operands[0], operands[1])); emit_insn (gen_negdi2_internal (operands[0], operands[1]));
DONE; DONE;
}") })
(define_insn "negdi2_internal" (define_insn "negdi2_internal"
[(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a") [(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a")
@ -3592,14 +3588,13 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "") [(set (match_operand:SI 0 "nonimmediate_operand" "")
(neg:SI (match_operand:SI 1 "general_operand" "")))] (neg:SI (match_operand:SI 1 "general_operand" "")))]
"" ""
"
{ {
if (TARGET_COLDFIRE) if (TARGET_COLDFIRE)
emit_insn (gen_negsi2_5200 (operands[0], operands[1])); emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
else else
emit_insn (gen_negsi2_internal (operands[0], operands[1])); emit_insn (gen_negsi2_internal (operands[0], operands[1]));
DONE; DONE;
}") })
(define_insn "negsi2_internal" (define_insn "negsi2_internal"
[(set (match_operand:SI 0 "nonimmediate_operand" "=dm") [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
@ -3643,7 +3638,6 @@
[(set (match_operand:SF 0 "nonimmediate_operand" "") [(set (match_operand:SF 0 "nonimmediate_operand" "")
(neg:SF (match_operand:SF 1 "general_operand" "")))] (neg:SF (match_operand:SF 1 "general_operand" "")))]
"" ""
"
{ {
if (!TARGET_68881) if (!TARGET_68881)
{ {
@ -3664,7 +3658,7 @@
emit_move_insn (operands[0], operands[0]); emit_move_insn (operands[0], operands[0]);
DONE; DONE;
} }
}") })
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,d") [(set (match_operand:SF 0 "nonimmediate_operand" "=f,d")
@ -3685,7 +3679,6 @@
[(set (match_operand:DF 0 "nonimmediate_operand" "") [(set (match_operand:DF 0 "nonimmediate_operand" "")
(neg:DF (match_operand:DF 1 "general_operand" "")))] (neg:DF (match_operand:DF 1 "general_operand" "")))]
"" ""
"
{ {
if (!TARGET_68881) if (!TARGET_68881)
{ {
@ -3713,7 +3706,7 @@
emit_no_conflict_block (insns, operands[0], operands[1], 0, 0); emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
DONE; DONE;
} }
}") })
(define_insn "" (define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,d") [(set (match_operand:DF 0 "nonimmediate_operand" "=f,d")
@ -3761,7 +3754,6 @@
[(set (match_operand:SF 0 "nonimmediate_operand" "") [(set (match_operand:SF 0 "nonimmediate_operand" "")
(abs:SF (match_operand:SF 1 "general_operand" "")))] (abs:SF (match_operand:SF 1 "general_operand" "")))]
"" ""
"
{ {
if (!TARGET_68881) if (!TARGET_68881)
{ {
@ -3782,7 +3774,7 @@
emit_move_insn (operands[0], operands[0]); emit_move_insn (operands[0], operands[0]);
DONE; DONE;
} }
}") })
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=f") [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
@ -3798,7 +3790,6 @@
[(set (match_operand:DF 0 "nonimmediate_operand" "") [(set (match_operand:DF 0 "nonimmediate_operand" "")
(abs:DF (match_operand:DF 1 "general_operand" "")))] (abs:DF (match_operand:DF 1 "general_operand" "")))]
"" ""
"
{ {
if (!TARGET_68881) if (!TARGET_68881)
{ {
@ -3826,7 +3817,7 @@
emit_no_conflict_block (insns, operands[0], operands[1], 0, 0); emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
DONE; DONE;
} }
}") })
(define_insn "" (define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=f") [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
@ -3861,14 +3852,13 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "") [(set (match_operand:SI 0 "nonimmediate_operand" "")
(not:SI (match_operand:SI 1 "general_operand" "")))] (not:SI (match_operand:SI 1 "general_operand" "")))]
"" ""
"
{ {
if (TARGET_COLDFIRE) if (TARGET_COLDFIRE)
emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1])); emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
else else
emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1])); emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
DONE; DONE;
}") })
(define_insn "one_cmplsi2_internal" (define_insn "one_cmplsi2_internal"
[(set (match_operand:SI 0 "nonimmediate_operand" "=dm") [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
@ -5059,14 +5049,13 @@
[(set (match_operand:QI 0 "register_operand" "") [(set (match_operand:QI 0 "register_operand" "")
(eq:QI (cc0) (const_int 0)))] (eq:QI (cc0) (const_int 0)))]
"" ""
"
{ {
if (TARGET_68060 && m68k_last_compare_had_fp_operands) if (TARGET_68060 && m68k_last_compare_had_fp_operands)
{ {
m68k_last_compare_had_fp_operands = 0; m68k_last_compare_had_fp_operands = 0;
FAIL; FAIL;
} }
}") })
(define_insn "" (define_insn ""
[(set (match_operand:QI 0 "register_operand" "=d") [(set (match_operand:QI 0 "register_operand" "=d")
@ -5081,14 +5070,13 @@
[(set (match_operand:QI 0 "register_operand" "") [(set (match_operand:QI 0 "register_operand" "")
(ne:QI (cc0) (const_int 0)))] (ne:QI (cc0) (const_int 0)))]
"" ""
"
{ {
if (TARGET_68060 && m68k_last_compare_had_fp_operands) if (TARGET_68060 && m68k_last_compare_had_fp_operands)
{ {
m68k_last_compare_had_fp_operands = 0; m68k_last_compare_had_fp_operands = 0;
FAIL; FAIL;
} }
}") })
(define_insn "" (define_insn ""
[(set (match_operand:QI 0 "register_operand" "=d") [(set (match_operand:QI 0 "register_operand" "=d")
@ -5103,14 +5091,13 @@
[(set (match_operand:QI 0 "register_operand" "") [(set (match_operand:QI 0 "register_operand" "")
(gt:QI (cc0) (const_int 0)))] (gt:QI (cc0) (const_int 0)))]
"" ""
"
{ {
if (TARGET_68060 && m68k_last_compare_had_fp_operands) if (TARGET_68060 && m68k_last_compare_had_fp_operands)
{ {
m68k_last_compare_had_fp_operands = 0; m68k_last_compare_had_fp_operands = 0;
FAIL; FAIL;
} }
}") })
(define_insn "" (define_insn ""
[(set (match_operand:QI 0 "register_operand" "=d") [(set (match_operand:QI 0 "register_operand" "=d")
@ -5140,14 +5127,13 @@
[(set (match_operand:QI 0 "register_operand" "") [(set (match_operand:QI 0 "register_operand" "")
(lt:QI (cc0) (const_int 0)))] (lt:QI (cc0) (const_int 0)))]
"" ""
"
{ {
if (TARGET_68060 && m68k_last_compare_had_fp_operands) if (TARGET_68060 && m68k_last_compare_had_fp_operands)
{ {
m68k_last_compare_had_fp_operands = 0; m68k_last_compare_had_fp_operands = 0;
FAIL; FAIL;
} }
}") })
(define_insn "" (define_insn ""
[(set (match_operand:QI 0 "register_operand" "=d") [(set (match_operand:QI 0 "register_operand" "=d")
@ -5177,14 +5163,13 @@
[(set (match_operand:QI 0 "register_operand" "") [(set (match_operand:QI 0 "register_operand" "")
(ge:QI (cc0) (const_int 0)))] (ge:QI (cc0) (const_int 0)))]
"" ""
"
{ {
if (TARGET_68060 && m68k_last_compare_had_fp_operands) if (TARGET_68060 && m68k_last_compare_had_fp_operands)
{ {
m68k_last_compare_had_fp_operands = 0; m68k_last_compare_had_fp_operands = 0;
FAIL; FAIL;
} }
}") })
(define_insn "" (define_insn ""
[(set (match_operand:QI 0 "register_operand" "=d") [(set (match_operand:QI 0 "register_operand" "=d")
@ -5214,14 +5199,13 @@
[(set (match_operand:QI 0 "register_operand" "") [(set (match_operand:QI 0 "register_operand" "")
(le:QI (cc0) (const_int 0)))] (le:QI (cc0) (const_int 0)))]
"" ""
"
{ {
if (TARGET_68060 && m68k_last_compare_had_fp_operands) if (TARGET_68060 && m68k_last_compare_had_fp_operands)
{ {
m68k_last_compare_had_fp_operands = 0; m68k_last_compare_had_fp_operands = 0;
FAIL; FAIL;
} }
}") })
(define_insn "" (define_insn ""
[(set (match_operand:QI 0 "register_operand" "=d") [(set (match_operand:QI 0 "register_operand" "=d")
@ -6092,13 +6076,12 @@
[(parallel [(set (pc) (match_operand 0 "" "")) [(parallel [(set (pc) (match_operand 0 "" ""))
(use (label_ref (match_operand 1 "" "")))])] (use (label_ref (match_operand 1 "" "")))])]
"" ""
"
{ {
#ifdef CASE_VECTOR_PC_RELATIVE #ifdef CASE_VECTOR_PC_RELATIVE
operands[0] = gen_rtx_PLUS (SImode, pc_rtx, operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
gen_rtx_SIGN_EXTEND (SImode, operands[0])); gen_rtx_SIGN_EXTEND (SImode, operands[0]));
#endif #endif
}") })
;; Jump to variable address from dispatch table of absolute addresses. ;; Jump to variable address from dispatch table of absolute addresses.
(define_insn "" (define_insn ""
@ -6298,11 +6281,10 @@
;; Operand 1 not really used on the m68000. ;; Operand 1 not really used on the m68000.
"" ""
"
{ {
if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1; SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
}") })
;; This is a normal call sequence. ;; This is a normal call sequence.
(define_insn "" (define_insn ""
@ -6340,11 +6322,10 @@
(match_operand:SI 2 "general_operand" "")))] (match_operand:SI 2 "general_operand" "")))]
;; Operand 2 not really used on the m68000. ;; Operand 2 not really used on the m68000.
"" ""
"
{ {
if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1; SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
}") })
;; This is a normal call_value ;; This is a normal call_value
(define_insn "" (define_insn ""
@ -6381,7 +6362,6 @@
(match_operand 1 "" "") (match_operand 1 "" "")
(match_operand 2 "" "")])] (match_operand 2 "" "")])]
"NEEDS_UNTYPED_CALL" "NEEDS_UNTYPED_CALL"
"
{ {
int i; int i;
@ -6400,7 +6380,7 @@
emit_insn (gen_blockage ()); emit_insn (gen_blockage ());
DONE; DONE;
}") })
;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
;; all of memory. This blocks insns from being moved across this point. ;; all of memory. This blocks insns from being moved across this point.
@ -6464,7 +6444,7 @@
;; But it is mainly intended to test the support for these optimizations. ;; But it is mainly intended to test the support for these optimizations.
(define_peephole (define_peephole
[(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4))) [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
(set (match_operand:DF 0 "register_operand" "=f") (set (match_operand:DF 0 "register_operand" "=f")
(match_operand:DF 1 "register_operand" "ad"))] (match_operand:DF 1 "register_operand" "ad"))]
"FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])" "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
@ -6481,8 +6461,8 @@
;; when there are consecutive library calls. ;; when there are consecutive library calls.
(define_peephole (define_peephole
[(set (reg:SI 15) (plus:SI (reg:SI 15) [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
(match_operand:SI 0 "const_int_operand" "n"))) (match_operand:SI 0 "const_int_operand" "n")))
(set (match_operand:SF 1 "push_operand" "=m") (set (match_operand:SF 1 "push_operand" "=m")
(match_operand:SF 2 "general_operand" "rmfF"))] (match_operand:SF 2 "general_operand" "rmfF"))]
"INTVAL (operands[0]) >= 4 "INTVAL (operands[0]) >= 4
@ -6525,8 +6505,8 @@
;; Speed up stack adjust followed by a fullword fixedpoint push. ;; Speed up stack adjust followed by a fullword fixedpoint push.
(define_peephole (define_peephole
[(set (reg:SI 15) (plus:SI (reg:SI 15) [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
(match_operand:SI 0 "const_int_operand" "n"))) (match_operand:SI 0 "const_int_operand" "n")))
(set (match_operand:SI 1 "push_operand" "=m") (set (match_operand:SI 1 "push_operand" "=m")
(match_operand:SI 2 "general_operand" "g"))] (match_operand:SI 2 "general_operand" "g"))]
"INTVAL (operands[0]) >= 4 "INTVAL (operands[0]) >= 4
@ -6569,9 +6549,9 @@
;; Speed up pushing a single byte but leaving four bytes of space. ;; Speed up pushing a single byte but leaving four bytes of space.
(define_peephole (define_peephole
[(set (mem:QI (pre_dec:SI (reg:SI 15))) [(set (mem:QI (pre_dec:SI (reg:SI SP_REG)))
(match_operand:QI 1 "general_operand" "dami")) (match_operand:QI 1 "general_operand" "dami"))
(set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))] (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (const_int 2)))]
"! reg_mentioned_p (stack_pointer_rtx, operands[1])" "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
{ {
rtx xoperands[4]; rtx xoperands[4];
@ -7026,7 +7006,6 @@
[(set (match_operand:XF 0 "nonimmediate_operand" "") [(set (match_operand:XF 0 "nonimmediate_operand" "")
(neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))] (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
"" ""
"
{ {
if (!TARGET_68881) if (!TARGET_68881)
{ {
@ -7056,7 +7035,7 @@
emit_no_conflict_block (insns, operands[0], operands[1], 0, 0); emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
DONE; DONE;
} }
}") })
(define_insn "negxf2_68881" (define_insn "negxf2_68881"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f") [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
@ -7072,7 +7051,6 @@
[(set (match_operand:XF 0 "nonimmediate_operand" "") [(set (match_operand:XF 0 "nonimmediate_operand" "")
(abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))] (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
"" ""
"
{ {
if (!TARGET_68881) if (!TARGET_68881)
{ {
@ -7102,7 +7080,7 @@
emit_no_conflict_block (insns, operands[0], operands[1], 0, 0); emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
DONE; DONE;
} }
}") })
(define_insn "absxf2_68881" (define_insn "absxf2_68881"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f") [(set (match_operand:XF 0 "nonimmediate_operand" "=f")