invoke.texi (-mcpu=power8): Document.
* doc/invoke.texi (-mcpu=power8): Document. * config.in (HAVE_AS_POWER8): New. * config.gcc: Add cpu_type power8. * configure.ac: (HAVE_AS_POWER8): Check for assembler support for the POWER8 instructions. * configure: Regenerate. * config/rs6000/rs6000.h: (ASM_CPU_POWER8_SPEC): Define. (ASM_CPU_SPEC): Pass %(asm_cpu_power8) for -mcpu=power8. (EXTRA_SPECS): Add asm_cpu_power8 spec string. * config/rs6000/rs6000-cpus.def (processor_target_table): Alias POWER8 to POWER7. * config/rs6000/rs6000-tables.opt: Regenerate. * config/rs6000/driver-rs6000.c (ASM_CPU_SPEC): For -mcpu=power8, pass %(asm_cpu_power8)/-mpwr8. * config/rs6000/aix53.h: Likewise. * config/rs6000/aix61.h: Likewise. From-SVN: r193307
This commit is contained in:
parent
ca78ecf41b
commit
428bffcbcd
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@ -1,3 +1,22 @@
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2012-11-07 Peter Bergner <bergner@vnet.ibm.com>
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* doc/invoke.texi (-mcpu=power8): Document.
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* config.in (HAVE_AS_POWER8): New.
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* config.gcc: Add cpu_type power8.
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* configure.ac: (HAVE_AS_POWER8): Check for assembler support for
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the POWER8 instructions.
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* configure: Regenerate.
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* config/rs6000/rs6000.h: (ASM_CPU_POWER8_SPEC): Define.
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(ASM_CPU_SPEC): Pass %(asm_cpu_power8) for -mcpu=power8.
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(EXTRA_SPECS): Add asm_cpu_power8 spec string.
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* config/rs6000/rs6000-cpus.def (processor_target_table): Alias
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POWER8 to POWER7.
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* config/rs6000/rs6000-tables.opt: Regenerate.
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* config/rs6000/driver-rs6000.c (ASM_CPU_SPEC): For -mcpu=power8,
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pass %(asm_cpu_power8)/-mpwr8.
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* config/rs6000/aix53.h: Likewise.
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* config/rs6000/aix61.h: Likewise.
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2012-11-07 Uros Bizjak <ubizjak@gmail.com>
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PR target/55224
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@ -424,7 +424,7 @@ powerpc*-*-*)
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extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h"
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need_64bit_hwint=yes
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case x$with_cpu in
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xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[34567]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|Xe6500)
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xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[345678]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|Xe6500)
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cpu_is_64bit=yes
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;;
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esac
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@ -3460,7 +3460,7 @@ case "${target}" in
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eval "with_$which=405"
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;;
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"" | common \
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| power | power[234567] | power6x | powerpc | powerpc64 \
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| power | power[2345678] | power6x | powerpc | powerpc64 \
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| rios | rios1 | rios2 | rsc | rsc1 | rs64a \
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| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
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| 476 | 476fp | 505 | 601 | 602 | 603 | 603e | ec603e \
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@ -441,6 +441,12 @@
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#endif
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/* Define if your assembler supports POWER8 instructions. */
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#ifndef USED_FOR_TARGET
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#undef HAVE_AS_POWER8
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#endif
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/* Define if your assembler supports .ref */
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#ifndef USED_FOR_TARGET
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#undef HAVE_AS_REF
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@ -62,6 +62,7 @@ do { \
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%{mcpu=power6: -mpwr6} \
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%{mcpu=power6x: -mpwr6} \
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%{mcpu=power7: -mpwr7} \
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%{mcpu=power8: -mpwr8} \
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%{mcpu=powerpc: -mppc} \
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%{mcpu=rs64a: -mppc} \
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%{mcpu=603: -m603} \
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@ -62,6 +62,7 @@ do { \
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%{mcpu=power6: -mpwr6} \
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%{mcpu=power6x: -mpwr6} \
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%{mcpu=power7: -mpwr7} \
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%{mcpu=power8: -mpwr8} \
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%{mcpu=powerpc: -mppc} \
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%{mcpu=rs64a: -mppc} \
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%{mcpu=603: -m603} \
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@ -354,6 +354,7 @@ static const struct asm_name asm_names[] = {
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{ "power6", "-mpwr6" },
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{ "power6x", "-mpwr6" },
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{ "power7", "-mpwr7" },
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{ "power8", "-mpwr8" },
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{ "powerpc", "-mppc" },
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{ "rs64a", "-mppc" },
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{ "603", "-m603" },
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@ -379,6 +380,7 @@ static const struct asm_name asm_names[] = {
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{ "power6", "%(asm_cpu_power6) -maltivec" },
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{ "power6x", "%(asm_cpu_power6) -maltivec" },
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{ "power7", "%(asm_cpu_power7)" },
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{ "power8", "%(asm_cpu_power8)" },
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{ "powerpc", "-mppc" },
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{ "rs64a", "-mppc64" },
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{ "401", "-mppc" },
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@ -166,6 +166,10 @@ RS6000_CPU ("power7", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */
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POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
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| MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD
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| MASK_VSX | MASK_RECIP_PRECISION)
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RS6000_CPU ("power8", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */
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POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
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| MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD
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| MASK_VSX | MASK_RECIP_PRECISION)
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RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
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RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
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RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)
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@ -177,11 +177,14 @@ EnumValue
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Enum(rs6000_cpu_opt_value) String(power7) Value(49)
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EnumValue
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Enum(rs6000_cpu_opt_value) String(powerpc) Value(50)
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Enum(rs6000_cpu_opt_value) String(power8) Value(50)
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EnumValue
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Enum(rs6000_cpu_opt_value) String(powerpc64) Value(51)
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Enum(rs6000_cpu_opt_value) String(powerpc) Value(51)
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EnumValue
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Enum(rs6000_cpu_opt_value) String(rs64) Value(52)
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Enum(rs6000_cpu_opt_value) String(powerpc64) Value(52)
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EnumValue
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Enum(rs6000_cpu_opt_value) String(rs64) Value(53)
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@ -89,6 +89,12 @@
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#define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec"
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#endif
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#ifdef HAVE_AS_POWER8
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#define ASM_CPU_POWER8_SPEC "-mpower8"
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#else
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#define ASM_CPU_POWER8_SPEC "-mpower4 -maltivec"
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#endif
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#ifdef HAVE_AS_DCI
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#define ASM_CPU_476_SPEC "-m476"
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#else
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%{mcpu=power6: %(asm_cpu_power6) -maltivec} \
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%{mcpu=power6x: %(asm_cpu_power6) -maltivec} \
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%{mcpu=power7: %(asm_cpu_power7)} \
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%{mcpu=power8: %(asm_cpu_power8)} \
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%{mcpu=a2: -ma2} \
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%{mcpu=powerpc: -mppc} \
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%{mcpu=rs64a: -mppc64} \
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{ "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \
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{ "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \
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{ "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \
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{ "asm_cpu_power8", ASM_CPU_POWER8_SPEC }, \
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{ "asm_cpu_476", ASM_CPU_476_SPEC }, \
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SUBTARGET_EXTRA_SPECS
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@ -25210,6 +25210,48 @@ if test $gcc_cv_as_powerpc_popcntd = yes; then
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$as_echo "#define HAVE_AS_POPCNTD 1" >>confdefs.h
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fi
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case $target in
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*-*-aix*) conftest_s=' .machine "pwr8"
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.csect .text[PR]';;
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*) conftest_s=' .machine power8
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.text';;
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esac
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{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for power8 support" >&5
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$as_echo_n "checking assembler for power8 support... " >&6; }
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if test "${gcc_cv_as_powerpc_power8+set}" = set; then :
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$as_echo_n "(cached) " >&6
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else
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gcc_cv_as_powerpc_power8=no
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if test $in_tree_gas = yes; then
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if test $gcc_cv_gas_vers -ge `expr \( \( 2 \* 1000 \) + 19 \) \* 1000 + 2`
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then gcc_cv_as_powerpc_power8=yes
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fi
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elif test x$gcc_cv_as != x; then
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$as_echo "$conftest_s" > conftest.s
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if { ac_try='$gcc_cv_as $gcc_cv_as_flags -a32 -o conftest.o conftest.s >&5'
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{ { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
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(eval $ac_try) 2>&5
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ac_status=$?
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$as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
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test $ac_status = 0; }; }
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then
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gcc_cv_as_powerpc_power8=yes
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else
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echo "configure: failed program was" >&5
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cat conftest.s >&5
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fi
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rm -f conftest.o conftest.s
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fi
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fi
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{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_powerpc_power8" >&5
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$as_echo "$gcc_cv_as_powerpc_power8" >&6; }
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if test $gcc_cv_as_powerpc_power8 = yes; then
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$as_echo "#define HAVE_AS_POWER8 1" >>confdefs.h
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fi
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case $target in
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@ -3863,6 +3863,19 @@ LCF0:
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[AC_DEFINE(HAVE_AS_POPCNTD, 1,
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[Define if your assembler supports POPCNTD instructions.])])
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case $target in
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*-*-aix*) conftest_s=' .machine "pwr8"
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.csect .text[[PR]]';;
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*) conftest_s=' .machine power8
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.text';;
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esac
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gcc_GAS_CHECK_FEATURE([power8 support],
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gcc_cv_as_powerpc_power8, [2,19,2], -a32,
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[$conftest_s],,
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[AC_DEFINE(HAVE_AS_POWER8, 1,
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[Define if your assembler supports POWER8 instructions.])])
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case $target in
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*-*-aix*) conftest_s=' .csect .text[[PR]]
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lwsync';;
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@ -17101,7 +17101,7 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403},
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@samp{e300c3}, @samp{e500mc}, @samp{e500mc64}, @samp{e5500},
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@samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
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@samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+},
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@samp{power6}, @samp{power6x}, @samp{power7}, @samp{powerpc},
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@samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8}, @samp{powerpc},
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@samp{powerpc64}, and @samp{rs64}.
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@option{-mcpu=powerpc}, and @option{-mcpu=powerpc64} specify pure 32-bit
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@opindex mrecip-precision
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Assume (do not assume) that the reciprocal estimate instructions
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provide higher-precision estimates than is mandated by the PowerPC
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ABI. Selecting @option{-mcpu=power6} or @option{-mcpu=power7}
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automatically selects @option{-mrecip-precision}. The double-precision
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square root estimate instructions are not generated by
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ABI. Selecting @option{-mcpu=power6}, @option{-mcpu=power7} or
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@option{-mcpu=power8} automatically selects @option{-mrecip-precision}.
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The double-precision square root estimate instructions are not generated by
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default on low-precision machines, since they do not provide an
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estimate that converges after three steps.
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