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re PR target/28150 (ICE in reload_cse_simplify_operands, at postreload.c:394) 

2006-07-06  David Edelsohn  <edelsohn@gnu.org>

        PR target/28150
        * config/rs6000/rs6000.c (rs6000_legitimate_address): Do not allow
        PRE_{INC,DEC} of TFmode.

2006-07-06  David Edelsohn  <edelsohn@gnu.org>
            Alan Modra  <amodra@bigpond.net.au>

        PR target/28170
        * config/rs6000/rs6000.c (insvdi_rshift_rlwimi_p): Correct shiftop
        bounds. Simplify.

Co-Authored-By: Alan Modra <amodra@bigpond.net.au>

From-SVN: r115229
This commit is contained in:
David Edelsohn 2006-07-06 18:59:58 +00:00 committed by David Edelsohn
parent 1f0b926a1f
commit 429ec7dc9b
2 changed files with 20 additions and 6 deletions
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13
gcc/ChangeLog
View File

@ -1,3 +1,16 @@
2006-07-06 David Edelsohn <edelsohn@gnu.org>
PR target/28150
* config/rs6000/rs6000.c (rs6000_legitimate_address): Do not allow
PRE_{INC,DEC} of TFmode.
2006-07-06 David Edelsohn <edelsohn@gnu.org>
Alan Modra <amodra@bigpond.net.au>
PR target/28170
* config/rs6000/rs6000.c (insvdi_rshift_rlwimi_p): Correct shiftop
bounds. Simplify.
2006-07-06 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
PR target/28285

13
gcc/config/rs6000/rs6000.c
View File

@ -3522,6 +3522,7 @@ rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
&& !ALTIVEC_VECTOR_MODE (mode)
&& !SPE_VECTOR_MODE (mode)
&& mode != TFmode
/* Restrict addressing for DI because of our SUBREG hackery. */
&& !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
&& TARGET_UPDATE
@ -9799,12 +9800,12 @@ effects of instruction do not correspond to semantics of RTL insn. */
int
insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
{
if (INTVAL (startop) < 64
&& INTVAL (startop) > 32
&& (INTVAL (sizeop) + INTVAL (startop) < 64)
&& (INTVAL (sizeop) + INTVAL (startop) > 33)
&& (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
&& (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
if (INTVAL (startop) > 32
&& INTVAL (startop) < 64
&& INTVAL (sizeop) > 1
&& INTVAL (sizeop) + INTVAL (startop) < 64
&& INTVAL (shiftop) > 0
&& INTVAL (sizeop) + INTVAL (shiftop) < 32
&& (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
return 1;