Fix zero-masking for vcvtps2ph when dest operand is memory.
When dest is memory, zero-masking is not valid, only merging-masking is available, 2020-06-24 Hongtao Liu <hongtao.liu@inte.com> gcc/ChangeLog: PR target/95254 * config/i386/sse.md (*vcvtps2ph_store<merge_mask_name>): Refine from *vcvtps2ph_store<mask_name>. (vcvtps2ph256<mask_name>): Refine constraint from vm to v. (<mask_codefor>avx512f_vcvtps2ph512<mask_name>): Ditto. (*vcvtps2ph256<merge_mask_name>): New define_insn. (*avx512f_vcvtps2ph512<merge_mask_name>): Ditto. * config/i386/subst.md (merge_mask): New define_subst. (merge_mask_name): New define_subst_attr. (merge_mask_operand3): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512f-vcvtps2ph-pr95254.c: New test. * gcc.target/i386/avx512vl-vcvtps2ph-pr95254.c: Ditto.
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@ -21775,19 +21775,19 @@
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(set_attr "prefix" "maybe_evex")
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(set_attr "mode" "V4SF")])
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(define_insn "*vcvtps2ph_store<mask_name>"
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(define_insn "*vcvtps2ph_store<merge_mask_name>"
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[(set (match_operand:V4HI 0 "memory_operand" "=m")
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(unspec:V4HI [(match_operand:V4SF 1 "register_operand" "v")
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(match_operand:SI 2 "const_0_to_255_operand" "N")]
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UNSPEC_VCVTPS2PH))]
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"TARGET_F16C || TARGET_AVX512VL"
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"vcvtps2ph\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
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"vcvtps2ph\t{%2, %1, %0<merge_mask_operand3>|%0<merge_mask_operand3>, %1, %2}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "maybe_evex")
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(set_attr "mode" "V4SF")])
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(define_insn "vcvtps2ph256<mask_name>"
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[(set (match_operand:V8HI 0 "nonimmediate_operand" "=vm")
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[(set (match_operand:V8HI 0 "register_operand" "=v")
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(unspec:V8HI [(match_operand:V8SF 1 "register_operand" "v")
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(match_operand:SI 2 "const_0_to_255_operand" "N")]
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UNSPEC_VCVTPS2PH))]
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@ -21798,8 +21798,20 @@
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(set_attr "btver2_decode" "vector")
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(set_attr "mode" "V8SF")])
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(define_insn "*vcvtps2ph256<merge_mask_name>"
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[(set (match_operand:V8HI 0 "memory_operand" "=m")
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(unspec:V8HI [(match_operand:V8SF 1 "register_operand" "v")
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(match_operand:SI 2 "const_0_to_255_operand" "N")]
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UNSPEC_VCVTPS2PH))]
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"TARGET_F16C || TARGET_AVX512VL"
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"vcvtps2ph\t{%2, %1, %0<merge_mask_operand3>|%0<merge_mask_operand3>, %1, %2}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "maybe_evex")
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(set_attr "btver2_decode" "vector")
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(set_attr "mode" "V8SF")])
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(define_insn "<mask_codefor>avx512f_vcvtps2ph512<mask_name>"
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[(set (match_operand:V16HI 0 "nonimmediate_operand" "=vm")
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[(set (match_operand:V16HI 0 "register_operand" "=v")
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(unspec:V16HI
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[(match_operand:V16SF 1 "register_operand" "v")
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(match_operand:SI 2 "const_0_to_255_operand" "N")]
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@ -21810,6 +21822,18 @@
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(set_attr "prefix" "evex")
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(set_attr "mode" "V16SF")])
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(define_insn "*avx512f_vcvtps2ph512<merge_mask_name>"
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[(set (match_operand:V16HI 0 "memory_operand" "=m")
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(unspec:V16HI
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[(match_operand:V16SF 1 "register_operand" "v")
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(match_operand:SI 2 "const_0_to_255_operand" "N")]
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UNSPEC_VCVTPS2PH))]
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"TARGET_AVX512F"
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"vcvtps2ph\t{%2, %1, %0<merge_mask_operand3>|%0<merge_mask_operand3>, %1, %2}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "V16SF")])
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;; For gather* insn patterns
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(define_mode_iterator VEC_GATHER_MODE
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[V2DI V2DF V4DI V4DF V4SI V4SF V8SI V8SF])
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@ -73,6 +73,18 @@
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(match_operand:SUBST_V 2 "nonimm_or_0_operand" "0C")
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(match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))])
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(define_subst_attr "merge_mask_name" "merge_mask" "" "_merge_mask")
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(define_subst_attr "merge_mask_operand3" "merge_mask" "" "%{%3%}")
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(define_subst "merge_mask"
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[(set (match_operand:SUBST_V 0)
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(match_operand:SUBST_V 1))]
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"TARGET_AVX512F"
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[(set (match_dup 0)
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(vec_merge:SUBST_V
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(match_dup 1)
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(match_dup 0)
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(match_operand:<avx512fmaskmode> 2 "register_operand" "Yk")))])
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(define_subst_attr "mask_scalar_merge_name" "mask_scalar_merge" "" "_mask")
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(define_subst_attr "mask_scalar_merge_operand3" "mask_scalar_merge" "" "%{%3%}")
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(define_subst_attr "mask_scalar_merge_operand4" "mask_scalar_merge" "" "%{%4%}")
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12
gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-pr95254.c
Normal file
12
gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-pr95254.c
Normal file
@ -0,0 +1,12 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -mavx512f" } */
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#include<immintrin.h>
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extern __m256i res;
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void
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foo (__m512 a, __mmask16 m)
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{
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res = _mm512_maskz_cvtps_ph (m, a, 10);
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}
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/* { dg-final { scan-assembler-not "vcvtps2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]\[^\n\]*res\[^\n\]*\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)"} } */
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18
gcc/testsuite/gcc.target/i386/avx512vl-vcvtps2ph-pr95254.c
Normal file
18
gcc/testsuite/gcc.target/i386/avx512vl-vcvtps2ph-pr95254.c
Normal file
@ -0,0 +1,18 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -mavx512vl -mavx512f" } */
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#include<immintrin.h>
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extern __m128i res;
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void
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foo (__m256 a, __mmask8 m)
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{
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res = _mm256_maskz_cvtps_ph (m, a, 10);
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}
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void
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foo1 (__m128 a, __mmask8 m)
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{
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res = _mm_maskz_cvtps_ph (m, a, 10);
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}
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/* { dg-final { scan-assembler-not "vcvtps2ph\[ \\t\]+\[^\{\n\]*%\[xy\]mm\[0-9\]\[^\n\]*res\[^\n\]*\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)"} } */
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