From 432b29c189a6d26ed701c7518402708b2fcb794f Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Thu, 15 Aug 2019 08:39:42 +0000 Subject: [PATCH] [AArch64] Add more SVE FMLA and FMAD /z alternatives This patch makes the floating-point conditional FMA patterns provide the same /z alternatives as the integer patterns added by a previous patch. We can handle cases in which individual inputs are allocated to the same register as the output, so we don't need to force all registers to be different. 2019-08-15 Richard Sandiford Kugan Vivekanandarajah gcc/ * config/aarch64/aarch64-sve.md (*cond__any): Add /z alternatives in which one of the inputs is in the same register as the output. gcc/testsuite/ * gcc.target/aarch64/sve/cond_mla_5.c: Allow FMAD as well as FMLA and FMSB as well as FMLS. Co-Authored-By: Kugan Vivekanandarajah From-SVN: r274516 --- gcc/ChangeLog | 8 ++++++++ gcc/config/aarch64/aarch64-sve.md | 15 +++++++++------ gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.target/aarch64/sve/cond_mla_5.c | 12 ++++++------ 4 files changed, 29 insertions(+), 12 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cb39212683c..0fd607e46bb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2019-08-15 Richard Sandiford + Kugan Vivekanandarajah + + * config/aarch64/aarch64-sve.md + (*cond__any): Add /z + alternatives in which one of the inputs is in the same register + as the output. + 2019-08-15 Richard Sandiford * config/aarch64/aarch64-sve.md (*vec_extract_ext) diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 9007a79d0e9..c5d7801a3ce 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -3844,17 +3844,17 @@ ;; Predicated floating-point ternary operations, merging with an ;; independent value. (define_insn_and_rewrite "*cond__any" - [(set (match_operand:SVE_F 0 "register_operand" "=&w, &w, ?&w") + [(set (match_operand:SVE_F 0 "register_operand" "=&w, &w, &w, &w, &w, ?&w") (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl, Upl, Upl") + [(match_operand: 1 "register_operand" "Upl, Upl, Upl, Upl, Upl, Upl") (unspec:SVE_F [(match_operand 6) (match_operand:SI 7 "aarch64_sve_gp_strictness") - (match_operand:SVE_F 2 "register_operand" "w, w, w") - (match_operand:SVE_F 3 "register_operand" "w, w, w") - (match_operand:SVE_F 4 "register_operand" "w, w, w")] + (match_operand:SVE_F 2 "register_operand" "w, w, 0, w, w, w") + (match_operand:SVE_F 3 "register_operand" "w, w, w, 0, w, w") + (match_operand:SVE_F 4 "register_operand" "w, 0, w, w, w, w")] SVE_COND_FP_TERNARY) - (match_operand:SVE_F 5 "aarch64_simd_reg_or_zero" "Dz, 0, w")] + (match_operand:SVE_F 5 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, Dz, 0, w")] UNSPEC_SEL))] "TARGET_SVE && !rtx_equal_p (operands[2], operands[5]) @@ -3863,6 +3863,9 @@ && aarch64_sve_pred_dominates_p (&operands[6], operands[1])" "@ movprfx\t%0., %1/z, %4.\;\t%0., %1/m, %2., %3. + movprfx\t%0., %1/z, %0.\;\t%0., %1/m, %2., %3. + movprfx\t%0., %1/z, %0.\;\t%0., %1/m, %3., %4. + movprfx\t%0., %1/z, %0.\;\t%0., %1/m, %2., %4. movprfx\t%0., %1/m, %4.\;\t%0., %1/m, %2., %3. #" "&& 1" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 731249adbdf..308386c703c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2019-08-15 Richard Sandiford + Kugan Vivekanandarajah + + * gcc.target/aarch64/sve/cond_mla_5.c: Allow FMAD as well as FMLA + and FMSB as well as FMLS. + 2019-08-15 Richard Sandiford * gcc.target/aarch64/sve/ext_2.c: Expect a MOVPRFX. diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_mla_5.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_mla_5.c index e71f2b0336f..97e23357996 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/cond_mla_5.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_mla_5.c @@ -39,13 +39,13 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {\t(?:mls|msb)\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ /* { dg-final { scan-assembler-times {\t(?:mls|msb)\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ -/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ -/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ -/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\t(?:fmla|fmad)\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\t(?:fmla|fmad)\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\t(?:fmla|fmad)\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ -/* { dg-final { scan-assembler-times {\tfmls\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ -/* { dg-final { scan-assembler-times {\tfmls\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ -/* { dg-final { scan-assembler-times {\tfmls\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\t(?:fmls|fmsb)\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\t(?:fmls|fmsb)\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\t(?:fmls|fmsb)\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ /* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.b, p[0-7]/z,} 2 } } */ /* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z,} 4 } } */