re PR target/72867 (SSE/AVX/AVX512: incorrect optimization of VMINPS/VMAXPS at compile time)
PR target/72867 * config/i386/sse.md (<code><mode>3<mask_name><round_saeonly_name>): Emit ieee_<ieee_maxmin><mode>3<mask_name><round_saeonly_name> for !flag_finite_math_only or flag_signed_zeros. (*<code><mode>3<mask_name><round_saeonly_name>): Rename from *<code><mode>3_finite<mask_name><round_saeonly_name>. Do not depend on flag_finite_math_only. (ieee_<ieee_maxmin><mode>3<mask_name><round_saeonly_name>): New insn pattern. (*<code><mode>3<mask_name><round_saeonly_name>): Remove. (*ieee_smin<mode>3): Ditto. (*ieee_smax<mode>3): Ditto. * config/i386/mmx.md (mmx_<code>v2sf3): Emit mmx_ieee_<ieee_maxmin>v2sf3 for !flag_finite_math_only or flag_signed_zeros. (*mmx_<code>v2sf3): Rename from *mmx_<code>v2sf3_finite. Do not depend on flag_finite_math_only. (mmx_ieee_<ieee_maxmin>v2sf3): New insn pattern. (*mmx_<code>v2sf3): Remove. * config/i386/subst.md (round_saeonly_mask_arg3): New subst attribute. * config/i386/i386.c (ix86_expand_sse_fp_mimnax): Check flag_signed_zeros instead of !flag_unsafe_math_optimizations. testsuite/ChangeLog: PR target/72867 * gcc.target/i386/pr72867.c: New test. From-SVN: r239487
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
87155d4f6c
commit
432baa029c
@ -1,3 +1,28 @@
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2016-08-15 Uros Bizjak <ubizjak@gmail.com>
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PR target/72867
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* config/i386/sse.md (<code><mode>3<mask_name><round_saeonly_name>):
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Emit ieee_<ieee_maxmin><mode>3<mask_name><round_saeonly_name>
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for !flag_finite_math_only or flag_signed_zeros.
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(*<code><mode>3<mask_name><round_saeonly_name>): Rename from
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*<code><mode>3_finite<mask_name><round_saeonly_name>. Do not
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depend on flag_finite_math_only.
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(ieee_<ieee_maxmin><mode>3<mask_name><round_saeonly_name>):
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New insn pattern.
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(*<code><mode>3<mask_name><round_saeonly_name>): Remove.
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(*ieee_smin<mode>3): Ditto.
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(*ieee_smax<mode>3): Ditto.
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* config/i386/mmx.md (mmx_<code>v2sf3): Emit
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mmx_ieee_<ieee_maxmin>v2sf3 for !flag_finite_math_only or
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flag_signed_zeros.
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(*mmx_<code>v2sf3): Rename from *mmx_<code>v2sf3_finite. Do not
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depend on flag_finite_math_only.
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(mmx_ieee_<ieee_maxmin>v2sf3): New insn pattern.
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(*mmx_<code>v2sf3): Remove.
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* config/i386/subst.md (round_saeonly_mask_arg3): New subst attribute.
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* config/i386/i386.c (ix86_expand_sse_fp_mimnax): Check
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flag_signed_zeros instead of !flag_unsafe_math_optimizations.
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2016-08-15 Segher Boessenkool <segher@kernel.crashing.org>
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PR rtl-optimization/73650
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@ -23404,7 +23404,7 @@ ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
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/* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
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but MODE may be a vector mode and thus not appropriate. */
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if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
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if (!flag_finite_math_only || flag_signed_zeros)
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{
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int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
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rtvec v;
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@ -885,6 +885,14 @@
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(umax "maxu") (umin "minu")])
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(define_code_attr maxmin_float [(smax "max") (smin "min")])
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(define_int_iterator IEEE_MAXMIN
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[UNSPEC_IEEE_MAX
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UNSPEC_IEEE_MIN])
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(define_int_attr ieee_maxmin
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[(UNSPEC_IEEE_MAX "max")
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(UNSPEC_IEEE_MIN "min")])
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;; Mapping of logic operators
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(define_code_iterator any_logic [and ior xor])
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(define_code_iterator any_or [ior xor])
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@ -17401,14 +17409,6 @@
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;; Their operands are not commutative, and thus they may be used in the
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;; presence of -0.0 and NaN.
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(define_int_iterator IEEE_MAXMIN
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[UNSPEC_IEEE_MAX
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UNSPEC_IEEE_MIN])
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(define_int_attr ieee_maxmin
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[(UNSPEC_IEEE_MAX "max")
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(UNSPEC_IEEE_MIN "min")])
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(define_insn "*ieee_s<ieee_maxmin><mode>3"
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[(set (match_operand:MODEF 0 "register_operand" "=x,v")
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(unspec:MODEF
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@ -296,10 +296,6 @@
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(set_attr "prefix_extra" "1")
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(set_attr "mode" "V2SF")])
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;; ??? For !flag_finite_math_only, the representation with SMIN/SMAX
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;; isn't really correct, as those rtl operators aren't defined when
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;; applied to NaNs. Hopefully the optimizers won't get too smart on us.
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(define_expand "mmx_<code>v2sf3"
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[(set (match_operand:V2SF 0 "register_operand")
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(smaxmin:V2SF
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@ -307,30 +303,47 @@
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(match_operand:V2SF 2 "nonimmediate_operand")))]
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"TARGET_3DNOW"
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{
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if (!flag_finite_math_only)
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operands[1] = force_reg (V2SFmode, operands[1]);
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ix86_fixup_binary_operands_no_copy (<CODE>, V2SFmode, operands);
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if (!flag_finite_math_only || flag_signed_zeros)
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{
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operands[1] = force_reg (V2SFmode, operands[1]);
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emit_insn (gen_mmx_ieee_<maxmin_float>v2sf3
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(operands[0], operands[1], operands[2]));
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DONE;
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}
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else
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ix86_fixup_binary_operands_no_copy (<CODE>, V2SFmode, operands);
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})
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(define_insn "*mmx_<code>v2sf3_finite"
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;; These versions of the min/max patterns are intentionally ignorant of
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;; their behavior wrt -0.0 and NaN (via the commutative operand mark).
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;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator
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;; are undefined in this condition, we're certain this is correct.
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(define_insn "*mmx_<code>v2sf3"
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[(set (match_operand:V2SF 0 "register_operand" "=y")
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(smaxmin:V2SF
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(match_operand:V2SF 1 "nonimmediate_operand" "%0")
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(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
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"TARGET_3DNOW && flag_finite_math_only
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&& ix86_binary_operator_ok (<CODE>, V2SFmode, operands)"
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"TARGET_3DNOW && ix86_binary_operator_ok (<CODE>, V2SFmode, operands)"
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"pf<maxmin_float>\t{%2, %0|%0, %2}"
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[(set_attr "type" "mmxadd")
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(set_attr "prefix_extra" "1")
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(set_attr "mode" "V2SF")])
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(define_insn "*mmx_<code>v2sf3"
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;; These versions of the min/max patterns implement exactly the operations
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;; min = (op1 < op2 ? op1 : op2)
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;; max = (!(op1 < op2) ? op1 : op2)
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;; Their operands are not commutative, and thus they may be used in the
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;; presence of -0.0 and NaN.
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(define_insn "mmx_ieee_<ieee_maxmin>v2sf3"
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[(set (match_operand:V2SF 0 "register_operand" "=y")
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(smaxmin:V2SF
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(match_operand:V2SF 1 "register_operand" "0")
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(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
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(unspec:V2SF
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[(match_operand:V2SF 1 "register_operand" "0")
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(match_operand:V2SF 2 "nonimmediate_operand" "ym")]
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IEEE_MAXMIN))]
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"TARGET_3DNOW"
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"pf<maxmin_float>\t{%2, %0|%0, %2}"
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"pf<ieee_maxmin>\t{%2, %0|%0, %2}"
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[(set_attr "type" "mmxadd")
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(set_attr "prefix_extra" "1")
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(set_attr "mode" "V2SF")])
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@ -1633,10 +1633,6 @@
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "SF")])
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;; ??? For !flag_finite_math_only, the representation with SMIN/SMAX
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;; isn't really correct, as those rtl operators aren't defined when
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;; applied to NaNs. Hopefully the optimizers won't get too smart on us.
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(define_expand "<code><mode>3<mask_name><round_saeonly_name>"
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[(set (match_operand:VF 0 "register_operand")
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(smaxmin:VF
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@ -1644,18 +1640,30 @@
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(match_operand:VF 2 "<round_saeonly_nimm_predicate>")))]
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"TARGET_SSE && <mask_mode512bit_condition> && <round_saeonly_mode512bit_condition>"
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{
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if (!flag_finite_math_only)
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operands[1] = force_reg (<MODE>mode, operands[1]);
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ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);
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if (!flag_finite_math_only || flag_signed_zeros)
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{
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operands[1] = force_reg (<MODE>mode, operands[1]);
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emit_insn (gen_ieee_<maxmin_float><mode>3<mask_name><round_saeonly_name>
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(operands[0], operands[1], operands[2]
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<mask_operand_arg34>
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<round_saeonly_mask_arg3>));
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DONE;
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}
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else
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ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);
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})
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(define_insn "*<code><mode>3_finite<mask_name><round_saeonly_name>"
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;; These versions of the min/max patterns are intentionally ignorant of
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;; their behavior wrt -0.0 and NaN (via the commutative operand mark).
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;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator
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;; are undefined in this condition, we're certain this is correct.
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(define_insn "*<code><mode>3<mask_name><round_saeonly_name>"
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[(set (match_operand:VF 0 "register_operand" "=x,v")
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(smaxmin:VF
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(match_operand:VF 1 "<round_saeonly_nimm_predicate>" "%0,v")
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(match_operand:VF 2 "<round_saeonly_nimm_predicate>" "xBm,<round_saeonly_constraint>")))]
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"TARGET_SSE && flag_finite_math_only
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&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
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"TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
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&& <mask_mode512bit_condition> && <round_saeonly_mode512bit_condition>"
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"@
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<maxmin_float><ssemodesuffix>\t{%2, %0|%0, %2}
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@ -1666,16 +1674,23 @@
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(set_attr "prefix" "<mask_prefix3>")
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(set_attr "mode" "<MODE>")])
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(define_insn "*<code><mode>3<mask_name><round_saeonly_name>"
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;; These versions of the min/max patterns implement exactly the operations
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;; min = (op1 < op2 ? op1 : op2)
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;; max = (!(op1 < op2) ? op1 : op2)
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;; Their operands are not commutative, and thus they may be used in the
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;; presence of -0.0 and NaN.
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(define_insn "ieee_<ieee_maxmin><mode>3<mask_name><round_saeonly_name>"
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[(set (match_operand:VF 0 "register_operand" "=x,v")
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(smaxmin:VF
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(match_operand:VF 1 "register_operand" "0,v")
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(match_operand:VF 2 "<round_saeonly_nimm_predicate>" "xBm,<round_saeonly_constraint>")))]
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"TARGET_SSE && !flag_finite_math_only
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(unspec:VF
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[(match_operand:VF 1 "register_operand" "0,v")
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(match_operand:VF 2 "<round_saeonly_nimm_predicate>" "xBm,<round_saeonly_constraint>")]
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IEEE_MAXMIN))]
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"TARGET_SSE
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&& <mask_mode512bit_condition> && <round_saeonly_mode512bit_condition>"
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"@
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<maxmin_float><ssemodesuffix>\t{%2, %0|%0, %2}
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v<maxmin_float><ssemodesuffix>\t{<round_saeonly_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_saeonly_mask_op3>}"
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<ieee_maxmin><ssemodesuffix>\t{%2, %0|%0, %2}
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v<ieee_maxmin><ssemodesuffix>\t{<round_saeonly_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_saeonly_mask_op3>}"
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[(set_attr "isa" "noavx,avx")
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(set_attr "type" "sseadd")
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(set_attr "btver2_sse_attr" "maxmin")
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@ -1700,42 +1715,6 @@
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(set_attr "prefix" "<round_saeonly_prefix>")
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(set_attr "mode" "<ssescalarmode>")])
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;; These versions of the min/max patterns implement exactly the operations
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;; min = (op1 < op2 ? op1 : op2)
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;; max = (!(op1 < op2) ? op1 : op2)
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;; Their operands are not commutative, and thus they may be used in the
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;; presence of -0.0 and NaN.
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(define_insn "*ieee_smin<mode>3"
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[(set (match_operand:VF 0 "register_operand" "=x,v")
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(unspec:VF
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[(match_operand:VF 1 "register_operand" "0,v")
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(match_operand:VF 2 "vector_operand" "xBm,vm")]
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UNSPEC_IEEE_MIN))]
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"TARGET_SSE"
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"@
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min<ssemodesuffix>\t{%2, %0|%0, %2}
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vmin<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "isa" "noavx,avx")
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(set_attr "type" "sseadd")
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "<MODE>")])
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(define_insn "*ieee_smax<mode>3"
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[(set (match_operand:VF 0 "register_operand" "=x,v")
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(unspec:VF
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[(match_operand:VF 1 "register_operand" "0,v")
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(match_operand:VF 2 "vector_operand" "xBm,vm")]
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UNSPEC_IEEE_MAX))]
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"TARGET_SSE"
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"@
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max<ssemodesuffix>\t{%2, %0|%0, %2}
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vmax<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "isa" "noavx,avx")
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(set_attr "type" "sseadd")
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "<MODE>")])
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(define_insn "avx_addsubv4df3"
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[(set (match_operand:V4DF 0 "register_operand" "=x")
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(vec_merge:V4DF
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@ -161,6 +161,7 @@
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(define_subst_attr "round_saeonly_mask_op4" "round_saeonly" "" "<round_saeonly_mask_operand4>")
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(define_subst_attr "round_saeonly_mask_scalar_merge_op4" "round_saeonly" "" "<round_saeonly_mask_scalar_merge_operand4>")
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(define_subst_attr "round_saeonly_sd_mask_op5" "round_saeonly" "" "<round_saeonly_sd_mask_operand5>")
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(define_subst_attr "round_saeonly_mask_arg3" "round_saeonly" "" ", operands[<mask_expand_op3>]")
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(define_subst_attr "round_saeonly_constraint" "round_saeonly" "vm" "v")
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(define_subst_attr "round_saeonly_constraint2" "round_saeonly" "m" "v")
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(define_subst_attr "round_saeonly_nimm_predicate" "round_saeonly" "vector_operand" "register_operand")
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@ -1,3 +1,8 @@
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2016-08-15 Uros Bizjak <ubizjak@gmail.com>
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PR target/72867
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* gcc.target/i386/pr72867.c: New test.
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2016-08-16 Eric Botcazou <ebotcazou@adacore.com>
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* c-c++-common/dump-ada-spec-5.c: New test.
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23
gcc/testsuite/gcc.target/i386/pr72867.c
Normal file
23
gcc/testsuite/gcc.target/i386/pr72867.c
Normal file
@ -0,0 +1,23 @@
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/* PR target/72867 */
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/* { dg-do run } */
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/* { dg-options "-O2" } */
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/* { dg-require-effective-target sse } */
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#include "sse-check.h"
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#include <xmmintrin.h>
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static void
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sse_test (void)
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{
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float nan = __builtin_nanf ("");
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__m128 x = _mm_min_ps(_mm_set1_ps(nan), _mm_set1_ps(1.0f));
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if (x[0] != 1.0f)
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abort ();
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x = _mm_min_ps(_mm_set1_ps(1.f), _mm_set1_ps(nan));
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if (!__builtin_isnan (x[0]))
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abort ();
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}
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