pa.c (output_global_address): Handle (high (const (plus ...))).
* pa.c (output_global_address): Handle (high (const (plus ...))). (secondary_reload_class): If TARGET_KERNEL, then loading a symbolic address, or the high part of a symbolic address requires %r1 as a secondary reload register. (emit_move_sequence, SYMBOL_REF case): If TARGET_KERNEL, then handle secondary reload created for a symbolic (high (const (plus ...))). No longer show DP relocation; read_only and normal operands emit the same RTL now. Emit the same RTL before and after reload, only change how the scratch/temporary register is chosen. From-SVN: r3186
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9f309ba3e7
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@ -594,8 +594,18 @@ emit_move_sequence (operands, mode, scratch_reg)
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}
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/* Simplify the source if we need to. */
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if (GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
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if (GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode)
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|| (GET_CODE (operand1) == HIGH
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&& symbolic_operand (XEXP (operand1, 0), mode)
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&& TARGET_KERNEL))
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{
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int ishighonly = 0;
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if (GET_CODE (operand1) == HIGH)
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{
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ishighonly = 1;
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operand1 = XEXP (operand1, 0);
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}
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if (symbolic_operand (operand1, mode))
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{
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if (flag_pic)
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@ -604,15 +614,26 @@ emit_move_sequence (operands, mode, scratch_reg)
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operands[1] = legitimize_pic_address (operand1, mode, temp);
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}
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/* On the HPPA, references to data space are supposed to */
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/* use dp, register 27. */
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else if (read_only_operand (operand1))
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/* use dp, register 27, but showing it in the RTL inhibits various
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cse and loop optimizations. */
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else
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{
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rtx set = gen_rtx (SET, VOIDmode,
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operand0,
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gen_rtx (LO_SUM, mode, operand0, operand1));
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rtx temp, set;
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if (reload_in_progress)
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temp = scratch_reg ? scratch_reg : operand0;
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else
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temp = gen_reg_rtx (mode);
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if (ishighonly)
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set = gen_rtx (SET, mode, operand0, temp);
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else
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set = gen_rtx (SET, VOIDmode,
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operand0,
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gen_rtx (LO_SUM, mode, temp, operand1));
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emit_insn (gen_rtx (SET, VOIDmode,
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operand0,
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temp,
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gen_rtx (HIGH, mode, operand1)));
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if (TARGET_SHARED_LIBS
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&& function_label_operand (operand1, mode))
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@ -631,45 +652,7 @@ emit_move_sequence (operands, mode, scratch_reg)
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emit_insn (set);
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return 1;
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}
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else
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{
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/* If reload_in_progress, we can't use addil and r1; we */
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/* have to use the more expensive ldil sequence. */
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if (reload_in_progress)
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{
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emit_insn (gen_rtx (SET, VOIDmode,
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operand0,
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gen_rtx (HIGH, mode, operand1)));
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emit_insn (gen_rtx (SET, VOIDmode,
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operand0,
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gen_rtx (PLUS, mode,
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operand0,
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gen_rtx (REG, mode, 27))));
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emit_insn (gen_rtx (SET, VOIDmode,
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operand0,
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gen_rtx (LO_SUM, mode,
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operand0, operand1)));
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}
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else
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{
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rtx temp1, temp2 = gen_reg_rtx (mode);
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/* For 2.4 we could set RTX_UNCHANGING and add a
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REG_EQUAL note for the first insn. This would
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allow the first insn to be moved out of loops. */
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temp1 = gen_rtx (HIGH, mode, operand1);
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emit_insn (gen_rtx (SET, VOIDmode,
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temp2,
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gen_rtx (PLUS, mode,
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gen_rtx (REG, mode, 27),
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temp1)));
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emit_insn (gen_rtx (SET, VOIDmode,
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operand0,
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gen_rtx (LO_SUM, mode,
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temp2, operand1)));
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}
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return 1;
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}
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return 1;
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}
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else if (depi_cint_operand (operand1, VOIDmode))
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return 0;
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@ -2097,6 +2080,11 @@ output_global_address (file, x)
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FILE *file;
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rtx x;
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{
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/* Imagine (high (const (plus ...))). */
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if (GET_CODE (x) == HIGH)
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x = XEXP (x, 0);
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if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x))
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assemble_name (file, XSTR (x, 0));
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else if (GET_CODE (x) == SYMBOL_REF)
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@ -2428,6 +2416,12 @@ secondary_reload_class (class, mode, in)
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|| (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
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return GENERAL_REGS;
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if (GET_CODE (in) == HIGH)
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in = XEXP (in, 0);
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if (TARGET_KERNEL && class != R1_REGS && symbolic_operand (in, VOIDmode))
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return R1_REGS;
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return NO_REGS;
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}
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