From 4395a4738963e1bfc2202a2433c6d1d24a28e017 Mon Sep 17 00:00:00 2001
From: Thomas Preud'homme <thomas.preudhomme@arm.com>
Date: Wed, 13 Sep 2017 10:27:00 +0000
Subject: [PATCH] [testsuite/ARM] Fix coprocessor intrinsic test failures on
 ARMv8-A

Coprocessor intrinsic tests in gcc.target/arm/acle test whether
__ARM_FEATURE_COPROC has the right bit defined before calling the
intrinsic. This allows to test both the correct setting of that macro
and the availability and correct working of the intrinsic. However the
__ARM_FEATURE_COPROC macro is no longer defined for ARMv8-A since
r249399.

This patch changes the testcases to skip that test for ARMv8-A and
ARMv8-R targets.  It also fixes some irregularity in the coprocessor
effective targets:
- add ldcl and stcl to the list of instructions listed as guarded by
  arm_coproc1_ok
- enable tests guarded by arm_coproc2_ok, arm_coproc3_ok and
  arm_coproc4_ok for Thumb-2 capable targets but disable for Thumb-1
  targets.

2017-09-13  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/testsuite/
    * gcc.target/arm/acle/cdp.c: Skip __ARM_FEATURE_COPROC check for
    ARMv8-A and ARMv8-R.
    * gcc.target/arm/acle/cdp2.c: Likewise.
    * gcc.target/arm/acle/ldc.c: Likewise.
    * gcc.target/arm/acle/ldc2.c: Likewise.
    * gcc.target/arm/acle/ldc2l.c: Likewise.
    * gcc.target/arm/acle/ldcl.c: Likewise.
    * gcc.target/arm/acle/mcr.c: Likewise.
    * gcc.target/arm/acle/mcr2.c: Likewise.
    * gcc.target/arm/acle/mcrr.c: Likewise.
    * gcc.target/arm/acle/mcrr2.c: Likewise.
    * gcc.target/arm/acle/mrc.c: Likewise.
    * gcc.target/arm/acle/mrc2.c: Likewise.
    * gcc.target/arm/acle/mrrc.c: Likewise.
    * gcc.target/arm/acle/mrrc2.c: Likewise.
    * gcc.target/arm/acle/stc.c: Likewise.
    * gcc.target/arm/acle/stc2.c: Likewise.
    * gcc.target/arm/acle/stc2l.c: Likewise.
    * gcc.target/arm/acle/stcl.c: Likewise.
    * lib/target-supports.exp:
    (check_effective_target_arm_coproc1_ok_nocache): Mention ldcl
    and stcl in the comment.
    (check_effective_target_arm_coproc2_ok_nocache): Allow Thumb-2 targets
    and disable Thumb-1 targets.
    (check_effective_target_arm_coproc3_ok_nocache): Likewise.
    (check_effective_target_arm_coproc4_ok_nocache): Likewise.

Acked-by: Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>

From-SVN: r252074
---
 gcc/testsuite/ChangeLog                   | 29 +++++++++++++++++++++++
 gcc/testsuite/gcc.target/arm/acle/cdp.c   |  3 ++-
 gcc/testsuite/gcc.target/arm/acle/cdp2.c  |  3 ++-
 gcc/testsuite/gcc.target/arm/acle/ldc.c   |  3 ++-
 gcc/testsuite/gcc.target/arm/acle/ldc2.c  |  3 ++-
 gcc/testsuite/gcc.target/arm/acle/ldc2l.c |  3 ++-
 gcc/testsuite/gcc.target/arm/acle/ldcl.c  |  3 ++-
 gcc/testsuite/gcc.target/arm/acle/mcr.c   |  3 ++-
 gcc/testsuite/gcc.target/arm/acle/mcr2.c  |  3 ++-
 gcc/testsuite/gcc.target/arm/acle/mcrr.c  |  3 ++-
 gcc/testsuite/gcc.target/arm/acle/mcrr2.c |  3 ++-
 gcc/testsuite/gcc.target/arm/acle/mrc.c   |  3 ++-
 gcc/testsuite/gcc.target/arm/acle/mrc2.c  |  3 ++-
 gcc/testsuite/gcc.target/arm/acle/mrrc.c  |  3 ++-
 gcc/testsuite/gcc.target/arm/acle/mrrc2.c |  3 ++-
 gcc/testsuite/gcc.target/arm/acle/stc.c   |  3 ++-
 gcc/testsuite/gcc.target/arm/acle/stc2.c  |  3 ++-
 gcc/testsuite/gcc.target/arm/acle/stc2l.c |  3 ++-
 gcc/testsuite/gcc.target/arm/acle/stcl.c  |  3 ++-
 gcc/testsuite/lib/target-supports.exp     | 11 +++++----
 20 files changed, 71 insertions(+), 23 deletions(-)

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index c7d26d66302..bb2bcbe4ac8 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,32 @@
+2017-09-13  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* gcc.target/arm/acle/cdp.c: Skip __ARM_FEATURE_COPROC check for
+	ARMv8-A and ARMv8-R.
+	* gcc.target/arm/acle/cdp2.c: Likewise.
+	* gcc.target/arm/acle/ldc.c: Likewise.
+	* gcc.target/arm/acle/ldc2.c: Likewise.
+	* gcc.target/arm/acle/ldc2l.c: Likewise.
+	* gcc.target/arm/acle/ldcl.c: Likewise.
+	* gcc.target/arm/acle/mcr.c: Likewise.
+	* gcc.target/arm/acle/mcr2.c: Likewise.
+	* gcc.target/arm/acle/mcrr.c: Likewise.
+	* gcc.target/arm/acle/mcrr2.c: Likewise.
+	* gcc.target/arm/acle/mrc.c: Likewise.
+	* gcc.target/arm/acle/mrc2.c: Likewise.
+	* gcc.target/arm/acle/mrrc.c: Likewise.
+	* gcc.target/arm/acle/mrrc2.c: Likewise.
+	* gcc.target/arm/acle/stc.c: Likewise.
+	* gcc.target/arm/acle/stc2.c: Likewise.
+	* gcc.target/arm/acle/stc2l.c: Likewise.
+	* gcc.target/arm/acle/stcl.c: Likewise.
+	* lib/target-supports.exp:
+	(check_effective_target_arm_coproc1_ok_nocache): Mention ldcl
+	and stcl in the comment.
+	(check_effective_target_arm_coproc2_ok_nocache): Allow Thumb-2 targets
+	and disable Thumb-1 targets.
+	(check_effective_target_arm_coproc3_ok_nocache): Likewise.
+	(check_effective_target_arm_coproc4_ok_nocache): Likewise.
+
 2017-09-13  Paolo Carlini  <paolo.carlini@oracle.com>
 
 	PR c++/47226
diff --git a/gcc/testsuite/gcc.target/arm/acle/cdp.c b/gcc/testsuite/gcc.target/arm/acle/cdp.c
index cebd8c4024e..cfa922a797c 100644
--- a/gcc/testsuite/gcc.target/arm/acle/cdp.c
+++ b/gcc/testsuite/gcc.target/arm/acle/cdp.c
@@ -5,7 +5,8 @@
 /* { dg-require-effective-target arm_coproc1_ok } */
 
 #include "arm_acle.h"
-#if (__ARM_FEATURE_COPROC & 0x1) == 0
+#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
+    && (__ARM_FEATURE_COPROC & 0x1) == 0
   #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
 #endif
 
diff --git a/gcc/testsuite/gcc.target/arm/acle/cdp2.c b/gcc/testsuite/gcc.target/arm/acle/cdp2.c
index 945d435d2fb..b18076c2627 100644
--- a/gcc/testsuite/gcc.target/arm/acle/cdp2.c
+++ b/gcc/testsuite/gcc.target/arm/acle/cdp2.c
@@ -5,7 +5,8 @@
 /* { dg-require-effective-target arm_coproc2_ok } */
 
 #include "arm_acle.h"
-#if (__ARM_FEATURE_COPROC & 0x2) == 0
+#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
+    && (__ARM_FEATURE_COPROC & 0x2) == 0
   #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
 #endif
 
diff --git a/gcc/testsuite/gcc.target/arm/acle/ldc.c b/gcc/testsuite/gcc.target/arm/acle/ldc.c
index cd57343208f..10c879f4a15 100644
--- a/gcc/testsuite/gcc.target/arm/acle/ldc.c
+++ b/gcc/testsuite/gcc.target/arm/acle/ldc.c
@@ -5,7 +5,8 @@
 /* { dg-require-effective-target arm_coproc1_ok } */
 
 #include "arm_acle.h"
-#if (__ARM_FEATURE_COPROC & 0x1) == 0
+#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
+    && (__ARM_FEATURE_COPROC & 0x1) == 0
   #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
 #endif
 
diff --git a/gcc/testsuite/gcc.target/arm/acle/ldc2.c b/gcc/testsuite/gcc.target/arm/acle/ldc2.c
index d7691e30d76..d561adacccf 100644
--- a/gcc/testsuite/gcc.target/arm/acle/ldc2.c
+++ b/gcc/testsuite/gcc.target/arm/acle/ldc2.c
@@ -5,7 +5,8 @@
 /* { dg-require-effective-target arm_coproc2_ok } */
 
 #include "arm_acle.h"
-#if (__ARM_FEATURE_COPROC & 0x2) == 0
+#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
+    && (__ARM_FEATURE_COPROC & 0x2) == 0
   #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
 #endif
 
diff --git a/gcc/testsuite/gcc.target/arm/acle/ldc2l.c b/gcc/testsuite/gcc.target/arm/acle/ldc2l.c
index 9ee63afa055..2c2a381c272 100644
--- a/gcc/testsuite/gcc.target/arm/acle/ldc2l.c
+++ b/gcc/testsuite/gcc.target/arm/acle/ldc2l.c
@@ -5,7 +5,8 @@
 /* { dg-require-effective-target arm_coproc2_ok } */
 
 #include "arm_acle.h"
-#if (__ARM_FEATURE_COPROC & 0x2) == 0
+#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
+    && (__ARM_FEATURE_COPROC & 0x2) == 0
   #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
 #endif
 
diff --git a/gcc/testsuite/gcc.target/arm/acle/ldcl.c b/gcc/testsuite/gcc.target/arm/acle/ldcl.c
index a6bfd9011dc..acbe5a3a2d0 100644
--- a/gcc/testsuite/gcc.target/arm/acle/ldcl.c
+++ b/gcc/testsuite/gcc.target/arm/acle/ldcl.c
@@ -5,7 +5,8 @@
 /* { dg-require-effective-target arm_coproc1_ok } */
 
 #include "arm_acle.h"
-#if (__ARM_FEATURE_COPROC & 0x1) == 0
+#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
+    && (__ARM_FEATURE_COPROC & 0x1) == 0
   #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
 #endif
 
diff --git a/gcc/testsuite/gcc.target/arm/acle/mcr.c b/gcc/testsuite/gcc.target/arm/acle/mcr.c
index 7095dcbc3ad..fb8e3c28ea1 100644
--- a/gcc/testsuite/gcc.target/arm/acle/mcr.c
+++ b/gcc/testsuite/gcc.target/arm/acle/mcr.c
@@ -5,7 +5,8 @@
 /* { dg-require-effective-target arm_coproc1_ok } */
 
 #include "arm_acle.h"
-#if (__ARM_FEATURE_COPROC & 0x1) == 0
+#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
+    && (__ARM_FEATURE_COPROC & 0x1) == 0
   #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
 #endif
 
diff --git a/gcc/testsuite/gcc.target/arm/acle/mcr2.c b/gcc/testsuite/gcc.target/arm/acle/mcr2.c
index 2a4b0ce4559..b83d9d7df8b 100644
--- a/gcc/testsuite/gcc.target/arm/acle/mcr2.c
+++ b/gcc/testsuite/gcc.target/arm/acle/mcr2.c
@@ -5,7 +5,8 @@
 /* { dg-require-effective-target arm_coproc2_ok } */
 
 #include "arm_acle.h"
-#if (__ARM_FEATURE_COPROC & 0x2) == 0
+#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
+    && (__ARM_FEATURE_COPROC & 0x2) == 0
   #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
 #endif
 
diff --git a/gcc/testsuite/gcc.target/arm/acle/mcrr.c b/gcc/testsuite/gcc.target/arm/acle/mcrr.c
index bcfbe1a4855..468dd96fb9b 100644
--- a/gcc/testsuite/gcc.target/arm/acle/mcrr.c
+++ b/gcc/testsuite/gcc.target/arm/acle/mcrr.c
@@ -5,7 +5,8 @@
 /* { dg-require-effective-target arm_coproc3_ok } */
 
 #include "arm_acle.h"
-#if (__ARM_FEATURE_COPROC & 0x4) == 0
+#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
+    && (__ARM_FEATURE_COPROC & 0x4) == 0
   #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
 #endif
 
diff --git a/gcc/testsuite/gcc.target/arm/acle/mcrr2.c b/gcc/testsuite/gcc.target/arm/acle/mcrr2.c
index afd07e67f21..1173ad06b53 100644
--- a/gcc/testsuite/gcc.target/arm/acle/mcrr2.c
+++ b/gcc/testsuite/gcc.target/arm/acle/mcrr2.c
@@ -5,7 +5,8 @@
 /* { dg-require-effective-target arm_coproc4_ok } */
 
 #include "arm_acle.h"
-#if (__ARM_FEATURE_COPROC & 0x8) == 0
+#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
+    && (__ARM_FEATURE_COPROC & 0x8) == 0
   #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
 #endif
 
diff --git a/gcc/testsuite/gcc.target/arm/acle/mrc.c b/gcc/testsuite/gcc.target/arm/acle/mrc.c
index 809b6c9c265..b09634f14f2 100644
--- a/gcc/testsuite/gcc.target/arm/acle/mrc.c
+++ b/gcc/testsuite/gcc.target/arm/acle/mrc.c
@@ -5,7 +5,8 @@
 /* { dg-require-effective-target arm_coproc1_ok } */
 
 #include "arm_acle.h"
-#if (__ARM_FEATURE_COPROC & 0x1) == 0
+#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
+    && (__ARM_FEATURE_COPROC & 0x1) == 0
   #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
 #endif
 
diff --git a/gcc/testsuite/gcc.target/arm/acle/mrc2.c b/gcc/testsuite/gcc.target/arm/acle/mrc2.c
index 4c06ea39b37..7dd691f0e49 100644
--- a/gcc/testsuite/gcc.target/arm/acle/mrc2.c
+++ b/gcc/testsuite/gcc.target/arm/acle/mrc2.c
@@ -5,7 +5,8 @@
 /* { dg-require-effective-target arm_coproc2_ok } */
 
 #include "arm_acle.h"
-#if (__ARM_FEATURE_COPROC & 0x2) == 0
+#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
+    && (__ARM_FEATURE_COPROC & 0x2) == 0
   #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
 #endif
 
diff --git a/gcc/testsuite/gcc.target/arm/acle/mrrc.c b/gcc/testsuite/gcc.target/arm/acle/mrrc.c
index 802de083d5c..c004660fadc 100644
--- a/gcc/testsuite/gcc.target/arm/acle/mrrc.c
+++ b/gcc/testsuite/gcc.target/arm/acle/mrrc.c
@@ -5,7 +5,8 @@
 /* { dg-require-effective-target arm_coproc3_ok } */
 
 #include "arm_acle.h"
-#if (__ARM_FEATURE_COPROC & 0x4) == 0
+#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
+    && (__ARM_FEATURE_COPROC & 0x4) == 0
   #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
 #endif
 
diff --git a/gcc/testsuite/gcc.target/arm/acle/mrrc2.c b/gcc/testsuite/gcc.target/arm/acle/mrrc2.c
index adf39563e29..b5d56da8f90 100644
--- a/gcc/testsuite/gcc.target/arm/acle/mrrc2.c
+++ b/gcc/testsuite/gcc.target/arm/acle/mrrc2.c
@@ -5,7 +5,8 @@
 /* { dg-require-effective-target arm_coproc4_ok } */
 
 #include "arm_acle.h"
-#if (__ARM_FEATURE_COPROC & 0x8) == 0
+#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
+    && (__ARM_FEATURE_COPROC & 0x8) == 0
   #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
 #endif
 
diff --git a/gcc/testsuite/gcc.target/arm/acle/stc.c b/gcc/testsuite/gcc.target/arm/acle/stc.c
index 2714f65787e..6155bd07dc3 100644
--- a/gcc/testsuite/gcc.target/arm/acle/stc.c
+++ b/gcc/testsuite/gcc.target/arm/acle/stc.c
@@ -5,7 +5,8 @@
 /* { dg-require-effective-target arm_coproc1_ok } */
 
 #include "arm_acle.h"
-#if (__ARM_FEATURE_COPROC & 0x1) == 0
+#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
+    && (__ARM_FEATURE_COPROC & 0x1) == 0
   #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
 #endif
 
diff --git a/gcc/testsuite/gcc.target/arm/acle/stc2.c b/gcc/testsuite/gcc.target/arm/acle/stc2.c
index 0a84652e0f0..57598d986a3 100644
--- a/gcc/testsuite/gcc.target/arm/acle/stc2.c
+++ b/gcc/testsuite/gcc.target/arm/acle/stc2.c
@@ -5,7 +5,8 @@
 /* { dg-require-effective-target arm_coproc2_ok } */
 
 #include "arm_acle.h"
-#if (__ARM_FEATURE_COPROC & 0x2) == 0
+#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
+    && (__ARM_FEATURE_COPROC & 0x2) == 0
   #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
 #endif
 
diff --git a/gcc/testsuite/gcc.target/arm/acle/stc2l.c b/gcc/testsuite/gcc.target/arm/acle/stc2l.c
index 2453d04ad72..0bca8dfa1f8 100644
--- a/gcc/testsuite/gcc.target/arm/acle/stc2l.c
+++ b/gcc/testsuite/gcc.target/arm/acle/stc2l.c
@@ -5,7 +5,8 @@
 /* { dg-require-effective-target arm_coproc2_ok } */
 
 #include "arm_acle.h"
-#if (__ARM_FEATURE_COPROC & 0x2) == 0
+#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
+    && (__ARM_FEATURE_COPROC & 0x2) == 0
   #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
 #endif
 
diff --git a/gcc/testsuite/gcc.target/arm/acle/stcl.c b/gcc/testsuite/gcc.target/arm/acle/stcl.c
index affdaa27982..be6270f2671 100644
--- a/gcc/testsuite/gcc.target/arm/acle/stcl.c
+++ b/gcc/testsuite/gcc.target/arm/acle/stcl.c
@@ -5,7 +5,8 @@
 /* { dg-require-effective-target arm_coproc1_ok } */
 
 #include "arm_acle.h"
-#if (__ARM_FEATURE_COPROC & 0x1) == 0
+#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
+    && (__ARM_FEATURE_COPROC & 0x1) == 0
   #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
 #endif
 
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 3ddc92ee273..2733c628100 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -8504,8 +8504,8 @@ proc check_effective_target_rdrand { } {
     } "-mrdrnd" ]
 }
 
-# Return 1 if the target supports coprocessor instructions: cdp, ldc, stc, mcr and
-# mrc.
+# Return 1 if the target supports coprocessor instructions: cdp, ldc, ldcl,
+# stc, stcl, mcr and mrc.
 proc check_effective_target_arm_coproc1_ok_nocache { } {
     if { ![istarget arm*-*-*] } {
 	return 0
@@ -8530,7 +8530,7 @@ proc check_effective_target_arm_coproc2_ok_nocache { } {
 	return 0
     }
     return [check_no_compiler_messages_nocache arm_coproc2_ok assembly {
-	#if __ARM_ARCH < 5
+	#if (__thumb__ && !__thumb2__) || __ARM_ARCH < 5
 	#error FOO
 	#endif
     }]
@@ -8549,7 +8549,8 @@ proc check_effective_target_arm_coproc3_ok_nocache { } {
 	return 0
     }
     return [check_no_compiler_messages_nocache arm_coproc3_ok assembly {
-	#if __ARM_ARCH < 6 && !defined (__ARM_ARCH_5TE__)
+	#if (__thumb__ && !__thumb2__) \
+	    || (__ARM_ARCH < 6 && !defined (__ARM_ARCH_5TE__))
 	#error FOO
 	#endif
     }]
@@ -8568,7 +8569,7 @@ proc check_effective_target_arm_coproc4_ok_nocache { } {
 	return 0
     }
     return [check_no_compiler_messages_nocache arm_coproc4_ok assembly {
-	#if __ARM_ARCH < 6
+	#if (__thumb__ && !__thumb2__) || __ARM_ARCH < 6
 	#error FOO
 	#endif
     }]