simplify-rtx.c (simplify_unary_operation_1): Use unsigned arithmetics in masking operations.
* simplify-rtx.c (simplify_unary_operation_1): Use unsigned arithmetics in masking operations. (simplify_const_unary_operation): Likewise. (simplify_binary_operation_1): Likewise. (simplify_const_binary_operation): Likewise. (simplify_const_relational_operation): Likewise. (simplify_ternary_operation): Likewise. (simplify_immed_subreg): Likewise. From-SVN: r165320
This commit is contained in:
Eric Botcazou
Eric Botcazou
parent
74b90fe2a0
commit
43c3628797
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@ -1,3 +1,14 @@
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2010-10-11 Eric Botcazou <ebotcazou@adacore.com>
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* simplify-rtx.c (simplify_unary_operation_1): Use unsigned arithmetics
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in masking operations.
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(simplify_const_unary_operation): Likewise.
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(simplify_binary_operation_1): Likewise.
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(simplify_const_binary_operation): Likewise.
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(simplify_const_relational_operation): Likewise.
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(simplify_ternary_operation): Likewise.
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(simplify_immed_subreg): Likewise.
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2010-10-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
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PR middle-end/45862
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@ -813,7 +813,7 @@ simplify_unary_operation_1 (enum rtx_code code, enum machine_mode mode, rtx op)
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than HOST_BITS_PER_WIDE_INT. */
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if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
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&& COMPARISON_P (op)
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&& ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
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&& (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
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return rtl_hooks.gen_lowpart_no_emit (mode, op);
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break;
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@ -912,7 +912,7 @@ simplify_unary_operation_1 (enum rtx_code code, enum machine_mode mode, rtx op)
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|| ((GET_MODE_BITSIZE (GET_MODE (op))
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<= HOST_BITS_PER_WIDE_INT)
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&& ((nonzero_bits (op, GET_MODE (op))
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& ((HOST_WIDE_INT) 1
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& ((unsigned HOST_WIDE_INT) 1
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<< (GET_MODE_BITSIZE (GET_MODE (op)) - 1)))
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== 0)))
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return op;
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@ -1330,7 +1330,8 @@ simplify_const_unary_operation (enum rtx_code code, enum machine_mode mode,
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val = arg0;
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}
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else if (GET_MODE_BITSIZE (op_mode) < HOST_BITS_PER_WIDE_INT)
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val = arg0 & ~((HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (op_mode));
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val = arg0 & ~((unsigned HOST_WIDE_INT) (-1)
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<< GET_MODE_BITSIZE (op_mode));
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else
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return 0;
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break;
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@ -1349,10 +1350,12 @@ simplify_const_unary_operation (enum rtx_code code, enum machine_mode mode,
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else if (GET_MODE_BITSIZE (op_mode) < HOST_BITS_PER_WIDE_INT)
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{
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val
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= arg0 & ~((HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (op_mode));
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if (val
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& ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (op_mode) - 1)))
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val -= (HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (op_mode);
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= arg0 & ~((unsigned HOST_WIDE_INT) (-1)
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<< GET_MODE_BITSIZE (op_mode));
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if (val & ((unsigned HOST_WIDE_INT) 1
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<< (GET_MODE_BITSIZE (op_mode) - 1)))
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val
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-= (unsigned HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (op_mode);
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}
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else
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return 0;
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@ -1505,9 +1508,9 @@ simplify_const_unary_operation (enum rtx_code code, enum machine_mode mode,
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{
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lv = l1 & GET_MODE_MASK (op_mode);
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if (GET_MODE_BITSIZE (op_mode) < HOST_BITS_PER_WIDE_INT
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&& (lv & ((HOST_WIDE_INT) 1
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&& (lv & ((unsigned HOST_WIDE_INT) 1
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<< (GET_MODE_BITSIZE (op_mode) - 1))) != 0)
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lv -= (HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (op_mode);
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lv -= (unsigned HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (op_mode);
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hv = HWI_SIGN_EXTEND (lv);
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}
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@ -1613,13 +1616,14 @@ simplify_const_unary_operation (enum rtx_code code, enum machine_mode mode,
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/* Test against the signed lower bound. */
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if (width > HOST_BITS_PER_WIDE_INT)
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{
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th = (HOST_WIDE_INT) -1 << (width - HOST_BITS_PER_WIDE_INT - 1);
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th = (unsigned HOST_WIDE_INT) (-1)
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<< (width - HOST_BITS_PER_WIDE_INT - 1);
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tl = 0;
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}
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else
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{
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th = -1;
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tl = (HOST_WIDE_INT) -1 << (width - 1);
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tl = (unsigned HOST_WIDE_INT) (-1) << (width - 1);
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}
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real_from_integer (&t, VOIDmode, tl, th, 0);
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if (REAL_VALUES_LESS (x, t))
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@ -2197,7 +2201,7 @@ simplify_binary_operation_1 (enum rtx_code code, enum machine_mode mode,
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/* Convert multiply by constant power of two into shift unless
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we are still generating RTL. This test is a kludge. */
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if (CONST_INT_P (trueop1)
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&& (val = exact_log2 (INTVAL (trueop1))) >= 0
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&& (val = exact_log2 (UINTVAL (trueop1))) >= 0
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/* If the mode is larger than the host word size, and the
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uppermost bit is set, then this isn't a power of two due
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to implicit sign extension. */
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@ -2263,7 +2267,7 @@ simplify_binary_operation_1 (enum rtx_code code, enum machine_mode mode,
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if (trueop1 == CONST0_RTX (mode))
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return op0;
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if (CONST_INT_P (trueop1)
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&& ((INTVAL (trueop1) & GET_MODE_MASK (mode))
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&& ((UINTVAL (trueop1) & GET_MODE_MASK (mode))
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== GET_MODE_MASK (mode)))
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return op1;
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if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
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@ -2278,7 +2282,7 @@ simplify_binary_operation_1 (enum rtx_code code, enum machine_mode mode,
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/* (ior A C) is C if all bits of A that might be nonzero are on in C. */
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if (CONST_INT_P (op1)
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&& GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
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&& (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
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&& (nonzero_bits (op0, mode) & ~UINTVAL (op1)) == 0)
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return op1;
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/* Canonicalize (X & C1) | C2. */
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@ -2367,12 +2371,12 @@ simplify_binary_operation_1 (enum rtx_code code, enum machine_mode mode,
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&& GET_CODE (op0) == AND
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&& CONST_INT_P (XEXP (op0, 1))
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&& CONST_INT_P (op1)
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&& (INTVAL (XEXP (op0, 1)) & INTVAL (op1)) != 0)
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&& (UINTVAL (XEXP (op0, 1)) & UINTVAL (op1)) != 0)
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return simplify_gen_binary (IOR, mode,
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simplify_gen_binary
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(AND, mode, XEXP (op0, 0),
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GEN_INT (INTVAL (XEXP (op0, 1))
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& ~INTVAL (op1))),
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GEN_INT (UINTVAL (XEXP (op0, 1))
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& ~UINTVAL (op1))),
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op1);
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/* If OP0 is (ashiftrt (plus ...) C), it might actually be
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@ -2405,7 +2409,7 @@ simplify_binary_operation_1 (enum rtx_code code, enum machine_mode mode,
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if (trueop1 == CONST0_RTX (mode))
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return op0;
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if (CONST_INT_P (trueop1)
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&& ((INTVAL (trueop1) & GET_MODE_MASK (mode))
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&& ((UINTVAL (trueop1) & GET_MODE_MASK (mode))
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== GET_MODE_MASK (mode)))
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return simplify_gen_unary (NOT, mode, op0, mode);
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if (rtx_equal_p (trueop0, trueop1)
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@ -2549,7 +2553,7 @@ simplify_binary_operation_1 (enum rtx_code code, enum machine_mode mode,
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&& CONST_INT_P (trueop1)
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&& GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
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&& (~GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))
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& INTVAL (trueop1)) == 0)
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& UINTVAL (trueop1)) == 0)
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{
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enum machine_mode imode = GET_MODE (XEXP (op0, 0));
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tem = simplify_gen_binary (AND, imode, XEXP (op0, 0),
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@ -2630,8 +2634,8 @@ simplify_binary_operation_1 (enum rtx_code code, enum machine_mode mode,
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(A +- N) & M -> A & M. */
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if (CONST_INT_P (trueop1)
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&& GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
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&& ~INTVAL (trueop1)
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&& (INTVAL (trueop1) & (INTVAL (trueop1) + 1)) == 0
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&& ~UINTVAL (trueop1)
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&& (UINTVAL (trueop1) & (UINTVAL (trueop1) + 1)) == 0
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&& (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS))
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{
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rtx pmop[2];
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@ -2641,7 +2645,7 @@ simplify_binary_operation_1 (enum rtx_code code, enum machine_mode mode,
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pmop[1] = XEXP (op0, 1);
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if (CONST_INT_P (pmop[1])
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&& (INTVAL (pmop[1]) & INTVAL (trueop1)) == 0)
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&& (UINTVAL (pmop[1]) & UINTVAL (trueop1)) == 0)
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return simplify_gen_binary (AND, mode, pmop[0], op1);
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for (which = 0; which < 2; which++)
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@ -2651,14 +2655,14 @@ simplify_binary_operation_1 (enum rtx_code code, enum machine_mode mode,
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{
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case AND:
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if (CONST_INT_P (XEXP (tem, 1))
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&& (INTVAL (XEXP (tem, 1)) & INTVAL (trueop1))
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== INTVAL (trueop1))
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&& (UINTVAL (XEXP (tem, 1)) & UINTVAL (trueop1))
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== UINTVAL (trueop1))
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pmop[which] = XEXP (tem, 0);
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break;
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case IOR:
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case XOR:
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if (CONST_INT_P (XEXP (tem, 1))
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&& (INTVAL (XEXP (tem, 1)) & INTVAL (trueop1)) == 0)
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&& (UINTVAL (XEXP (tem, 1)) & UINTVAL (trueop1)) == 0)
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pmop[which] = XEXP (tem, 0);
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break;
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default:
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@ -2704,7 +2708,7 @@ simplify_binary_operation_1 (enum rtx_code code, enum machine_mode mode,
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return rtl_hooks.gen_lowpart_no_emit (mode, op0);
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/* Convert divide by power of two into shift. */
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if (CONST_INT_P (trueop1)
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&& (val = exact_log2 (INTVAL (trueop1))) > 0)
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&& (val = exact_log2 (UINTVAL (trueop1))) > 0)
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return simplify_gen_binary (LSHIFTRT, mode, op0, GEN_INT (val));
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break;
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@ -2786,7 +2790,7 @@ simplify_binary_operation_1 (enum rtx_code code, enum machine_mode mode,
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}
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/* Implement modulus by power of two as AND. */
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if (CONST_INT_P (trueop1)
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&& exact_log2 (INTVAL (trueop1)) > 0)
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&& exact_log2 (UINTVAL (trueop1)) > 0)
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return simplify_gen_binary (AND, mode, op0,
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GEN_INT (INTVAL (op1) - 1));
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break;
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@ -2817,7 +2821,7 @@ simplify_binary_operation_1 (enum rtx_code code, enum machine_mode mode,
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return op0;
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/* Rotating ~0 always results in ~0. */
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if (CONST_INT_P (trueop0) && width <= HOST_BITS_PER_WIDE_INT
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&& (unsigned HOST_WIDE_INT) INTVAL (trueop0) == GET_MODE_MASK (mode)
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&& UINTVAL (trueop0) == GET_MODE_MASK (mode)
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&& ! side_effects_p (op1))
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return op0;
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canonicalize_shift:
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@ -2863,7 +2867,7 @@ simplify_binary_operation_1 (enum rtx_code code, enum machine_mode mode,
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case SMIN:
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if (width <= HOST_BITS_PER_WIDE_INT
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&& CONST_INT_P (trueop1)
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&& INTVAL (trueop1) == (HOST_WIDE_INT) 1 << (width -1)
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&& UINTVAL (trueop1) == (unsigned HOST_WIDE_INT) 1 << (width -1)
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&& ! side_effects_p (op0))
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return op1;
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if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
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@ -2876,8 +2880,7 @@ simplify_binary_operation_1 (enum rtx_code code, enum machine_mode mode,
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case SMAX:
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if (width <= HOST_BITS_PER_WIDE_INT
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&& CONST_INT_P (trueop1)
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&& ((unsigned HOST_WIDE_INT) INTVAL (trueop1)
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== (unsigned HOST_WIDE_INT) GET_MODE_MASK (mode) >> 1)
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&& (UINTVAL (trueop1) == GET_MODE_MASK (mode) >> 1)
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&& ! side_effects_p (op0))
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return op1;
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if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
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@ -3469,16 +3472,16 @@ simplify_const_binary_operation (enum rtx_code code, enum machine_mode mode,
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if (width < HOST_BITS_PER_WIDE_INT)
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{
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arg0 &= ((HOST_WIDE_INT) 1 << width) - 1;
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arg1 &= ((HOST_WIDE_INT) 1 << width) - 1;
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arg0 &= ((unsigned HOST_WIDE_INT) 1 << width) - 1;
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arg1 &= ((unsigned HOST_WIDE_INT) 1 << width) - 1;
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arg0s = arg0;
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if (arg0s & ((HOST_WIDE_INT) 1 << (width - 1)))
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arg0s |= ((HOST_WIDE_INT) (-1) << width);
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if (arg0s & ((unsigned HOST_WIDE_INT) 1 << (width - 1)))
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arg0s |= ((unsigned HOST_WIDE_INT) (-1) << width);
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arg1s = arg1;
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if (arg1s & ((HOST_WIDE_INT) 1 << (width - 1)))
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arg1s |= ((HOST_WIDE_INT) (-1) << width);
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if (arg1s & ((unsigned HOST_WIDE_INT) 1 << (width - 1)))
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arg1s |= ((unsigned HOST_WIDE_INT) (-1) << width);
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}
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else
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{
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@ -3504,7 +3507,8 @@ simplify_const_binary_operation (enum rtx_code code, enum machine_mode mode,
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case DIV:
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if (arg1s == 0
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|| (arg0s == (HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
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|| ((unsigned HOST_WIDE_INT) arg0s
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== (unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
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&& arg1s == -1))
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return 0;
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val = arg0s / arg1s;
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@ -3512,7 +3516,8 @@ simplify_const_binary_operation (enum rtx_code code, enum machine_mode mode,
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case MOD:
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if (arg1s == 0
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|| (arg0s == (HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
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|| ((unsigned HOST_WIDE_INT) arg0s
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== (unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
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&& arg1s == -1))
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return 0;
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val = arg0s % arg1s;
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@ -3520,7 +3525,8 @@ simplify_const_binary_operation (enum rtx_code code, enum machine_mode mode,
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case UDIV:
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if (arg1 == 0
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|| (arg0s == (HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
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|| ((unsigned HOST_WIDE_INT) arg0s
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== (unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
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&& arg1s == -1))
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return 0;
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val = (unsigned HOST_WIDE_INT) arg0 / arg1;
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@ -3528,7 +3534,8 @@ simplify_const_binary_operation (enum rtx_code code, enum machine_mode mode,
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case UMOD:
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if (arg1 == 0
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|| (arg0s == (HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
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|| ((unsigned HOST_WIDE_INT) arg0s
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== (unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
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&& arg1s == -1))
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return 0;
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val = (unsigned HOST_WIDE_INT) arg0 % arg1;
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@ -3567,7 +3574,7 @@ simplify_const_binary_operation (enum rtx_code code, enum machine_mode mode,
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/* Sign-extend the result for arithmetic right shifts. */
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if (code == ASHIFTRT && arg0s < 0 && arg1 > 0)
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val |= ((HOST_WIDE_INT) -1) << (width - arg1);
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val |= ((unsigned HOST_WIDE_INT) (-1)) << (width - arg1);
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break;
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case ROTATERT:
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@ -4447,14 +4454,14 @@ simplify_const_relational_operation (enum rtx_code code,
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we have to sign or zero-extend the values. */
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if (width != 0 && width < HOST_BITS_PER_WIDE_INT)
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{
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l0u &= ((HOST_WIDE_INT) 1 << width) - 1;
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l1u &= ((HOST_WIDE_INT) 1 << width) - 1;
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l0u &= ((unsigned HOST_WIDE_INT) 1 << width) - 1;
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l1u &= ((unsigned HOST_WIDE_INT) 1 << width) - 1;
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if (l0s & ((HOST_WIDE_INT) 1 << (width - 1)))
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l0s |= ((HOST_WIDE_INT) (-1) << width);
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if (l0s & ((unsigned HOST_WIDE_INT) 1 << (width - 1)))
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l0s |= ((unsigned HOST_WIDE_INT) (-1) << width);
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if (l1s & ((HOST_WIDE_INT) 1 << (width - 1)))
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l1s |= ((HOST_WIDE_INT) (-1) << width);
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if (l1s & ((unsigned HOST_WIDE_INT) 1 << (width - 1)))
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l1s |= ((unsigned HOST_WIDE_INT) (-1) << width);
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}
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if (width != 0 && width <= HOST_BITS_PER_WIDE_INT)
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h0u = h1u = 0, h0s = HWI_SIGN_EXTEND (l0s), h1s = HWI_SIGN_EXTEND (l1s);
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@ -4607,8 +4614,9 @@ simplify_const_relational_operation (enum rtx_code code,
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{
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int sign_bitnum = GET_MODE_BITSIZE (mode) - 1;
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int has_sign = (HOST_BITS_PER_WIDE_INT >= sign_bitnum
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&& (INTVAL (inner_const)
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& ((HOST_WIDE_INT) 1 << sign_bitnum)));
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&& (UINTVAL (inner_const)
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& ((unsigned HOST_WIDE_INT) 1
|
||||
<< sign_bitnum)));
|
||||
|
||||
switch (code)
|
||||
{
|
||||
|
|
@ -4713,22 +4721,22 @@ simplify_ternary_operation (enum rtx_code code, enum machine_mode mode,
|
|||
&& width <= (unsigned) HOST_BITS_PER_WIDE_INT)
|
||||
{
|
||||
/* Extracting a bit-field from a constant */
|
||||
HOST_WIDE_INT val = INTVAL (op0);
|
||||
unsigned HOST_WIDE_INT val = UINTVAL (op0);
|
||||
|
||||
if (BITS_BIG_ENDIAN)
|
||||
val >>= (GET_MODE_BITSIZE (op0_mode)
|
||||
- INTVAL (op2) - INTVAL (op1));
|
||||
val >>= GET_MODE_BITSIZE (op0_mode) - INTVAL (op2) - INTVAL (op1);
|
||||
else
|
||||
val >>= INTVAL (op2);
|
||||
|
||||
if (HOST_BITS_PER_WIDE_INT != INTVAL (op1))
|
||||
{
|
||||
/* First zero-extend. */
|
||||
val &= ((HOST_WIDE_INT) 1 << INTVAL (op1)) - 1;
|
||||
val &= ((unsigned HOST_WIDE_INT) 1 << INTVAL (op1)) - 1;
|
||||
/* If desired, propagate sign bit. */
|
||||
if (code == SIGN_EXTRACT
|
||||
&& (val & ((HOST_WIDE_INT) 1 << (INTVAL (op1) - 1))))
|
||||
val |= ~ (((HOST_WIDE_INT) 1 << INTVAL (op1)) - 1);
|
||||
&& (val & ((unsigned HOST_WIDE_INT) 1 << (INTVAL (op1) - 1)))
|
||||
!= 0)
|
||||
val |= ~ (((unsigned HOST_WIDE_INT) 1 << INTVAL (op1)) - 1);
|
||||
}
|
||||
|
||||
/* Clear the bits that don't belong in our mode,
|
||||
|
|
@ -4736,9 +4744,9 @@ simplify_ternary_operation (enum rtx_code code, enum machine_mode mode,
|
|||
So we get either a reasonable negative value or a reasonable
|
||||
unsigned value for this mode. */
|
||||
if (width < HOST_BITS_PER_WIDE_INT
|
||||
&& ((val & ((HOST_WIDE_INT) (-1) << (width - 1)))
|
||||
!= ((HOST_WIDE_INT) (-1) << (width - 1))))
|
||||
val &= ((HOST_WIDE_INT) 1 << width) - 1;
|
||||
&& ((val & ((unsigned HOST_WIDE_INT) (-1) << (width - 1)))
|
||||
!= ((unsigned HOST_WIDE_INT) (-1) << (width - 1))))
|
||||
val &= ((unsigned HOST_WIDE_INT) 1 << width) - 1;
|
||||
|
||||
return gen_int_mode (val, mode);
|
||||
}
|
||||
|
|
@ -5096,10 +5104,10 @@ simplify_immed_subreg (enum machine_mode outermode, rtx op,
|
|||
for (i = 0;
|
||||
i < HOST_BITS_PER_WIDE_INT && i < elem_bitsize;
|
||||
i += value_bit)
|
||||
lo |= (HOST_WIDE_INT)(*vp++ & value_mask) << i;
|
||||
lo |= (unsigned HOST_WIDE_INT)(*vp++ & value_mask) << i;
|
||||
for (; i < elem_bitsize; i += value_bit)
|
||||
hi |= ((HOST_WIDE_INT)(*vp++ & value_mask)
|
||||
<< (i - HOST_BITS_PER_WIDE_INT));
|
||||
hi |= (unsigned HOST_WIDE_INT)(*vp++ & value_mask)
|
||||
<< (i - HOST_BITS_PER_WIDE_INT);
|
||||
|
||||
/* immed_double_const doesn't call trunc_int_for_mode. I don't
|
||||
know why. */
|
||||
|
|
@ -5152,9 +5160,9 @@ simplify_immed_subreg (enum machine_mode outermode, rtx op,
|
|||
for (i = 0;
|
||||
i < HOST_BITS_PER_WIDE_INT && i < elem_bitsize;
|
||||
i += value_bit)
|
||||
f.data.low |= (HOST_WIDE_INT)(*vp++ & value_mask) << i;
|
||||
f.data.low |= (unsigned HOST_WIDE_INT)(*vp++ & value_mask) << i;
|
||||
for (; i < elem_bitsize; i += value_bit)
|
||||
f.data.high |= ((HOST_WIDE_INT)(*vp++ & value_mask)
|
||||
f.data.high |= ((unsigned HOST_WIDE_INT)(*vp++ & value_mask)
|
||||
<< (i - HOST_BITS_PER_WIDE_INT));
|
||||
|
||||
elems[elem] = CONST_FIXED_FROM_FIXED_VALUE (f, outer_submode);
|
||||
|
|
|
|||
Loading…
Reference in New Issue