Fix some typos and coding style violations.
Backport from mainline 2012-08-28 Walter Lee <walt@tilera.com> * confg/tilegx/tilegx.md: Fix code style. (*zero_extendsidi_truncdisi): Fix typo. * config/tilegx/tilegx.c: Fix code style. (tilegx_function_profiler): Fix typo. From-SVN: r190740
This commit is contained in:
Walter Lee
Walter Lee
parent
59798f281c
commit
43d4e561b3
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@ -1,3 +1,12 @@
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2012-08-28 Walter Lee <walt@tilera.com>
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Backport from mainline
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2012-08-28 Walter Lee <walt@tilera.com>
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* confg/tilegx/tilegx.md: Fix code style.
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(*zero_extendsidi_truncdisi): Fix typo.
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* config/tilegx/tilegx.c: Fix code style.
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(tilegx_function_profiler): Fix typo.
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2012-08-27 Walter Lee <walt@tilera.com>
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Backport from mainline
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@ -144,7 +144,7 @@ tilegx_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
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}
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/* TARGET_MODE_REP_EXTENDED. */
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/* Implement TARGET_MODE_REP_EXTENDED. */
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static int
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tilegx_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
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{
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@ -405,7 +405,7 @@ tilegx_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
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addr = create_tmp_var (ptr_type_node, "va_arg");
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/* if an object is dynamically sized, a pointer to it is passed
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/* If an object is dynamically sized, a pointer to it is passed
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instead of the object itself. */
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pass_by_reference_p = pass_by_reference (NULL, TYPE_MODE (type), type,
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false);
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@ -457,11 +457,11 @@ tilegx_rtx_costs (rtx x, int code, int outer_code, int opno, int *total,
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{
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case CONST_INT:
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/* If this is an 8-bit constant, return zero since it can be
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used nearly anywhere with no cost. If it is a valid operand
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for an ADD or AND, likewise return 0 if we know it will be
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used in that context. Otherwise, return 2 since it might be
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used there later. All other constants take at least two
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insns. */
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used nearly anywhere with no cost. If it is a valid operand
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for an ADD or AND, likewise return 0 if we know it will be
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used in that context. Otherwise, return 2 since it might be
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used there later. All other constants take at least two
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insns. */
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if (satisfies_constraint_I (x))
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{
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*total = 0;
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@ -506,8 +506,8 @@ tilegx_rtx_costs (rtx x, int code, int outer_code, int opno, int *total,
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case MEM:
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/* If outer-code was a sign or zero extension, a cost of
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COSTS_N_INSNS (1) was already added in, so account for
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that. */
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COSTS_N_INSNS (1) was already added in, so account for
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that. */
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if (outer_code == ZERO_EXTEND || outer_code == SIGN_EXTEND)
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*total = COSTS_N_INSNS (1);
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else
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@ -635,7 +635,7 @@ tilegx_rtx_costs (rtx x, int code, int outer_code, int opno, int *total,
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static rtx
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create_temp_reg_if_possible (enum machine_mode mode, rtx default_reg)
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{
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return can_create_pseudo_p ()? gen_reg_rtx (mode) : default_reg;
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return can_create_pseudo_p () ? gen_reg_rtx (mode) : default_reg;
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}
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@ -1335,8 +1335,8 @@ tilegx_simd_int (rtx num, enum machine_mode mode)
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/* Returns true iff VAL can be moved into a register in one
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instruction. And if it can, it emits the code to move the
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constant into DEST_REG.
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instruction. And if it can, it emits the code to move the constant
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into DEST_REG.
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If THREE_WIDE_ONLY is true, this insists on an instruction that
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works in a bundle containing three instructions. */
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@ -1396,7 +1396,7 @@ tilegx_bitfield_operand_p (HOST_WIDE_INT n, int *first_bit, int *last_bit)
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continue;
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/* See if x is a power of two minus one, i.e. only consecutive 1
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bits starting from bit 0. */
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bits starting from bit 0. */
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if ((x & (x + 1)) == 0)
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{
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if (first_bit != NULL)
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@ -1480,8 +1480,8 @@ expand_set_cint64 (rtx dest_reg, rtx src_val)
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if (expand_set_cint64_one_inst (temp, r, three_wide_only))
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{
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/* 0xFFFFFFFFFFA5FFFF becomes:
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movei temp, 0xFFFFFFFFFFFFFFA5
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rotli dest, temp, 16 */
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movei temp, 0xFFFFFFFFFFFFFFA5
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rotli dest, temp, 16 */
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emit_move_insn (dest_reg,
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gen_rtx_ROTATE (DImode, temp, GEN_INT (count)));
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return;
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@ -1530,11 +1530,11 @@ expand_set_cint64 (rtx dest_reg, rtx src_val)
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unsigned HOST_WIDE_INT leftover;
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/* Recursively create the constant above the lowest 16 zero
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bits. */
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bits. */
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expand_set_cint64 (temp, GEN_INT (val >> shift));
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/* See if we can easily insert the remaining bits, or if we need
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to fall through to the more general case. */
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to fall through to the more general case. */
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leftover = val - ((val >> shift) << shift);
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if (leftover == 0)
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{
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@ -1571,8 +1571,8 @@ expand_set_cint64 (rtx dest_reg, rtx src_val)
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else
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{
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/* Set as many high 16-bit blocks as we can with a single
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instruction. We'll insert the remaining 16-bit blocks
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below. */
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instruction. We'll insert the remaining 16-bit blocks
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below. */
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for (shift = 16;; shift += 16)
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{
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gcc_assert (shift < 64);
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@ -1615,10 +1615,10 @@ tilegx_expand_set_const64 (rtx op0, rtx op1)
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if (CONST_INT_P (op1))
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{
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/* TODO: I don't know if we want to split large constants
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now, or wait until later (with a define_split).
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now, or wait until later (with a define_split).
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Does splitting early help CSE? Does it harm other
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optimizations that might fold loads? */
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Does splitting early help CSE? Does it harm other
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optimizations that might fold loads? */
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expand_set_cint64 (op0, op1);
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}
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else
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@ -1716,7 +1716,7 @@ tilegx_expand_unaligned_load (rtx dest_reg, rtx mem, HOST_WIDE_INT bitsize,
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if (bitsize == 2 * BITS_PER_UNIT && (bit_offset % BITS_PER_UNIT) == 0)
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{
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/* When just loading a two byte value, we can load the two bytes
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individually and combine them efficiently. */
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individually and combine them efficiently. */
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mem_lo = adjust_address (mem, QImode, byte_offset);
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mem_hi = adjust_address (mem, QImode, byte_offset + 1);
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@ -2053,6 +2053,7 @@ tilegx_expand_const_muldi (rtx op0, rtx op1, long long multiplier)
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return false;
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}
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/* Expand the muldi pattern. */
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bool
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tilegx_expand_muldi (rtx op0, rtx op1, rtx op2)
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@ -2227,7 +2228,7 @@ tilegx_emit_setcc_internal (rtx res, enum rtx_code code, rtx op0, rtx op1,
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case GEU:
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case GTU:
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/* We do not have these compares, so we reverse the
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operands. */
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operands. */
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swap = true;
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break;
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@ -2322,7 +2323,7 @@ tilegx_emit_cc_test (enum rtx_code code, rtx op0, rtx op1,
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case GEU:
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case GTU:
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/* These must be reversed (except NE, but let's
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canonicalize). */
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canonicalize). */
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code = reverse_condition (code);
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branch_code = EQ;
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break;
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@ -2352,7 +2353,7 @@ tilegx_emit_cc_test (enum rtx_code code, rtx op0, rtx op1,
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|| (REG_P (op0) && REG_POINTER (op0))))
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{
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/* TODO: Use a SIMD add immediate to hit zero for tiled
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constants in a single instruction. */
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constants in a single instruction. */
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if (GET_MODE (op0) != DImode)
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{
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/* Convert to DImode so we can use addli. Note that
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@ -3400,47 +3401,47 @@ tilegx_expand_builtin (tree exp,
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opnum = nonvoid;
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FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
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{
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const struct insn_operand_data *insn_op;
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{
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const struct insn_operand_data *insn_op;
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if (arg == error_mark_node)
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return NULL_RTX;
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if (opnum > MAX_BUILTIN_ARGS)
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return NULL_RTX;
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if (arg == error_mark_node)
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return NULL_RTX;
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if (opnum > MAX_BUILTIN_ARGS)
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return NULL_RTX;
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insn_op = &insn_data[icode].operand[opnum];
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insn_op = &insn_data[icode].operand[opnum];
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op[opnum] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
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op[opnum] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
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if (!(*insn_op->predicate) (op[opnum], insn_op->mode))
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{
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enum machine_mode opmode = insn_op->mode;
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if (!(*insn_op->predicate) (op[opnum], insn_op->mode))
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{
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enum machine_mode opmode = insn_op->mode;
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/* pointer_operand and pmode_register_operand operands do
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not specify a mode, so use the operand's mode instead
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(which should always be right by the time we get here,
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except for constants, which are VOIDmode). */
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if (opmode == VOIDmode)
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{
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enum machine_mode m = GET_MODE (op[opnum]);
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gcc_assert (m == Pmode || m == VOIDmode);
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opmode = Pmode;
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}
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/* pointer_operand and pmode_register_operand operands do
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not specify a mode, so use the operand's mode instead
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(which should always be right by the time we get here,
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except for constants, which are VOIDmode). */
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if (opmode == VOIDmode)
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{
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enum machine_mode m = GET_MODE (op[opnum]);
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gcc_assert (m == Pmode || m == VOIDmode);
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opmode = Pmode;
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}
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op[opnum] = copy_to_mode_reg (opmode, op[opnum]);
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}
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op[opnum] = copy_to_mode_reg (opmode, op[opnum]);
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}
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if (!(*insn_op->predicate) (op[opnum], insn_op->mode))
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{
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/* We still failed to meet the predicate even after moving
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into a register. Assume we needed an immediate. */
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error_at (EXPR_LOCATION (exp),
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"operand must be an immediate of the right size");
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return const0_rtx;
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}
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if (!(*insn_op->predicate) (op[opnum], insn_op->mode))
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{
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/* We still failed to meet the predicate even after moving
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into a register. Assume we needed an immediate. */
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error_at (EXPR_LOCATION (exp),
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"operand must be an immediate of the right size");
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return const0_rtx;
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}
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opnum++;
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}
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opnum++;
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}
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if (nonvoid)
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{
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@ -3874,7 +3875,7 @@ tilegx_expand_prologue (void)
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REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY;
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/* fp holds a copy of the incoming sp, in case we need to store
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it. */
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it. */
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sp_copy_regno = HARD_FRAME_POINTER_REGNUM;
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}
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else if (!tilegx_current_function_is_leaf ())
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@ -4069,7 +4070,7 @@ tilegx_expand_epilogue (bool sibcall_p)
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if (frame_pointer_needed)
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{
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/* Restore the old stack pointer by copying from the frame
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pointer. */
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pointer. */
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if (TARGET_32BIT)
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{
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insn = emit_insn (gen_sp_restore_32bit (stack_pointer_rtx,
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@ -4266,6 +4267,7 @@ get_jump_target (rtx branch)
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return 0;
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}
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/* Implement TARGET_SCHED_ADJUST_COST. */
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static int
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tilegx_sched_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
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@ -4311,37 +4313,37 @@ tilegx_gen_bundles (void)
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{
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basic_block bb;
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FOR_EACH_BB (bb)
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{
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rtx insn, next;
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rtx end = NEXT_INSN (BB_END (bb));
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{
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rtx insn, next;
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rtx end = NEXT_INSN (BB_END (bb));
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for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn; insn = next)
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{
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next = next_insn_to_bundle (NEXT_INSN (insn), end);
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for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn; insn = next)
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{
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next = next_insn_to_bundle (NEXT_INSN (insn), end);
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/* Never wrap {} around inline asm. */
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if (GET_CODE (PATTERN (insn)) != ASM_INPUT)
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{
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if (next == NULL_RTX || GET_MODE (next) == TImode
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/* NOTE: The scheduler incorrectly believes a call
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insn can execute in the same cycle as the insn
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after the call. This is of course impossible.
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Really we need to fix the scheduler somehow, so
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the code after the call gets scheduled
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optimally. */
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|| CALL_P (insn))
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{
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/* Mark current insn as the end of a bundle. */
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PUT_MODE (insn, QImode);
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}
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else
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{
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/* Mark it as part of a bundle. */
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PUT_MODE (insn, SImode);
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}
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}
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}
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}
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/* Never wrap {} around inline asm. */
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if (GET_CODE (PATTERN (insn)) != ASM_INPUT)
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{
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if (next == NULL_RTX || GET_MODE (next) == TImode
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/* NOTE: The scheduler incorrectly believes a call
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insn can execute in the same cycle as the insn
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after the call. This is of course impossible.
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Really we need to fix the scheduler somehow, so
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the code after the call gets scheduled
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optimally. */
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|| CALL_P (insn))
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{
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/* Mark current insn as the end of a bundle. */
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PUT_MODE (insn, QImode);
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}
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else
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{
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/* Mark it as part of a bundle. */
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PUT_MODE (insn, SImode);
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}
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}
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}
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}
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}
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@ -4906,7 +4908,7 @@ tilegx_print_operand (FILE *file, rtx x, int code)
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switch (code)
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{
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case 'c':
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/* Print the compare operator opcode for conditional moves. */
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/* Print the compare operator opcode for conditional moves. */
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switch (GET_CODE (x))
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{
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case EQ:
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@ -4921,7 +4923,7 @@ tilegx_print_operand (FILE *file, rtx x, int code)
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return;
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case 'C':
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/* Print the compare operator opcode for conditional moves. */
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/* Print the compare operator opcode for conditional moves. */
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switch (GET_CODE (x))
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{
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case EQ:
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@ -4937,7 +4939,7 @@ tilegx_print_operand (FILE *file, rtx x, int code)
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case 'd':
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{
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/* Print the compare operator opcode for conditional moves. */
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/* Print the compare operator opcode for conditional moves. */
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switch (GET_CODE (x))
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{
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case EQ:
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@ -4954,7 +4956,7 @@ tilegx_print_operand (FILE *file, rtx x, int code)
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case 'D':
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{
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/* Print the compare operator opcode for conditional moves. */
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/* Print the compare operator opcode for conditional moves. */
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switch (GET_CODE (x))
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{
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case EQ:
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@ -5196,7 +5198,7 @@ tilegx_print_operand (FILE *file, rtx x, int code)
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case 'r':
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/* In this case we need a register. Use 'zero' if the operand
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is const0_rtx. */
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is const0_rtx. */
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if (x == const0_rtx
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|| (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
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{
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@ -5283,7 +5285,7 @@ tilegx_final_prescan_insn (rtx insn)
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}
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/* While emitting asm, are we currently inside '{' for a bundle? */
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/* While emitting asm, are we currently inside '{' for a bundle? */
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static bool tilegx_in_bundle = false;
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/* Implement ASM_OUTPUT_OPCODE. Prepend/append curly braces as
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@ -5345,7 +5347,7 @@ tilegx_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
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"\t{\n"
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"\tmove\tr10, lr\n"
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"\tjal\t%s\n"
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"\t}\t\n", MCOUNT_NAME);
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"\t}\n", MCOUNT_NAME);
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}
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tilegx_in_bundle = false;
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@ -5458,7 +5460,7 @@ tilegx_file_end (void)
|
|||
#undef TARGET_BUILTIN_DECL
|
||||
#define TARGET_BUILTIN_DECL tilegx_builtin_decl
|
||||
|
||||
#undef TARGET_EXPAND_BUILTIN
|
||||
#undef TARGET_EXPAND_BUILTIN
|
||||
#define TARGET_EXPAND_BUILTIN tilegx_expand_builtin
|
||||
|
||||
#undef TARGET_CONDITIONAL_REGISTER_USAGE
|
||||
|
|
|
|||
|
|
@ -408,7 +408,7 @@
|
|||
(ss_minus "")
|
||||
(us_minus "")
|
||||
])
|
||||
|
||||
|
||||
;; <s> is the load/store extension suffix.
|
||||
(define_code_attr s [(zero_extend "u")
|
||||
(sign_extend "s")])
|
||||
|
|
@ -816,11 +816,11 @@
|
|||
bit_width = INTVAL (operands[2]);
|
||||
bit_offset = INTVAL (operands[3]);
|
||||
|
||||
/* Reject bitfields that can be done with a normal load */
|
||||
/* Reject bitfields that can be done with a normal load. */
|
||||
if (MEM_ALIGN (operands[1]) >= bit_offset + bit_width)
|
||||
FAIL;
|
||||
|
||||
/* The value in memory cannot span more than 8 bytes. */
|
||||
/* The value in memory cannot span more than 8 bytes. */
|
||||
first_byte_offset = bit_offset / BITS_PER_UNIT;
|
||||
last_byte_offset = (bit_offset + bit_width - 1) / BITS_PER_UNIT;
|
||||
if (last_byte_offset - first_byte_offset > 7)
|
||||
|
|
@ -845,7 +845,6 @@
|
|||
HOST_WIDE_INT bit_width = INTVAL (operands[2]);
|
||||
HOST_WIDE_INT bit_offset = INTVAL (operands[3]);
|
||||
|
||||
|
||||
if (MEM_P (operands[1]))
|
||||
{
|
||||
HOST_WIDE_INT first_byte_offset, last_byte_offset;
|
||||
|
|
@ -853,11 +852,11 @@
|
|||
if (GET_MODE (operands[1]) != QImode)
|
||||
FAIL;
|
||||
|
||||
/* Reject bitfields that can be done with a normal load */
|
||||
/* Reject bitfields that can be done with a normal load. */
|
||||
if (MEM_ALIGN (operands[1]) >= bit_offset + bit_width)
|
||||
FAIL;
|
||||
|
||||
/* The value in memory cannot span more than 8 bytes. */
|
||||
/* The value in memory cannot span more than 8 bytes. */
|
||||
first_byte_offset = bit_offset / BITS_PER_UNIT;
|
||||
last_byte_offset = (bit_offset + bit_width - 1) / BITS_PER_UNIT;
|
||||
if (last_byte_offset - first_byte_offset > 7)
|
||||
|
|
@ -873,7 +872,7 @@
|
|||
|
||||
if (bit_offset == 0)
|
||||
{
|
||||
/* Extracting the low bits is just a bitwise AND. */
|
||||
/* Extracting the low bits is just a bitwise AND. */
|
||||
HOST_WIDE_INT mask = ((HOST_WIDE_INT)1 << bit_width) - 1;
|
||||
emit_insn (gen_anddi3 (operands[0], operands[1], GEN_INT (mask)));
|
||||
DONE;
|
||||
|
|
@ -891,7 +890,7 @@
|
|||
[(set (match_operand:DI 0 "register_operand" "")
|
||||
(const:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
|
||||
UNSPEC_HW2_LAST)))])
|
||||
|
||||
|
||||
;; Second step of the 3-insn sequence to materialize a symbolic
|
||||
;; address.
|
||||
(define_expand "mov_address_step2"
|
||||
|
|
@ -947,7 +946,7 @@
|
|||
"%1 = . + 8\n\tlnk\t%0"
|
||||
[(set_attr "type" "Y1")])
|
||||
|
||||
;; First step of the 3-insn sequence to materialize a position
|
||||
;; The next three patterns are used to to materialize a position
|
||||
;; independent address by adding the difference of two labels to a
|
||||
;; base label in the text segment, assuming that the difference fits
|
||||
;; in 32 signed bits.
|
||||
|
|
@ -959,10 +958,6 @@
|
|||
UNSPEC_HW1_LAST_PCREL)))]
|
||||
"flag_pic")
|
||||
|
||||
;; Second step of the 3-insn sequence to materialize a position
|
||||
;; independent address by adding the difference of two labels to a
|
||||
;; base label in the text segment, assuming that the difference fits
|
||||
;; in 32 signed bits.
|
||||
(define_expand "mov_pcrel_step2<bitsuffix>"
|
||||
[(set (match_operand:I48MODE 0 "register_operand" "")
|
||||
(unspec:I48MODE
|
||||
|
|
@ -973,11 +968,7 @@
|
|||
UNSPEC_HW0_PCREL))]
|
||||
UNSPEC_INSN_ADDR_SHL16INSLI))]
|
||||
"flag_pic")
|
||||
|
||||
;; Third step of the 3-insn sequence to materialize a position
|
||||
;; independent address by adding the difference of two labels to a base
|
||||
;; label in the text segment, assuming that the difference fits in 32
|
||||
;; signed bits.
|
||||
|
||||
(define_insn "mov_pcrel_step3<bitsuffix>"
|
||||
[(set (match_operand:I48MODE 0 "register_operand" "=r")
|
||||
(unspec:I48MODE [(match_operand:I48MODE 1 "reg_or_0_operand" "rO")
|
||||
|
|
@ -1335,7 +1326,6 @@
|
|||
DONE;
|
||||
})
|
||||
|
||||
|
||||
(define_expand "subdf3"
|
||||
[(set (match_operand:DF 0 "register_operand" "")
|
||||
(minus:DF (match_operand:DF 1 "register_operand" "")
|
||||
|
|
@ -1708,7 +1698,6 @@
|
|||
"ctz\t%0, %r1"
|
||||
[(set_attr "type" "Y0")])
|
||||
|
||||
|
||||
(define_insn "popcount<mode>2"
|
||||
[(set (match_operand:I48MODE 0 "register_operand" "=r")
|
||||
(popcount:I48MODE (match_operand:DI 1 "reg_or_0_operand" "rO")))]
|
||||
|
|
@ -1937,7 +1926,7 @@
|
|||
(define_insn "*zero_extendsidi_truncdisi"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(zero_extend:DI
|
||||
(truncate:SI (match_operand:DI 1 "reg_or_0_operand" "0"))))]
|
||||
(truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO"))))]
|
||||
""
|
||||
"v4int_l\t%0, zero, %r1"
|
||||
[(set_attr "type" "X01")])
|
||||
|
|
@ -2008,7 +1997,7 @@
|
|||
shruxi\t%0, %r1, %2
|
||||
shrux\t%0, %r1, %r2"
|
||||
[(set_attr "type" "X01,X01")])
|
||||
|
||||
|
||||
(define_insn "*lshrsi_truncdisi2"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(lshiftrt:SI
|
||||
|
|
@ -2213,7 +2202,8 @@
|
|||
;; Loops
|
||||
;;
|
||||
|
||||
;; Define the subtract-one-and-jump insns so loop.c knows what to generate.
|
||||
;; Define the subtract-one-and-jump insns so loop.c knows what to
|
||||
;; generate.
|
||||
(define_expand "doloop_end"
|
||||
[(use (match_operand 0 "" "")) ;; loop pseudo
|
||||
(use (match_operand 1 "" "")) ;; iterations; zero if unknown
|
||||
|
|
@ -2481,8 +2471,8 @@
|
|||
[(set_attr "type" "*,*,X01")])
|
||||
|
||||
;; Used for move sp, r52, to pop a stack frame. We need to make sure
|
||||
;; that stack frame memory operations have been issued before we do this.
|
||||
;; TODO: see above TODO.
|
||||
;; that stack frame memory operations have been issued before we do
|
||||
;; this. TODO: see above TODO.
|
||||
(define_insn "sp_restore<bitsuffix>"
|
||||
[(set (match_operand:I48MODE 0 "register_operand" "=r")
|
||||
(match_operand:I48MODE 1 "register_operand" "r"))
|
||||
|
|
|
|||
Loading…
Reference in New Issue