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[AArch64] More aarch64_endian_lane_rtx 

r254466 failed to update some uses of ENDIAN_LANE_N that were added after
the patch was initially written, which meant that we were treating the
mode number as an element count.

2017-11-13  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* config/aarch64/aarch64-simd.md (aarch64_store_lane0<mode>):
	Upddate call to ENDIAN_LANE_N.
	(aarch64_<sur>dot_lane<vsi2qi>): Use aarch64_endian_lane_rtx.
	(aarch64_<sur>dot_laneq<vsi2qi>): Likewise.
	(*aarch64_simd_vec_copy_lane<mode>): Update calls to ENDIAN_LANE_N
	and use aarch64_endian_lane_rtx.
	(*aarch64_simd_vec_copy_lane_<vswap_width_name><mode>): Likewise.

From-SVN: r254670
This commit is contained in:
Richard Sandiford 2017-11-13 08:21:16 +00:00 committed by Richard Sandiford
parent 41a0d8d4c0
commit 441b4d0fa2
2 changed files with 18 additions and 10 deletions
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10
gcc/ChangeLog
View File

@ -1,3 +1,13 @@
2017-11-13 Richard Sandiford <richard.sandiford@linaro.org>
* config/aarch64/aarch64-simd.md (aarch64_store_lane0<mode>):
Upddate call to ENDIAN_LANE_N.
(aarch64_<sur>dot_lane<vsi2qi>): Use aarch64_endian_lane_rtx.
(aarch64_<sur>dot_laneq<vsi2qi>): Likewise.
(*aarch64_simd_vec_copy_lane<mode>): Update calls to ENDIAN_LANE_N
and use aarch64_endian_lane_rtx.
(*aarch64_simd_vec_copy_lane_<vswap_width_name><mode>): Likewise.
2017-11-12 Tom de Vries <tom@codesourcery.com>
* config/riscv/riscv.h (ASM_OUTPUT_LABELREF): Wrap in do {} while (0).

18
gcc/config/aarch64/aarch64-simd.md
View File

@ -173,7 +173,7 @@
(vec_select:<VEL> (match_operand:VALL_F16 1 "register_operand" "w")
(parallel [(match_operand 2 "const_int_operand" "n")])))]
"TARGET_SIMD
&& ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])) == 0"
&& ENDIAN_LANE_N (<nunits>, INTVAL (operands[2])) == 0"
"str\\t%<Vetype>1, %0"
[(set_attr "type" "neon_store1_1reg<q>")]
)
@ -450,8 +450,7 @@
DOTPROD)))]
"TARGET_DOTPROD"
{
operands[4]
= GEN_INT (ENDIAN_LANE_N (V8QImode, INTVAL (operands[4])));
operands[4] = aarch64_endian_lane_rtx (V8QImode, INTVAL (operands[4]));
return "<sur>dot\\t%0.<Vtype>, %2.<Vdottype>, %3.4b[%4]";
}
[(set_attr "type" "neon_dot")]
@ -466,8 +465,7 @@
DOTPROD)))]
"TARGET_DOTPROD"
{
operands[4]
= GEN_INT (ENDIAN_LANE_N (V16QImode, INTVAL (operands[4])));
operands[4] = aarch64_endian_lane_rtx (V16QImode, INTVAL (operands[4]));
return "<sur>dot\\t%0.<Vtype>, %2.<Vdottype>, %3.4b[%4]";
}
[(set_attr "type" "neon_dot")]
@ -734,9 +732,9 @@
(match_operand:SI 2 "immediate_operand" "i")))]
"TARGET_SIMD"
{
int elt = ENDIAN_LANE_N (<MODE>mode, exact_log2 (INTVAL (operands[2])));
int elt = ENDIAN_LANE_N (<nunits>, exact_log2 (INTVAL (operands[2])));
operands[2] = GEN_INT (HOST_WIDE_INT_1 << elt);
operands[4] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[4])));
operands[4] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[4]));
return "ins\t%0.<Vetype>[%p2], %3.<Vetype>[%4]";
}
@ -755,10 +753,10 @@
(match_operand:SI 2 "immediate_operand" "i")))]
"TARGET_SIMD"
{
int elt = ENDIAN_LANE_N (<MODE>mode, exact_log2 (INTVAL (operands[2])));
int elt = ENDIAN_LANE_N (<nunits>, exact_log2 (INTVAL (operands[2])));
operands[2] = GEN_INT (HOST_WIDE_INT_1 << elt);
operands[4] = GEN_INT (ENDIAN_LANE_N (<VSWAP_WIDTH>mode,
INTVAL (operands[4])));
operands[4] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode,
INTVAL (operands[4]));
return "ins\t%0.<Vetype>[%p2], %3.<Vetype>[%4]";
}