[AArch64] More aarch64_endian_lane_rtx
r254466 failed to update some uses of ENDIAN_LANE_N that were added after the patch was initially written, which meant that we were treating the mode number as an element count. 2017-11-13 Richard Sandiford <richard.sandiford@linaro.org> gcc/ * config/aarch64/aarch64-simd.md (aarch64_store_lane0<mode>): Upddate call to ENDIAN_LANE_N. (aarch64_<sur>dot_lane<vsi2qi>): Use aarch64_endian_lane_rtx. (aarch64_<sur>dot_laneq<vsi2qi>): Likewise. (*aarch64_simd_vec_copy_lane<mode>): Update calls to ENDIAN_LANE_N and use aarch64_endian_lane_rtx. (*aarch64_simd_vec_copy_lane_<vswap_width_name><mode>): Likewise. From-SVN: r254670
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@ -1,3 +1,13 @@
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2017-11-13 Richard Sandiford <richard.sandiford@linaro.org>
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* config/aarch64/aarch64-simd.md (aarch64_store_lane0<mode>):
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Upddate call to ENDIAN_LANE_N.
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(aarch64_<sur>dot_lane<vsi2qi>): Use aarch64_endian_lane_rtx.
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(aarch64_<sur>dot_laneq<vsi2qi>): Likewise.
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(*aarch64_simd_vec_copy_lane<mode>): Update calls to ENDIAN_LANE_N
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and use aarch64_endian_lane_rtx.
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(*aarch64_simd_vec_copy_lane_<vswap_width_name><mode>): Likewise.
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2017-11-12 Tom de Vries <tom@codesourcery.com>
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* config/riscv/riscv.h (ASM_OUTPUT_LABELREF): Wrap in do {} while (0).
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@ -173,7 +173,7 @@
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(vec_select:<VEL> (match_operand:VALL_F16 1 "register_operand" "w")
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(parallel [(match_operand 2 "const_int_operand" "n")])))]
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"TARGET_SIMD
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&& ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])) == 0"
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&& ENDIAN_LANE_N (<nunits>, INTVAL (operands[2])) == 0"
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"str\\t%<Vetype>1, %0"
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[(set_attr "type" "neon_store1_1reg<q>")]
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)
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@ -450,8 +450,7 @@
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DOTPROD)))]
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"TARGET_DOTPROD"
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{
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operands[4]
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= GEN_INT (ENDIAN_LANE_N (V8QImode, INTVAL (operands[4])));
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operands[4] = aarch64_endian_lane_rtx (V8QImode, INTVAL (operands[4]));
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return "<sur>dot\\t%0.<Vtype>, %2.<Vdottype>, %3.4b[%4]";
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}
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[(set_attr "type" "neon_dot")]
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@ -466,8 +465,7 @@
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DOTPROD)))]
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"TARGET_DOTPROD"
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{
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operands[4]
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= GEN_INT (ENDIAN_LANE_N (V16QImode, INTVAL (operands[4])));
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operands[4] = aarch64_endian_lane_rtx (V16QImode, INTVAL (operands[4]));
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return "<sur>dot\\t%0.<Vtype>, %2.<Vdottype>, %3.4b[%4]";
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}
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[(set_attr "type" "neon_dot")]
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@ -734,9 +732,9 @@
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(match_operand:SI 2 "immediate_operand" "i")))]
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"TARGET_SIMD"
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{
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int elt = ENDIAN_LANE_N (<MODE>mode, exact_log2 (INTVAL (operands[2])));
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int elt = ENDIAN_LANE_N (<nunits>, exact_log2 (INTVAL (operands[2])));
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operands[2] = GEN_INT (HOST_WIDE_INT_1 << elt);
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operands[4] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[4])));
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operands[4] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[4]));
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return "ins\t%0.<Vetype>[%p2], %3.<Vetype>[%4]";
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}
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@ -755,10 +753,10 @@
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(match_operand:SI 2 "immediate_operand" "i")))]
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"TARGET_SIMD"
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{
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int elt = ENDIAN_LANE_N (<MODE>mode, exact_log2 (INTVAL (operands[2])));
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int elt = ENDIAN_LANE_N (<nunits>, exact_log2 (INTVAL (operands[2])));
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operands[2] = GEN_INT (HOST_WIDE_INT_1 << elt);
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operands[4] = GEN_INT (ENDIAN_LANE_N (<VSWAP_WIDTH>mode,
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INTVAL (operands[4])));
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operands[4] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode,
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INTVAL (operands[4]));
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return "ins\t%0.<Vetype>[%p2], %3.<Vetype>[%4]";
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}
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