[AArch64][2/2] Add constrain to address offset in storewb_pair/loadwb_pair insns
Add a pridicate to check whether the const offset is valid. For 32-bit variant: -256 <= offset <= 252 For 64-bit variant: -512 <= offset <= 504 2014-07-29 Renlin Li <renlin.li@arm.com> 2014-07-29 Jiong Wang <jiong.wang@arm.com> gcc/ * config/aarch64/aarch64.c (offset_7bit_signed_scaled_p): Rename to aarch64_offset_7bit_signed_scaled_p, remove static and use it. * config/aarch64/aarch64-protos.h (aarch64_offset_7bit_signed_scaled_p): Declaration. * config/aarch64/predicates.md (aarch64_mem_pair_offset): Define new predicate. * config/aarch64/aarch64.md (loadwb_pair, storewb_pair): Use aarch64_mem_pair_offset. From-SVN: r213487
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@ -1,3 +1,15 @@
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2014-08-01 Renlin Li <renlin.li@arm.com>
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2014-08-01 Jiong Wang <jiong.wang@arm.com>
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* config/aarch64/aarch64.c (offset_7bit_signed_scaled_p): Rename to
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aarch64_offset_7bit_signed_scaled_p, remove static and use it.
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* config/aarch64/aarch64-protos.h (aarch64_offset_7bit_signed_scaled_p):
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Declaration.
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* config/aarch64/predicates.md (aarch64_mem_pair_offset): Define new
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predicate.
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* config/aarch64/aarch64.md (loadwb_pair, storewb_pair): Use
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aarch64_mem_pair_offset.
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2014-08-01 Jiong Wang <jiong.wang@arm.com>
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* config/aarch64/aarch64.md (loadwb_pair<GPI:mode>_<P:mode>): Fix
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@ -194,6 +194,7 @@ bool aarch64_modes_tieable_p (enum machine_mode mode1,
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bool aarch64_move_imm (HOST_WIDE_INT, enum machine_mode);
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bool aarch64_mov_operand_p (rtx, enum aarch64_symbol_context,
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enum machine_mode);
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bool aarch64_offset_7bit_signed_scaled_p (enum machine_mode, HOST_WIDE_INT);
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char *aarch64_output_scalar_simd_mov_immediate (rtx, enum machine_mode);
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char *aarch64_output_simd_mov_immediate (rtx, enum machine_mode, unsigned);
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bool aarch64_pad_arg_upward (enum machine_mode, const_tree);
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@ -3193,8 +3193,8 @@ aarch64_classify_index (struct aarch64_address_info *info, rtx x,
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return false;
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}
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static inline bool
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offset_7bit_signed_scaled_p (enum machine_mode mode, HOST_WIDE_INT offset)
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bool
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aarch64_offset_7bit_signed_scaled_p (enum machine_mode mode, HOST_WIDE_INT offset)
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{
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return (offset >= -64 * GET_MODE_SIZE (mode)
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&& offset < 64 * GET_MODE_SIZE (mode)
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@ -3266,12 +3266,12 @@ aarch64_classify_address (struct aarch64_address_info *info,
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We conservatively require an offset representable in either mode.
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*/
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if (mode == TImode || mode == TFmode)
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return (offset_7bit_signed_scaled_p (mode, offset)
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return (aarch64_offset_7bit_signed_scaled_p (mode, offset)
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&& offset_9bit_signed_unscaled_p (mode, offset));
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if (outer_code == PARALLEL)
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return ((GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)
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&& offset_7bit_signed_scaled_p (mode, offset));
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&& aarch64_offset_7bit_signed_scaled_p (mode, offset));
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else
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return (offset_9bit_signed_unscaled_p (mode, offset)
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|| offset_12bit_unsigned_scaled_p (mode, offset));
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@ -3326,12 +3326,12 @@ aarch64_classify_address (struct aarch64_address_info *info,
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We conservatively require an offset representable in either mode.
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*/
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if (mode == TImode || mode == TFmode)
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return (offset_7bit_signed_scaled_p (mode, offset)
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return (aarch64_offset_7bit_signed_scaled_p (mode, offset)
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&& offset_9bit_signed_unscaled_p (mode, offset));
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if (outer_code == PARALLEL)
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return ((GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)
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&& offset_7bit_signed_scaled_p (mode, offset));
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&& aarch64_offset_7bit_signed_scaled_p (mode, offset));
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else
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return offset_9bit_signed_unscaled_p (mode, offset);
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}
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@ -1022,7 +1022,7 @@
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[(parallel
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[(set (match_operand:P 0 "register_operand" "=k")
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(plus:P (match_operand:P 1 "register_operand" "0")
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(match_operand:P 4 "const_int_operand" "n")))
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(match_operand:P 4 "aarch64_mem_pair_offset" "n")))
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(set (match_operand:GPI 2 "register_operand" "=r")
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(mem:GPI (match_dup 1)))
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(set (match_operand:GPI 3 "register_operand" "=r")
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@ -1037,7 +1037,7 @@
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[(parallel
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[(set (match_operand:P 0 "register_operand" "=k")
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(plus:P (match_operand:P 1 "register_operand" "0")
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(match_operand:P 4 "const_int_operand" "n")))
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(match_operand:P 4 "aarch64_mem_pair_offset" "n")))
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(set (match_operand:GPF 2 "register_operand" "=w")
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(mem:GPF (match_dup 1)))
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(set (match_operand:GPF 3 "register_operand" "=w")
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@ -1054,7 +1054,7 @@
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[(parallel
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[(set (match_operand:P 0 "register_operand" "=&k")
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(plus:P (match_operand:P 1 "register_operand" "0")
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(match_operand:P 4 "const_int_operand" "n")))
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(match_operand:P 4 "aarch64_mem_pair_offset" "n")))
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(set (mem:GPI (plus:P (match_dup 0)
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(match_dup 4)))
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(match_operand:GPI 2 "register_operand" "r"))
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@ -1070,7 +1070,7 @@
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[(parallel
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[(set (match_operand:P 0 "register_operand" "=&k")
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(plus:P (match_operand:P 1 "register_operand" "0")
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(match_operand:P 4 "const_int_operand" "n")))
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(match_operand:P 4 "aarch64_mem_pair_offset" "n")))
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(set (mem:GPF (plus:P (match_dup 0)
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(match_dup 4)))
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(match_operand:GPF 2 "register_operand" "w"))
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@ -123,6 +123,10 @@
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(match_test "INTVAL (op) != 0
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&& (unsigned) exact_log2 (INTVAL (op)) < 64")))
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(define_predicate "aarch64_mem_pair_offset"
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(and (match_code "const_int")
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(match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))")))
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(define_predicate "aarch64_mem_pair_operand"
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(and (match_code "mem")
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(match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), PARALLEL,
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