(seqdi_special_trunc, snedi_special_trunc,
seqsi_special_extend, snesi_special_extend): Delete uses of SUBREG. Make compare modes match modes of operands. (snesi_zero_extend, snedi_zero_trunc_sp32, snedi_zero_trunc_sp64, seqsi_zero_extend, seqdi_zero_trunc_sp32, seqdi_zero_trunc_sp64): New patterns. From-SVN: r10646
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482cfaf8a5
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44965badd0
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@ -370,8 +370,8 @@
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(xor:DI (match_operand:DI 1 "register_operand" "")
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(match_operand:DI 2 "register_operand" "")))
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(parallel [(set (match_operand:SI 0 "register_operand" "")
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(eq:SI (subreg:SI (match_dup 3) 0) (const_int 0)))
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(clobber (reg:CC 0))])]
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(eq:DI (match_dup 3) (const_int 0)))
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(clobber (reg:CCX 0))])]
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""
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"{ operands[3] = gen_reg_rtx (DImode); }")
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@ -380,31 +380,31 @@
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(xor:DI (match_operand:DI 1 "register_operand" "")
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(match_operand:DI 2 "register_operand" "")))
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(parallel [(set (match_operand:SI 0 "register_operand" "")
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(ne:SI (subreg:SI (match_dup 3) 0) (const_int 0)))
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(clobber (reg:CC 0))])]
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""
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"{ operands[3] = gen_reg_rtx (DImode); }")
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(define_expand "seqsi_special_extend"
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[(set (subreg:SI (match_dup 3) 0)
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(xor:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "register_operand" "")))
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(parallel [(set (match_operand:DI 0 "register_operand" "")
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(eq:DI (match_dup 3) (const_int 0)))
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(clobber (reg:CCX 0))])]
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""
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"{ operands[3] = gen_reg_rtx (DImode); }")
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(define_expand "snesi_special_extend"
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[(set (subreg:SI (match_dup 3) 0)
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(xor:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "register_operand" "")))
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(parallel [(set (match_operand:DI 0 "register_operand" "")
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(ne:DI (match_dup 3) (const_int 0)))
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(clobber (reg:CCX 0))])]
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""
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"{ operands[3] = gen_reg_rtx (DImode); }")
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(define_expand "seqsi_special_extend"
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[(set (match_dup 3)
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(xor:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "register_operand" "")))
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(parallel [(set (match_operand:DI 0 "register_operand" "")
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(eq:SI (match_dup 3) (const_int 0)))
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(clobber (reg:CC 0))])]
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"TARGET_V9"
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"{ operands[3] = gen_reg_rtx (SImode); }")
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(define_expand "snesi_special_extend"
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[(set (match_dup 3)
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(xor:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "register_operand" "")))
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(parallel [(set (match_operand:DI 0 "register_operand" "")
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(ne:SI (match_dup 3) (const_int 0)))
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(clobber (reg:CC 0))])]
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"TARGET_V9"
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"{ operands[3] = gen_reg_rtx (SImode); }")
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;; ??? v9: Operand 0 needs a mode, so SImode was chosen.
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;; However, the code handles both SImode and DImode.
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(define_expand "seq"
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@ -824,6 +824,16 @@
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[(set_attr "type" "unary")
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(set_attr "length" "2")])
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(define_insn "*snesi_zero_extend"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(ne:SI (match_operand:SI 1 "register_operand" "r")
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(const_int 0)))
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(clobber (reg:CC 0))]
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"TARGET_V9"
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"subcc %%g0,%1,%%g0\;addx %%g0,0,%0"
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[(set_attr "type" "unary")
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(set_attr "length" "2")])
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(define_insn "*snedi_zero"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(ne:DI (match_operand:DI 1 "register_operand" "r")
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@ -844,6 +854,26 @@
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[(set_attr "type" "unary")
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(set_attr "length" "2")])
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(define_insn "*snedi_zero_trunc_sp32"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(ne:DI (match_operand:DI 1 "register_operand" "r")
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(const_int 0)))
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(clobber (reg:CCX 0))]
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"! TARGET_V9"
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"xor %1,%R1,%0\;subcc %%g0,%0,%%g0\;addx %%g0,0,%0"
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[(set_attr "type" "unary")
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(set_attr "length" "3")])
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(define_insn "*snedi_zero_trunc_sp64"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(ne:DI (match_operand:DI 1 "register_operand" "r")
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(const_int 0)))
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(clobber (reg:CCX 0))]
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"TARGET_V9"
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"mov 0,%0\;movrnz %1,1,%0"
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[(set_attr "type" "unary")
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(set_attr "length" "2")])
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(define_insn "*seqsi_zero"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(eq:SI (match_operand:SI 1 "register_operand" "r")
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@ -864,6 +894,16 @@
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[(set_attr "type" "unary")
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(set_attr "length" "2")])
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(define_insn "*seqsi_zero_extend"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(eq:SI (match_operand:SI 1 "register_operand" "r")
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(const_int 0)))
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(clobber (reg:CC 0))]
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"TARGET_V9"
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"subcc %%g0,%1,%%g0\;subx %%g0,-1,%0"
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[(set_attr "type" "unary")
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(set_attr "length" "2")])
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(define_insn "*seqdi_zero"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(eq:DI (match_operand:DI 1 "register_operand" "r")
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@ -884,6 +924,26 @@
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[(set_attr "type" "unary")
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(set_attr "length" "2")])
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(define_insn "*seqdi_zero_trunc_sp32"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(eq:DI (match_operand:DI 1 "register_operand" "r")
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(const_int 0)))
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(clobber (reg:CCX 0))]
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"! TARGET_V9"
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"xor %1,%R1,%0\;subcc %%g0,%0,%%g0\;subx %%g0,-1,%0"
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[(set_attr "type" "unary")
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(set_attr "length" "3")])
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(define_insn "*seqdi_zero_trunc_sp64"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(eq:DI (match_operand:DI 1 "register_operand" "r")
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(const_int 0)))
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(clobber (reg:CCX 0))]
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"TARGET_V9"
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"mov 0,%0\;movrz %1,1,%0"
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[(set_attr "type" "unary")
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(set_attr "length" "2")])
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;; We can also do (x + (i == 0)) and related, so put them in.
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;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
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;; versions for v9.
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