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invoke.texi: Add cpu_type power6x (RS/6000 and PowerPC Options): Add -mmfpgpr.

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* doc/invoke.texi: Add cpu_type power6x
	(RS/6000 and PowerPC Options): Add -mmfpgpr.
	* config.gcc: Add cpu_type power6x.
	* configure.ac: Add test for mf{t,f}gpr instructions.
	(HAVE_AS_MFPGPR): New.
	* config.in: Regenerate.
	* configure: Regenerate.
	* config/rs6000/aix52.h (ASM_CPU_SPEC): Add power6x.
	* config/rs6000/rs6000.md (define_attr "type"): Add insert_dword,
	shift,trap,var_shift_rotate,cntlz,exts, var_delayed_compare, mffgpr
	and mftgpr attributes.
	(define_attr "cpu"): Add power6.
	Change instruction sequences to use new attributes.
	(floatsidf2,fix_truncdfsi2): use TARGET_MFPGPR.
	(fix_truncdfsi2_mfpgpr): New.
	(floatsidf_ppc64_mfpgpr): New.
	(floatsidf_ppc64): Added !TARGET_MFPGPR condition.
	(movdf_hardfloat64_mfpgpr,movdi_mfpgpr): New.
	(movdf_hardfloat64): Added !TARGET_MFPGPR condition.
	(movdi_internal64): Added !TARGET_MFPGPR and related conditions.
	(fix_truncdfsi2): Use gpc_reg_operand constraint.
	* config/rs6000/{6xx.md,power4.md,8540.md,603.md,mpc.md,
	7xx.md,rios2.md,7450.md,440.md,rios1.md,rs64.md,power5.md,40x.md}:
	Add descriptions for insert_dword, shift,trap,var_shift_rotate,
	cntlz,exts and var_delayed_compare.
	* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Define
	_ARCH_PWR6X, if features enabled.
	* config/rs6000/rs6000.opt (mmfpgpr): New.
	* config/rs6000/rs6000.c (rs6000_align_branch_targets): New variable.
	(cached_can_issue_more): New variable.
	(processor_costs): Add power6_cost.
	(rs6000_sched_init): New function.
	(is_dispatch_slot_restricted): Deleted.
	(set_to_load_agen): New function.
	(is_load_insn,is_store_insn): New functions.
	(adjacent_mem_locations): New function.
	(insn_must_be_first_in_group): New function.
	(insn_must_be_last_in_group): New function.
	(rs6000_sched_reorder): New function.
	(rs6000_sched_reorder2): New function.
	(TARGET_SCHED_INIT,TARGET_SCHED_REORDER,
	TARGET_SCHED_REORDER2): Define.
	(processor_target_table): Use PROCESSOR_POWER6 for power6.
	Add power6x. Add MASK_MFPGPR for power6x.
	(POWERPC_MASKS): Add MASK_MFPGPR.
	(rs6000_override_options): Set rs6000_always_hint to false
	for power6.  Set rs6000_align_branch_targets. Replace
	rs6000_sched_groups check with rs6000_align_branch_targets.
	Use PROCESSOR_POWER6.
	(last_scheduled_insn): New variable.
	(load_store_pendulum): New variable.
	(rs6000_variable_issue): Set last_scheduled_insn and
	cached_can_issue_more.
	(rs6000_adjust_cost): Add power6 cost adjustments.
	(rs6000_adjust_priority): Replace is_dispatch_slot_restricted
	with insn_must_be_first_in_group. Add power6 priority adjustments.
	(rs6000_issue_rate): Add CPU_POWER6.
	(insn_terminates_group_p): Use insn_must_be_{first,last}_in_group.
	* config/rs6000/rs6000.h (processor_type): Add PROCESSOR_POWER6.
	(TARGET_MFPGPR): New.
	(SECONDARY_MEMORY_NEEDED): Use TARGET_MFPGPR.
	(ASM_CPU_SPEC): Add power6x.
	(SECONDARY_MEMORY_NEEDED): Added mode!=DFmode and mode!=DImode
	conditions.
	* config/rs6000/power6.md: New file.


Co-Authored-By: Peter Bergner <bergner@vnet.ibm.com>

From-SVN: r118396
This commit is contained in:
Pete Steinmetz 2006-11-01 20:47:53 +00:00 committed by Peter Bergner
parent 293be7fd22
commit 44cd321ed8
27 changed files with 2143 additions and 475 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

69
gcc/ChangeLog
View File

@ -1,3 +1,72 @@
2006-11-01 Pete Steinmetz <steinmtz@us.ibm.com>
Peter Bergner <bergner@vnet.ibm.com>
* doc/invoke.texi: Add cpu_type power6x
(RS/6000 and PowerPC Options): Add -mmfpgpr.
* config.gcc: Add cpu_type power6x.
* configure.ac: Add test for mf{t,f}gpr instructions.
(HAVE_AS_MFPGPR): New.
* config.in: Regenerate.
* configure: Regenerate.
* config/rs6000/aix52.h (ASM_CPU_SPEC): Add power6x.
* config/rs6000/rs6000.md (define_attr "type"): Add insert_dword,
shift,trap,var_shift_rotate,cntlz,exts, var_delayed_compare, mffgpr
and mftgpr attributes.
(define_attr "cpu"): Add power6.
Change instruction sequences to use new attributes.
(floatsidf2,fix_truncdfsi2): use TARGET_MFPGPR.
(fix_truncdfsi2_mfpgpr): New.
(floatsidf_ppc64_mfpgpr): New.
(floatsidf_ppc64): Added !TARGET_MFPGPR condition.
(movdf_hardfloat64_mfpgpr,movdi_mfpgpr): New.
(movdf_hardfloat64): Added !TARGET_MFPGPR condition.
(movdi_internal64): Added !TARGET_MFPGPR and related conditions.
(fix_truncdfsi2): Use gpc_reg_operand constraint.
* config/rs6000/{6xx.md,power4.md,8540.md,603.md,mpc.md,
7xx.md,rios2.md,7450.md,440.md,rios1.md,rs64.md,power5.md,40x.md}:
Add descriptions for insert_dword, shift,trap,var_shift_rotate,
cntlz,exts and var_delayed_compare.
* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Define
_ARCH_PWR6X, if features enabled.
* config/rs6000/rs6000.opt (mmfpgpr): New.
* config/rs6000/rs6000.c (rs6000_align_branch_targets): New variable.
(cached_can_issue_more): New variable.
(processor_costs): Add power6_cost.
(rs6000_sched_init): New function.
(is_dispatch_slot_restricted): Deleted.
(set_to_load_agen): New function.
(is_load_insn,is_store_insn): New functions.
(adjacent_mem_locations): New function.
(insn_must_be_first_in_group): New function.
(insn_must_be_last_in_group): New function.
(rs6000_sched_reorder): New function.
(rs6000_sched_reorder2): New function.
(TARGET_SCHED_INIT,TARGET_SCHED_REORDER,
TARGET_SCHED_REORDER2): Define.
(processor_target_table): Use PROCESSOR_POWER6 for power6.
Add power6x. Add MASK_MFPGPR for power6x.
(POWERPC_MASKS): Add MASK_MFPGPR.
(rs6000_override_options): Set rs6000_always_hint to false
for power6. Set rs6000_align_branch_targets. Replace
rs6000_sched_groups check with rs6000_align_branch_targets.
Use PROCESSOR_POWER6.
(last_scheduled_insn): New variable.
(load_store_pendulum): New variable.
(rs6000_variable_issue): Set last_scheduled_insn and
cached_can_issue_more.
(rs6000_adjust_cost): Add power6 cost adjustments.
(rs6000_adjust_priority): Replace is_dispatch_slot_restricted
with insn_must_be_first_in_group. Add power6 priority adjustments.
(rs6000_issue_rate): Add CPU_POWER6.
(insn_terminates_group_p): Use insn_must_be_{first,last}_in_group.
* config/rs6000/rs6000.h (processor_type): Add PROCESSOR_POWER6.
(TARGET_MFPGPR): New.
(SECONDARY_MEMORY_NEEDED): Use TARGET_MFPGPR.
(ASM_CPU_SPEC): Add power6x.
(SECONDARY_MEMORY_NEEDED): Added mode!=DFmode and mode!=DImode
conditions.
* config/rs6000/power6.md: New file.
2006-11-01 Adam Nemet <anemet@caviumnetworks.com>
* tree-pretty-print.c (dump_generic_node) <INTEGER_CST>: Use

4
gcc/config.gcc
View File

@ -303,7 +303,7 @@ powerpc*-*-*)
extra_headers="ppc-asm.h altivec.h spe.h"
need_64bit_hwint=yes
case x$with_cpu in
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456]|xrs64a)
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456]|xpower6x|xrs64a)
cpu_is_64bit=yes
;;
esac
@ -2870,7 +2870,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common \
| power | power[23456] | powerpc | powerpc64 \
| power | power[23456] | power6x | powerpc | powerpc64 \
| rios | rios1 | rios2 | rsc | rsc1 | rs64a \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 505 \
| 601 | 602 | 603 | 603e | ec603e | 604 \

6
gcc/config.in
View File

@ -233,6 +233,12 @@
#endif
/* Define if your assembler supports mffgpr and mftgpr. */
#ifndef USED_FOR_TARGET
#undef HAVE_AS_MFPGPR
#endif
/* Define if your assembler supports the -no-mul-bug-abort option. */
#ifndef USED_FOR_TARGET
#undef HAVE_AS_NO_MUL_BUG_ABORT_OPTION

6
gcc/config/rs6000/40x.md
View File

@ -38,7 +38,8 @@
"iu_40x")
(define_insn_reservation "ppc403-integer" 1
(and (eq_attr "type" "integer,insert_word")
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
var_shift_rotate,cntlz,exts")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
@ -53,7 +54,8 @@
"iu_40x,iu_40x,iu_40x")
(define_insn_reservation "ppc403-compare" 3
(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
var_delayed_compare")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x,nothing,bpu_40x")

3
gcc/config/rs6000/440.md
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@ -55,7 +55,8 @@
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-integer" 1
(and (eq_attr "type" "integer,insert_word")
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,\
trap,var_shift_rotate,cntlz,exts")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")

6
gcc/config/rs6000/603.md
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@ -59,7 +59,8 @@
"lsu_603")
(define_insn_reservation "ppc603-integer" 1
(and (eq_attr "type" "integer,insert_word")
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
var_shift_rotate,cntlz,exts")
(eq_attr "cpu" "ppc603"))
"iu_603")
@ -90,7 +91,8 @@
"iu_603*37")
(define_insn_reservation "ppc603-compare" 3
(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
var_delayed_compare")
(eq_attr "cpu" "ppc603"))
"iu_603,nothing,bpu_603")

6
gcc/config/rs6000/6xx.md
View File

@ -74,7 +74,8 @@
"lsu_6xx")
(define_insn_reservation "ppc604-integer" 1
(and (eq_attr "type" "integer,insert_word")
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
var_shift_rotate,cntlz,exts")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx")
@ -139,7 +140,8 @@
"mciu_6xx*36")
(define_insn_reservation "ppc604-compare" 3
(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
var_delayed_compare")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"(iu1_6xx|iu2_6xx)")

6
gcc/config/rs6000/7450.md
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@ -75,7 +75,8 @@
"ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-integer" 1
(and (eq_attr "type" "integer,insert_word")
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,\
trap,var_shift_rotate,cntlz,exts")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,iu1_7450|iu2_7450|iu3_7450")
@ -106,7 +107,8 @@
"ppc7450_du,mciu_7450*23")
(define_insn_reservation "ppc7450-compare" 2
(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
var_delayed_compare")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")

6
gcc/config/rs6000/7xx.md
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@ -65,7 +65,8 @@
"ppc750_du,lsu_7xx")
(define_insn_reservation "ppc750-integer" 1
(and (eq_attr "type" "integer,insert_word")
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,\
trap,var_shift_rotate,cntlz,exts")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx|iu2_7xx")
@ -100,7 +101,8 @@
"ppc750_du,iu1_7xx*19")
(define_insn_reservation "ppc750-compare" 2
(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
var_delayed_compare")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,(iu1_7xx|iu2_7xx)")

4
gcc/config/rs6000/8540.md
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@ -85,7 +85,9 @@
;; Simple SU insns
(define_insn_reservation "ppc8540_su" 1
(and (eq_attr "type" "integer,insert_word,cmp,compare,delayed_compare,fast_compare")
(and (eq_attr "type" "integer,insert_word,insert_dword,cmp,compare,\
delayed_compare,var_delayed_compare,fast_compare,\
shift,trap,var_shift_rotate,cntlz,exts")
(eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")

1
gcc/config/rs6000/aix52.h
View File

@ -69,6 +69,7 @@ do { \
%{mcpu=power5: -m620} \
%{mcpu=power5+: -m620} \
%{mcpu=power6: -m620} \
%{mcpu=power6x: -m620} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rs64a: -mppc} \
%{mcpu=603: -m603} \

4
gcc/config/rs6000/linux64.h
View File

@ -58,9 +58,9 @@ extern int dot_symbols;
#endif
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_POWER4
#define PROCESSOR_DEFAULT PROCESSOR_POWER6
#undef PROCESSOR_DEFAULT64
#define PROCESSOR_DEFAULT64 PROCESSOR_POWER4
#define PROCESSOR_DEFAULT64 PROCESSOR_POWER6
/* We don't need to generate entries in .fixup, except when
-mrelocatable or -mrelocatable-lib is given. */

6
gcc/config/rs6000/mpc.md
View File

@ -43,7 +43,8 @@
"lsu_mpc")
(define_insn_reservation "mpccore-integer" 1
(and (eq_attr "type" "integer,insert_word")
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
var_shift_rotate,cntlz,exts")
(eq_attr "cpu" "mpccore"))
"iu_mpc")
@ -69,7 +70,8 @@
"mciu_mpc*6")
(define_insn_reservation "mpccore-compare" 3
(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
var_delayed_compare")
(eq_attr "cpu" "mpccore"))
"iu_mpc,nothing,bpu_mpc")

5
gcc/config/rs6000/power4.md
View File

@ -183,7 +183,8 @@
; Integer latency is 2 cycles
(define_insn_reservation "power4-integer" 2
(and (eq_attr "type" "integer")
(and (eq_attr "type" "integer,insert_dword,shift,trap,\
var_shift_rotate,cntlz,exts")
(eq_attr "cpu" "power4"))
"iq_power4")
@ -220,7 +221,7 @@
"iq_power4")
(define_insn_reservation "power4-compare" 2
(and (eq_attr "type" "compare,delayed_compare")
(and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4,iu1_power4,iu2_power4)\
|(du2_power4+du3_power4,iu2_power4,iu2_power4)\

5
gcc/config/rs6000/power5.md
View File

@ -144,7 +144,8 @@
; Integer latency is 2 cycles
(define_insn_reservation "power5-integer" 2
(and (eq_attr "type" "integer")
(and (eq_attr "type" "integer,insert_dword,shift,trap,\
var_shift_rotate,cntlz,exts")
(eq_attr "cpu" "power5"))
"iq_power5")
@ -179,7 +180,7 @@
"iq_power5")
(define_insn_reservation "power5-compare" 2
(and (eq_attr "type" "compare,delayed_compare")
(and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,iu1_power5,iu2_power5")

569
gcc/config/rs6000/power6.md Normal file
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@ -0,0 +1,569 @@
;; Scheduling description for IBM POWER6 processor.
;; Copyright (C) 2006 Free Software Foundation, Inc.
;; Contributed by Peter Steinmetz (steinmtz@us.ibm.com)
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 2, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING. If not, write to the
;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
;; MA 02110-1301, USA.
;; Sources:
;; The POWER6 has 2 iu, 2 fpu, 2 lsu, and 1 bu/cru unit per engine
;; (2 engines per chip). The chip can issue up to 5 internal ops
;; per cycle.
(define_automaton "power6iu,power6lsu,power6fpu,power6bu")
(define_cpu_unit "iu1_power6,iu2_power6" "power6iu")
(define_cpu_unit "lsu1_power6,lsu2_power6" "power6lsu")
(define_cpu_unit "bpu_power6" "power6bu")
(define_cpu_unit "fpu1_power6,fpu2_power6" "power6fpu")
(define_reservation "LS2_power6"
"lsu1_power6+lsu2_power6")
(define_reservation "FPU_power6"
"fpu1_power6|fpu2_power6")
(define_reservation "BRU_power6"
"bpu_power6")
(define_reservation "LSU_power6"
"lsu1_power6|lsu2_power6")
(define_reservation "LSF_power6"
"(lsu1_power6+fpu1_power6)\
|(lsu1_power6+fpu2_power6)\
|(lsu2_power6+fpu1_power6)\
|(lsu2_power6+fpu2_power6)")
(define_reservation "LX2_power6"
"(iu1_power6+iu2_power6+lsu1_power6)\
|(iu1_power6+iu2_power6+lsu2_power6)")
(define_reservation "FX2_power6"
"iu1_power6+iu2_power6")
(define_reservation "X2F_power6"
"(iu1_power6+iu2_power6+fpu1_power6)\
|(iu1_power6+iu2_power6+fpu2_power6)")
(define_reservation "BX2_power6"
"iu1_power6+iu2_power6+bpu_power6")
(define_reservation "LSX_power6"
"(iu1_power6+lsu1_power6)\
|(iu1_power6+lsu2_power6)\
|(iu2_power6+lsu1_power6)\
|(iu2_power6+lsu2_power6)")
(define_reservation "FXU_power6"
"iu1_power6|iu2_power6")
(define_reservation "XLF_power6"
"(iu1_power6+lsu1_power6+fpu1_power6)\
|(iu1_power6+lsu1_power6+fpu2_power6)\
|(iu1_power6+lsu2_power6+fpu1_power6)\
|(iu1_power6+lsu2_power6+fpu2_power6)\
|(iu2_power6+lsu1_power6+fpu1_power6)\
|(iu2_power6+lsu1_power6+fpu2_power6)\
|(iu2_power6+lsu2_power6+fpu1_power6)\
|(iu2_power6+lsu2_power6+fpu2_power6)")
(define_reservation "BRX_power6"
"(bpu_power6+iu1_power6)\
|(bpu_power6+iu2_power6)")
; Load/store
; The default for a value written by a fixed point load
; that is read/written by a subsequent fixed point op.
(define_insn_reservation "power6-load" 2 ; fx
(and (eq_attr "type" "load")
(eq_attr "cpu" "power6"))
"LSU_power6")
; define the bypass for the case where the value written
; by a fixed point load is used as the source value on
; a store.
(define_bypass 1 "power6-load,\
power6-load-update,\
power6-load-update-indexed"
"power6-store,\
power6-store-update,\
power6-store-update-indexed,\
power6-fpstore,\
power6-fpstore-update"
"store_data_bypass_p")
(define_insn_reservation "power6-load-ext" 4 ; fx
(and (eq_attr "type" "load_ext")
(eq_attr "cpu" "power6"))
"LSU_power6")
; define the bypass for the case where the value written
; by a fixed point load ext is used as the source value on
; a store.
(define_bypass 1 "power6-load-ext,\
power6-load-ext-update,\
power6-load-ext-update-indexed"
"power6-store,\
power6-store-update,\
power6-store-update-indexed,\
power6-fpstore,\
power6-fpstore-update"
"store_data_bypass_p")
(define_insn_reservation "power6-load-update" 2 ; fx
(and (eq_attr "type" "load_u")
(eq_attr "cpu" "power6"))
"LSX_power6")
(define_insn_reservation "power6-load-update-indexed" 2 ; fx
(and (eq_attr "type" "load_ux")
(eq_attr "cpu" "power6"))
"LSX_power6")
(define_insn_reservation "power6-load-ext-update" 4 ; fx
(and (eq_attr "type" "load_ext_u")
(eq_attr "cpu" "power6"))
"LSX_power6")
(define_insn_reservation "power6-load-ext-update-indexed" 4 ; fx
(and (eq_attr "type" "load_ext_ux")
(eq_attr "cpu" "power6"))
"LSX_power6")
(define_insn_reservation "power6-fpload" 1
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "power6"))
"LSU_power6")
(define_insn_reservation "power6-fpload-update" 1
(and (eq_attr "type" "fpload_u,fpload_ux")
(eq_attr "cpu" "power6"))
"LSX_power6")
(define_insn_reservation "power6-store" 14
(and (eq_attr "type" "store")
(eq_attr "cpu" "power6"))
"LSU_power6")
(define_insn_reservation "power6-store-update" 14
(and (eq_attr "type" "store_u")
(eq_attr "cpu" "power6"))
"LSX_power6")
(define_insn_reservation "power6-store-update-indexed" 14
(and (eq_attr "type" "store_ux")
(eq_attr "cpu" "power6"))
"LX2_power6")
(define_insn_reservation "power6-fpstore" 14
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "power6"))
"LSF_power6")
(define_insn_reservation "power6-fpstore-update" 14
(and (eq_attr "type" "fpstore_u,fpstore_ux")
(eq_attr "cpu" "power6"))
"XLF_power6")
(define_insn_reservation "power6-larx" 3
(and (eq_attr "type" "load_l")
(eq_attr "cpu" "power6"))
"LS2_power6")
(define_insn_reservation "power6-stcx" 10 ; best case
(and (eq_attr "type" "store_c")
(eq_attr "cpu" "power6"))
"LSX_power6")
(define_insn_reservation "power6-sync" 11 ; N/A
(and (eq_attr "type" "sync")
(eq_attr "cpu" "power6"))
"LSU_power6")
(define_insn_reservation "power6-integer" 1
(and (eq_attr "type" "integer")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_insn_reservation "power6-exts" 1
(and (eq_attr "type" "exts")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_insn_reservation "power6-shift" 1
(and (eq_attr "type" "shift")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_insn_reservation "power6-insert" 1
(and (eq_attr "type" "insert_word")
(eq_attr "cpu" "power6"))
"FX2_power6")
(define_insn_reservation "power6-insert-dword" 1
(and (eq_attr "type" "insert_dword")
(eq_attr "cpu" "power6"))
"FX2_power6")
; define the bypass for the case where the value written
; by a fixed point op is used as the source value on a
; store.
(define_bypass 1 "power6-integer,\
power6-exts,\
power6-shift,\
power6-insert,\
power6-insert-dword"
"power6-store,\
power6-store-update,\
power6-store-update-indexed,\
power6-fpstore,\
power6-fpstore-update"
"store_data_bypass_p")
(define_insn_reservation "power6-cntlz" 2
(and (eq_attr "type" "cntlz")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_bypass 1 "power6-cntlz"
"power6-store,\
power6-store-update,\
power6-store-update-indexed,\
power6-fpstore,\
power6-fpstore-update"
"store_data_bypass_p")
(define_insn_reservation "power6-var-rotate" 4
(and (eq_attr "type" "var_shift_rotate")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_insn_reservation "power6-trap" 1 ; N/A
(and (eq_attr "type" "trap")
(eq_attr "cpu" "power6"))
"BRX_power6")
(define_insn_reservation "power6-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "power6"))
"(iu1_power6,iu1_power6)\
|(iu1_power6+iu2_power6,nothing)\
|(iu1_power6,iu2_power6)\
|(iu2_power6,iu1_power6)\
|(iu2_power6,iu2_power6)")
(define_insn_reservation "power6-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "power6"))
"(iu1_power6,iu1_power6,iu1_power6)\
|(iu1_power6,iu1_power6,iu2_power6)\
|(iu1_power6,iu2_power6,iu1_power6)\
|(iu1_power6,iu2_power6,iu2_power6)\
|(iu2_power6,iu1_power6,iu1_power6)\
|(iu2_power6,iu1_power6,iu2_power6)\
|(iu2_power6,iu2_power6,iu1_power6)\
|(iu2_power6,iu2_power6,iu2_power6)\
|(iu1_power6+iu2_power6,iu1_power6)\
|(iu1_power6+iu2_power6,iu2_power6)\
|(iu1_power6,iu1_power6+iu2_power6)\
|(iu2_power6,iu1_power6+iu2_power6)")
(define_insn_reservation "power6-cmp" 1
(and (eq_attr "type" "cmp")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_insn_reservation "power6-compare" 1
(and (eq_attr "type" "compare")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_insn_reservation "power6-fast-compare" 1
(and (eq_attr "type" "fast_compare")
(eq_attr "cpu" "power6"))
"FXU_power6")
; define the bypass for the case where the value written
; by a fixed point rec form op is used as the source value
; on a store.
(define_bypass 1 "power6-compare,\
power6-fast-compare"
"power6-store,\
power6-store-update,\
power6-store-update-indexed,\
power6-fpstore,\
power6-fpstore-update"
"store_data_bypass_p")
(define_insn_reservation "power6-delayed-compare" 2 ; N/A
(and (eq_attr "type" "delayed_compare")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_insn_reservation "power6-var-delayed-compare" 4
(and (eq_attr "type" "var_delayed_compare")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_insn_reservation "power6-lmul-cmp" 16
(and (eq_attr "type" "lmul_compare")
(eq_attr "cpu" "power6"))
"(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
|(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
(define_insn_reservation "power6-imul-cmp" 16
(and (eq_attr "type" "imul_compare")
(eq_attr "cpu" "power6"))
"(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
|(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
(define_insn_reservation "power6-lmul" 16
(and (eq_attr "type" "lmul")
(eq_attr "cpu" "power6"))
"(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
|(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
(define_insn_reservation "power6-imul" 16
(and (eq_attr "type" "imul")
(eq_attr "cpu" "power6"))
"(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
|(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
(define_insn_reservation "power6-imul3" 16
(and (eq_attr "type" "imul2,imul3")
(eq_attr "cpu" "power6"))
"(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
|(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
(define_bypass 9 "power6-imul,\
power6-lmul,\
power6-imul-cmp,\
power6-lmul-cmp,\
power6-imul3"
"power6-store,\
power6-store-update,\
power6-store-update-indexed,\
power6-fpstore,\
power6-fpstore-update"
"store_data_bypass_p")
(define_insn_reservation "power6-idiv" 44
(and (eq_attr "type" "idiv")
(eq_attr "cpu" "power6"))
"(iu1_power6*44+iu2_power6*44+fpu1_power6*44)\
|(iu1_power6*44+iu2_power6*44+fpu2_power6*44)");
; The latency for this bypass is yet to be defined
;(define_bypass ? "power6-idiv"
; "power6-store,\
; power6-store-update,\
; power6-store-update-indexed,\
; power6-fpstore,\
; power6-fpstore-update"
; "store_data_bypass_p")
(define_insn_reservation "power6-ldiv" 56
(and (eq_attr "type" "ldiv")
(eq_attr "cpu" "power6"))
"(iu1_power6*56+iu2_power6*56+fpu1_power6*56)\
|(iu1_power6*56+iu2_power6*56+fpu2_power6*56)");
; The latency for this bypass is yet to be defined
;(define_bypass ? "power6-ldiv"
; "power6-store,\
; power6-store-update,\
; power6-store-update-indexed,\
; power6-fpstore,\
; power6-fpstore-update"
; "store_data_bypass_p")
(define_insn_reservation "power6-mtjmpr" 2
(and (eq_attr "type" "mtjmpr,mfjmpr")
(eq_attr "cpu" "power6"))
"BX2_power6")
(define_bypass 5 "power6-mtjmpr" "power6-branch")
(define_insn_reservation "power6-branch" 2
(and (eq_attr "type" "jmpreg,branch")
(eq_attr "cpu" "power6"))
"BRU_power6")
(define_bypass 5 "power6-branch" "power6-mtjmpr")
(define_insn_reservation "power6-crlogical" 3
(and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "power6"))
"BRU_power6")
(define_bypass 3 "power6-crlogical" "power6-branch")
(define_insn_reservation "power6-delayedcr" 3
(and (eq_attr "type" "delayed_cr")
(eq_attr "cpu" "power6"))
"BRU_power6")
(define_insn_reservation "power6-mfcr" 6 ; N/A
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "power6"))
"BX2_power6")
; mfcrf (1 field)
(define_insn_reservation "power6-mfcrf" 3 ; N/A
(and (eq_attr "type" "mfcrf")
(eq_attr "cpu" "power6"))
"BX2_power6") ;
; mtcrf (1 field)
(define_insn_reservation "power6-mtcr" 4 ; N/A
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "power6"))
"BX2_power6")
(define_bypass 9 "power6-mtcr" "power6-branch")
(define_insn_reservation "power6-fp" 6
(and (eq_attr "type" "fp,dmul")
(eq_attr "cpu" "power6"))
"FPU_power6")
; Any fp instruction that updates a CR has a latency
; of 6 to a dependent branch
(define_bypass 6 "power6-fp" "power6-branch")
(define_bypass 1 "power6-fp"
"power6-fpstore,power6-fpstore-update"
"store_data_bypass_p")
(define_insn_reservation "power6-fpcompare" 8
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_bypass 12 "power6-fpcompare"
"power6-branch,power6-crlogical")
(define_insn_reservation "power6-sdiv" 26
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_insn_reservation "power6-ddiv" 32
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_insn_reservation "power6-sqrt" 30
(and (eq_attr "type" "ssqrt")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_insn_reservation "power6-dsqrt" 42
(and (eq_attr "type" "dsqrt")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_insn_reservation "power6-isync" 2 ; N/A
(and (eq_attr "type" "isync")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_insn_reservation "power6-vecload" 1
(and (eq_attr "type" "vecload")
(eq_attr "cpu" "power6"))
"LSU_power6")
(define_insn_reservation "power6-vecstore" 1
(and (eq_attr "type" "vecstore")
(eq_attr "cpu" "power6"))
"LSF_power6")
(define_insn_reservation "power6-vecsimple" 3
(and (eq_attr "type" "vecsimple")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_bypass 6 "power6-vecsimple" "power6-veccomplex,\
power6-vecperm")
(define_bypass 5 "power6-vecsimple" "power6-vecfloat")
(define_bypass 4 "power6-vecsimple" "power6-vecstore" )
(define_insn_reservation "power6-veccmp" 1
(and (eq_attr "type" "veccmp")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_bypass 10 "power6-veccmp" "power6-branch")
(define_insn_reservation "power6-vecfloat" 7
(and (eq_attr "type" "vecfloat")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_bypass 10 "power6-vecfloat" "power6-vecsimple")
(define_bypass 11 "power6-vecfloat" "power6-veccomplex,\
power6-vecperm")
(define_bypass 9 "power6-vecfloat" "power6-vecstore" )
(define_insn_reservation "power6-veccomplex" 7
(and (eq_attr "type" "vecsimple")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_bypass 10 "power6-veccomplex" "power6-vecsimple,\
power6-vecfloat" )
(define_bypass 9 "power6-veccomplex" "power6-vecperm" )
(define_bypass 8 "power6-veccomplex" "power6-vecstore" )
(define_insn_reservation "power6-vecperm" 4
(and (eq_attr "type" "vecperm")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_bypass 7 "power6-vecperm" "power6-vecsimple,\
power6-vecfloat" )
(define_bypass 6 "power6-vecperm" "power6-veccomplex" )
(define_bypass 5 "power6-vecperm" "power6-vecstore" )
(define_insn_reservation "power6-mftgpr" 8
(and (eq_attr "type" "mftgpr")
(eq_attr "cpu" "power6"))
"X2F_power6")
(define_insn_reservation "power6-mffgpr" 14
(and (eq_attr "type" "mffgpr")
(eq_attr "cpu" "power6"))
"LX2_power6")
(define_bypass 4 "power6-mftgpr" "power6-imul,\
power6-lmul,\
power6-imul-cmp,\
power6-lmul-cmp,\
power6-imul3,\
power6-idiv,\
power6-ldiv" )

8
gcc/config/rs6000/rios1.md
View File

@ -52,7 +52,8 @@
"iu_rios1+fpu_rios1")
(define_insn_reservation "rios1-integer" 1
(and (eq_attr "type" "integer,insert_word")
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,\
trap,var_shift_rotate,cntlz,exts")
(eq_attr "cpu" "rios1,ppc601"))
"iu_rios1")
@ -104,12 +105,13 @@
"iu_rios1,nothing*2,bpu_rios1")
(define_insn_reservation "rios1-delayed_compare" 5
(and (eq_attr "type" "delayed_compare")
(and (eq_attr "type" "delayed_compare,var_delayed_compare")
(eq_attr "cpu" "rios1"))
"iu_rios1,nothing*3,bpu_rios1")
(define_insn_reservation "ppc601-compare" 3
(and (eq_attr "type" "cmp,compare,delayed_compare")
(and (eq_attr "type" "cmp,compare,delayed_compare,\
var_delayed_compare")
(eq_attr "cpu" "ppc601"))
"iu_rios1,nothing,bpu_rios1")

6
gcc/config/rs6000/rios2.md
View File

@ -40,7 +40,8 @@
"iu1_rios2|iu2_rios2")
(define_insn_reservation "rios2-integer" 1
(and (eq_attr "type" "integer,insert_word")
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
var_shift_rotate,cntlz,exts")
(eq_attr "cpu" "rios2"))
"iu1_rios2|iu2_rios2")
@ -67,7 +68,8 @@
; compare executes on integer unit, but feeds insns which
; execute on the branch unit.
(define_insn_reservation "rios2-compare" 3
(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
var_delayed_compare")
(eq_attr "cpu" "rios2"))
"(iu1_rios2|iu2_rios2),nothing,bpu_rios2")

2
gcc/config/rs6000/rs6000-c.c
View File

@ -106,6 +106,8 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile)
builtin_define ("_ARCH_PWR5");
if (TARGET_FPRND)
builtin_define ("_ARCH_PWR5X");
if (TARGET_MFPGPR)
builtin_define ("_ARCH_PWR6X");
if (! TARGET_POWER && ! TARGET_POWER2 && ! TARGET_POWERPC)
builtin_define ("_ARCH_COM");
if (TARGET_ALTIVEC)

941
gcc/config/rs6000/rs6000.c
View File

File diff suppressed because it is too large Load Diff

28
gcc/config/rs6000/rs6000.h
View File

@ -75,6 +75,7 @@
%{mcpu=power5: -mpower4} \
%{mcpu=power5+: -mpower4} \
%{mcpu=power6: -mpower4 -maltivec} \
%{mcpu=power6x: -mpower4 -maltivec} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rios: -mpwr} \
%{mcpu=rios1: -mpwr} \
@ -162,6 +163,14 @@
#define TARGET_FPRND 0
#endif
/* Define TARGET_MFPGPR if the target assembler does not support the
mffpr and mftgpr instructions. */
#ifndef HAVE_AS_MFPGPR
#undef TARGET_MFPGPR
#define TARGET_MFPGPR 0
#endif
#ifndef TARGET_SECURE_PLT
#define TARGET_SECURE_PLT 0
#endif
@ -212,7 +221,8 @@ enum processor_type
PROCESSOR_PPC7450,
PROCESSOR_PPC8540,
PROCESSOR_POWER4,
PROCESSOR_POWER5
PROCESSOR_POWER5,
PROCESSOR_POWER6
};
extern enum processor_type rs6000_cpu;
@ -1109,12 +1119,18 @@ enum reg_class
rs6000_secondary_reload_class (CLASS, MODE, IN)
/* If we are copying between FP or AltiVec registers and anything
else, we need a memory location. */
else, we need a memory location. The exception is when we are
targeting ppc64 and the move to/from fpr to gpr instructions
are available.*/
#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \
|| (CLASS2) == FLOAT_REGS \
|| (CLASS1) == ALTIVEC_REGS \
#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
((CLASS1) != (CLASS2) && (((CLASS1) == FLOAT_REGS \
&& (!TARGET_MFPGPR || !TARGET_POWERPC64 \
|| ((MODE != DFmode) && (MODE != DImode)))) \
|| ((CLASS2) == FLOAT_REGS \
&& (!TARGET_MFPGPR || !TARGET_POWERPC64 \
|| ((MODE != DFmode) && (MODE != DImode)))) \
|| (CLASS1) == ALTIVEC_REGS \
|| (CLASS2) == ALTIVEC_REGS))
/* Return the maximum number of consecutive registers

829
gcc/config/rs6000/rs6000.md
View File

File diff suppressed because it is too large Load Diff

4
gcc/config/rs6000/rs6000.opt
View File

@ -64,6 +64,10 @@ mfprnd
Target Report Mask(FPRND)
Use PowerPC V2.02 floating point rounding instructions
mmfpgpr
Target Report Mask(MFPGPR)
Use extended PowerPC V2.05 move floating point to/from GPR instructions
maltivec
Target Report Mask(ALTIVEC)
Use AltiVec instructions

6
gcc/config/rs6000/rs64.md
View File

@ -47,7 +47,8 @@
"lsu_rs64")
(define_insn_reservation "rs64a-integer" 1
(and (eq_attr "type" "integer,insert_word")
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
var_shift_rotate,cntlz,exts")
(eq_attr "cpu" "rs64a"))
"iu_rs64")
@ -92,7 +93,8 @@
"mciu_rs64*66")
(define_insn_reservation "rs64a-compare" 3
(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
(and (eq_attr "type" "cmp,fast_compare,compare,\
delayed_compare,var_delayed_compare")
(eq_attr "cpu" "rs64a"))
"iu_rs64,nothing,bpu_rs64")

46
gcc/configure vendored
View File

@ -15510,6 +15510,52 @@ cat >>confdefs.h <<\_ACEOF
#define HAVE_AS_FPRND 1
_ACEOF
fi
case $target in
*-*-aix*) conftest_s=' .machine "pwr6"
.csect .text[PR]
mffgpr 1,3';;
*) conftest_s=' .machine power6
.text
mffgpr 1,3';;
esac
echo "$as_me:$LINENO: checking assembler for move fp gpr support" >&5
echo $ECHO_N "checking assembler for move fp gpr support... $ECHO_C" >&6
if test "${gcc_cv_as_powerpc_mfpgpr+set}" = set; then
echo $ECHO_N "(cached) $ECHO_C" >&6
else
gcc_cv_as_powerpc_mfpgpr=no
if test $in_tree_gas = yes; then
if test $gcc_cv_gas_vers -ge `expr \( \( 9 \* 1000 \) + 99 \) \* 1000 + 0`
then gcc_cv_as_powerpc_mfpgpr=yes
fi
elif test x$gcc_cv_as != x; then
echo "$conftest_s" > conftest.s
if { ac_try='$gcc_cv_as -o conftest.o conftest.s >&5'
{ (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
(eval $ac_try) 2>&5
ac_status=$?
echo "$as_me:$LINENO: \$? = $ac_status" >&5
(exit $ac_status); }; }
then
gcc_cv_as_powerpc_mfpgpr=yes
else
echo "configure: failed program was" >&5
cat conftest.s >&5
fi
rm -f conftest.o conftest.s
fi
fi
echo "$as_me:$LINENO: result: $gcc_cv_as_powerpc_mfpgpr" >&5
echo "${ECHO_T}$gcc_cv_as_powerpc_mfpgpr" >&6
if test $gcc_cv_as_powerpc_mfpgpr = yes; then
cat >>confdefs.h <<\_ACEOF
#define HAVE_AS_MFPGPR 1
_ACEOF
fi
case $target in

15
gcc/configure.ac
View File

@ -2933,6 +2933,21 @@ foo: nop
[AC_DEFINE(HAVE_AS_FPRND, 1,
[Define if your assembler supports fprnd.])])
case $target in
*-*-aix*) conftest_s=' .machine "pwr6"
.csect .text[[PR]]
mffgpr 1,3';;
*) conftest_s=' .machine power6
.text
mffgpr 1,3';;
esac
gcc_GAS_CHECK_FEATURE([move fp gpr support],
gcc_cv_as_powerpc_mfpgpr, [9,99,0],,
[$conftest_s],,
[AC_DEFINE(HAVE_AS_MFPGPR, 1,
[Define if your assembler supports mffgpr and mftgpr.])])
case $target in
*-*-aix*) conftest_s=' .csect .text[[PR]]
LCF..0:

27
gcc/doc/invoke.texi
View File

@ -656,6 +656,7 @@ See RS/6000 and PowerPC Options.
-mpowerpc-gpopt -mno-powerpc-gpopt @gol
-mpowerpc-gfxopt -mno-powerpc-gfxopt @gol
-mmfcrf -mno-mfcrf -mpopcntb -mno-popcntb -mfprnd -mno-fprnd @gol
-mmfpgpr -mno-mfpgpr @gol
-mnew-mnemonics -mold-mnemonics @gol
-mfull-toc -mminimal-toc -mno-fp-in-toc -mno-sum-in-toc @gol
-m64 -m32 -mxl-compat -mno-xl-compat -mpe @gol
@ -11253,6 +11254,8 @@ These @samp{-m} options are defined for the IBM RS/6000 and PowerPC:
@itemx -mno-popcntb
@itemx -mfprnd
@itemx -mno-fprnd
@itemx -mmfpgpr
@itemx -mno-mfpgpr
@opindex mpower
@opindex mno-power
@opindex mpower2
@ -11271,6 +11274,8 @@ These @samp{-m} options are defined for the IBM RS/6000 and PowerPC:
@opindex mno-popcntb
@opindex mfprnd
@opindex mno-fprnd
@opindex mmfpgpr
@opindex mno-mfpgpr
GCC supports two related instruction set architectures for the
RS/6000 and PowerPC@. The @dfn{POWER} instruction set are those
instructions supported by the @samp{rios} chip set used in the original
@ -11315,6 +11320,10 @@ architecture.
The @option{-mfprnd} option allows GCC to generate the FP round to
integer instructions implemented on the POWER5+ processor and other
processors that support the PowerPC V2.03 architecture.
The @option{-mmfpgpr} option allows GCC to generate the FP move to/from
general purpose register instructions implemented on the POWER6X
processor and other processors that support the extended PowerPC V2.05
architecture.
The @option{-mpowerpc64} option allows GCC to generate the additional
64-bit instructions that are found in the full PowerPC64 architecture
@ -11357,7 +11366,7 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403},
@samp{860}, @samp{970}, @samp{8540}, @samp{ec603e}, @samp{G3},
@samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3},
@samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6},
@samp{common}, @samp{powerpc}, @samp{powerpc64},
@samp{power6x}, @samp{common}, @samp{powerpc}, @samp{powerpc64},
@samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}.
@option{-mcpu=common} selects a completely generic processor. Code
@ -11381,14 +11390,14 @@ following options: @option{-maltivec}, @option{-mfprnd},
@option{-mhard-float}, @option{-mmfcrf}, @option{-mmultiple},
@option{-mnew-mnemonics}, @option{-mpopcntb}, @option{-mpower},
@option{-mpower2}, @option{-mpowerpc64}, @option{-mpowerpc-gpopt},
@option{-mpowerpc-gfxopt}, @option{-mstring}, @option{-mmulhw}, @option{-mdlmzb}.
The particular options
set for any particular CPU will vary between compiler versions,
depending on what setting seems to produce optimal code for that CPU;
it doesn't necessarily reflect the actual hardware's capabilities. If
you wish to set an individual option to a particular value, you may
specify it after the @option{-mcpu} option, like @samp{-mcpu=970
-mno-altivec}.
@option{-mpowerpc-gfxopt}, @option{-mstring}, @option{-mmulhw},
@option{-mdlmzb}, @option{-mmfpgpr}.
The particular options set for any particular CPU will vary between
compiler versions, depending on what setting seems to produce optimal
code for that CPU; it doesn't necessarily reflect the actual hardware's
capabilities. If you wish to set an individual option to a particular
value, you may specify it after the @option{-mcpu} option, like
@samp{-mcpu=970 -mno-altivec}.
On AIX, the @option{-maltivec} and @option{-mpowerpc64} options are
not enabled or disabled by the @option{-mcpu} option at present because