sparc.md (sltu, sgeu): Don't FAIL, call gen_compare_reg.
* config/sparc/sparc.md (sltu, sgeu): Don't FAIL, call gen_compare_reg. (movsf_const_intreg, movsf_const_high, movsf_const_lo, movdf_const_intreg and helper splits): New patterns to move float constants into integer registers. (negtf2, negdf2, abstf2, absdf2): Rework using new patterns and splits. From-SVN: r21813
This commit is contained in:
David S. Miller
David S. Miller
parent
648f19f647
commit
45120407b5
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@ -1,3 +1,13 @@
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Mon Aug 17 21:26:38 1998 David S. Miller <davem@pierdol.cobaltmicro.com>
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* config/sparc/sparc.md (sltu, sgeu): Don't FAIL, call
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gen_compare_reg.
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(movsf_const_intreg, movsf_const_high, movsf_const_lo,
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movdf_const_intreg and helper splits): New patterns to move float
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constants into integer registers.
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(negtf2, negdf2, abstf2, absdf2): Rework using new patterns and
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splits.
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Mon Aug 17 11:46:19 1998 Jeffrey A Law (law@cygnus.com)
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* From Graham
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@ -37,10 +37,12 @@
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;; 9 sethh
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;; 10 setlm
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;; 11 embmedany_sethi, embmedany_brsum
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;; 12 movsf_const_high
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;; 13 embmedany_textuhi
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;; 14 embmedany_texthi
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;; 15 embmedany_textulo
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;; 16 embmedany_textlo
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;; 17 movsf_const_lo
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;; 18 sethm
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;; 19 setlo
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;;
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@ -983,8 +985,7 @@
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if (gen_v9_scc (LTU, operands))
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DONE;
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}
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/* XXX less than unsigned == Carry */
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FAIL;
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operands[1] = gen_compare_reg (LTU, sparc_compare_op0, sparc_compare_op1);
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}")
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(define_expand "sgeu"
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@ -998,7 +999,7 @@
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if (gen_v9_scc (GEU, operands))
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DONE;
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}
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FAIL;
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operands[1] = gen_compare_reg (GEU, sparc_compare_op0, sparc_compare_op1);
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}")
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(define_expand "sleu"
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@ -2722,6 +2723,74 @@
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;; Floating point move insns
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(define_insn "*movsf_const_intreg"
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[(set (match_operand:SF 0 "general_operand" "=f,r")
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(match_operand:SF 1 "" "m,F"))]
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"TARGET_FPU
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&& GET_CODE (operands[1]) == CONST_DOUBLE
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&& GET_CODE (operands[0]) == REG"
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"*
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{
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REAL_VALUE_TYPE r;
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long i;
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if (which_alternative == 0)
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return \"ld\\t%1, %0\";
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REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
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REAL_VALUE_TO_TARGET_SINGLE (r, i);
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if (SPARC_SIMM13_P (i) || SPARC_SETHI_P (i))
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{
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operands[1] = GEN_INT (i);
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if (SPARC_SIMM13_P (INTVAL (operands[1])))
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return \"mov\\t%1, %0\";
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else if (SPARC_SETHI_P (INTVAL (operands[1])))
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return \"sethi\\t%%hi(%a1), %0\";
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}
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else
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return \"#\";
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}"
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[(set_attr "type" "move")
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(set_attr "length" "1")])
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;; There isn't much I can do about this, if I change the
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;; mode then flow info gets really confused because the
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;; destination no longer looks the same. Ho hum...
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(define_insn "*movsf_const_high"
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[(set (match_operand:SF 0 "register_operand" "=r")
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(unspec:SF [(match_operand 1 "const_int_operand" "")] 12))]
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""
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"sethi\\t%%hi(%a1), %0"
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[(set_attr "type" "move")
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(set_attr "length" "1")])
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(define_insn "*movsf_const_lo"
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[(set (match_operand:SF 0 "register_operand" "=r")
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(unspec:SF [(match_operand 1 "register_operand" "r")
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(match_operand 2 "const_int_operand" "")] 17))]
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""
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"or\\t%1, %%lo(%a2), %0"
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[(set_attr "type" "move")
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(set_attr "length" "1")])
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(define_split
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[(set (match_operand:SF 0 "register_operand" "")
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(match_operand:SF 1 "const_double_operand" ""))]
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"TARGET_FPU
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&& GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < 32"
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[(set (match_dup 0) (unspec:SF [(match_dup 1)] 12))
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(set (match_dup 0) (unspec:SF [(match_dup 0) (match_dup 1)] 17))]
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"
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{
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REAL_VALUE_TYPE r;
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long i;
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REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
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REAL_VALUE_TO_TARGET_SINGLE (r, i);
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operands[1] = GEN_INT (i);
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}")
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(define_expand "movsf"
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[(set (match_operand:SF 0 "general_operand" "")
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(match_operand:SF 1 "general_operand" ""))]
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@ -2808,6 +2877,60 @@
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[(set_attr "type" "move,load,store")
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(set_attr "length" "1")])
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(define_insn "*movdf_const_intreg"
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[(set (match_operand:DF 0 "general_operand" "=e,e,r")
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(match_operand:DF 1 "" "T,o,F"))]
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"TARGET_FPU
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&& GET_CODE (operands[1]) == CONST_DOUBLE
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&& GET_CODE (operands[0]) == REG"
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"*
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{
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if (which_alternative == 0)
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return \"ldd\\t%1, %0\";
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else
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return \"#\";
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}"
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[(set_attr "type" "move")
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(set_attr "length" "1")])
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(define_split
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[(set (match_operand:DF 0 "register_operand" "")
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(match_operand:DF 1 "const_double_operand" ""))]
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"TARGET_FPU
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&& GET_CODE (operands[1]) == CONST_DOUBLE
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&& GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < 32
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&& reload_completed"
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[(clobber (const_int 0))]
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"
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{
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REAL_VALUE_TYPE r;
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long l[2];
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REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
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REAL_VALUE_TO_TARGET_DOUBLE (r, l);
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operands[0] = gen_rtx_raw_REG (DImode, REGNO (operands[0]));
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emit_insn (gen_movsi (gen_highpart (SImode, operands[0]),
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GEN_INT (l[0])));
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/* Slick... but this trick loses if this subreg constant part
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can be done in one insn. */
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if (l[1] == l[0]
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&& !(SPARC_SETHI_P (l[0])
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|| SPARC_SIMM13_P (l[0])))
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{
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emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
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gen_highpart (SImode, operands[0])));
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}
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else
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{
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emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
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GEN_INT (l[1])));
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}
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DONE;
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}")
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(define_expand "movdf"
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[(set (match_operand:DF 0 "general_operand" "")
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(match_operand:DF 1 "general_operand" ""))]
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@ -6274,44 +6397,109 @@
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[(set_attr "type" "fpdivs")
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(set_attr "length" "1")])
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;; XXX
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(define_insn "negtf2"
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(define_expand "negtf2"
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[(set (match_operand:TF 0 "register_operand" "=e,e")
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(neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
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"TARGET_FPU"
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"")
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(define_insn "*negtf2_notv9"
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[(set (match_operand:TF 0 "register_operand" "=e,e")
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(neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
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; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
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"TARGET_FPU"
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"*
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{
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/* v9: can't use fnegs, won't work with upper regs. */
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if (which_alternative == 0)
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return TARGET_V9 ? \"fnegd %0,%0\" : \"fnegs %0,%0\";
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else
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return TARGET_V9 ? \"fnegd %1,%0\;fmovd %S1,%S0\"
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: \"fnegs %1,%0\;fmovs %R1,%R0\;fmovs %S1,%S0\;fmovs %T1,%T0\";
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}"
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"TARGET_FPU
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&& ! TARGET_V9"
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"@
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fnegs\\t%0, %0
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#"
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[(set_attr "type" "fpmove")
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(set_attr_alternative "length"
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[(const_int 1)
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(if_then_else (eq_attr "isa" "v9") (const_int 2) (const_int 4))])])
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(set_attr "length" "1,2")])
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;; XXX
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(define_insn "negdf2"
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(define_split
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[(set (match_operand:TF 0 "register_operand" "")
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(neg:TF (match_operand:TF 1 "register_operand" "")))]
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"TARGET_FPU
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&& ! TARGET_V9
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&& GET_CODE (operands[0]) == REG
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&& GET_CODE (operands[1]) == REG
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&& REGNO (operands[0]) != REGNO (operands[1])
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&& reload_completed"
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[(set (match_dup 2) (neg (match_dup 3)))
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(set (match_dup 4) (match_dup 5))
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(set (match_dup 6) (match_dup 7))]
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"operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
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operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
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operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
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operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
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operands[6] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 2);
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operands[7] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 2);")
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(define_insn "*negtf2_v9"
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[(set (match_operand:TF 0 "register_operand" "=e,e")
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(neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
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; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
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"TARGET_FPU && TARGET_V9"
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"@
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fnegd\\t%0, %0
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#"
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[(set_attr "type" "fpmove")
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(set_attr "length" "1,2")])
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(define_split
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[(set (match_operand:TF 0 "register_operand" "")
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(neg:TF (match_operand:TF 1 "register_operand" "")))]
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"TARGET_FPU
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&& TARGET_V9
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&& GET_CODE (operands[0]) == REG
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&& GET_CODE (operands[1]) == REG
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&& REGNO (operands[0]) != REGNO (operands[1])
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&& reload_completed"
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[(set (match_dup 2) (neg:DF (match_dup 3)))
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(set (match_dup 4) (match_dup 5))]
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"operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
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operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
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operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
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operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);")
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(define_expand "negdf2"
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[(set (match_operand:DF 0 "register_operand" "")
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(neg:DF (match_operand:DF 1 "register_operand" "")))]
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"TARGET_FPU"
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"")
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(define_insn "*negdf2_notv9"
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[(set (match_operand:DF 0 "register_operand" "=e,e")
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(neg:DF (match_operand:DF 1 "register_operand" "0,e")))]
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"TARGET_FPU"
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"*
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{
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if (TARGET_V9)
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return \"fnegd %1,%0\";
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else if (which_alternative == 0)
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return \"fnegs %0,%0\";
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else
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return \"fnegs %1,%0\;fmovs %R1,%R0\";
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}"
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"TARGET_FPU && ! TARGET_V9"
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"@
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fnegs\\t%0, %0
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#"
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[(set_attr "type" "fpmove")
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(set_attr_alternative "length"
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[(const_int 1)
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(if_then_else (eq_attr "isa" "v9") (const_int 1) (const_int 2))])])
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(set_attr "length" "1,2")])
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(define_split
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[(set (match_operand:DF 0 "register_operand" "")
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(neg:DF (match_operand:DF 1 "register_operand" "")))]
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"TARGET_FPU
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&& ! TARGET_V9
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&& GET_CODE (operands[0]) == REG
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&& GET_CODE (operands[1]) == REG
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&& REGNO (operands[0]) != REGNO (operands[1])
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&& reload_completed"
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[(set (match_dup 2) (neg:SF (match_dup 3)))
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(set (match_dup 4) (match_dup 5))]
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"operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
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operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
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operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
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operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);")
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(define_insn "*negdf2_v9"
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[(set (match_operand:DF 0 "register_operand" "=e")
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(neg:DF (match_operand:DF 1 "register_operand" "e")))]
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"TARGET_FPU && TARGET_V9"
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"fnegd\\t%0, %0"
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[(set_attr "type" "fpmove")
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(set_attr "length" "1")])
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(define_insn "negsf2"
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[(set (match_operand:SF 0 "register_operand" "=f")
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@ -6321,44 +6509,108 @@
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[(set_attr "type" "fpmove")
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(set_attr "length" "1")])
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;; XXX
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(define_insn "abstf2"
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[(set (match_operand:TF 0 "register_operand" "")
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(abs:TF (match_operand:TF 1 "register_operand" "")))]
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"TARGET_FPU"
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"")
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(define_insn "*abstf2_notv9"
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[(set (match_operand:TF 0 "register_operand" "=e,e")
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(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
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; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
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"TARGET_FPU"
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"*
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{
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/* v9: can't use fabss, won't work with upper regs. */
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if (which_alternative == 0)
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return TARGET_V9 ? \"fabsd %0,%0\" : \"fabss %0,%0\";
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else
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return TARGET_V9 ? \"fabsd %1,%0\;fmovd %S1,%S0\"
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: \"fabss %1,%0\;fmovs %R1,%R0\;fmovs %S1,%S0\;fmovs %T1,%T0\";
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}"
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"TARGET_FPU && ! TARGET_V9"
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"@
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fabss\\t%0, %0
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#"
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[(set_attr "type" "fpmove")
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(set_attr_alternative "length"
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[(const_int 1)
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(if_then_else (eq_attr "isa" "v9") (const_int 2) (const_int 4))])])
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(set_attr "length" "1,2")])
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;; XXX
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(define_insn "absdf2"
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(define_split
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[(set (match_operand:TF 0 "register_operand" "=e,e")
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(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
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"TARGET_FPU
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&& ! TARGET_V9
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&& GET_CODE (operands[0]) == REG
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&& GET_CODE (operands[1]) == REG
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&& REGNO (operands[0]) != REGNO (operands[1])
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&& reload_completed"
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[(set (match_dup 2) (abs:SF (match_dup 3)))
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(set (match_dup 4) (match_dup 5))
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(set (match_dup 6) (match_dup 7))]
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"operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
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operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
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operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
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operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
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operands[6] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 2);
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operands[7] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 2);")
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(define_insn "*abstf2_v9"
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[(set (match_operand:TF 0 "register_operand" "=e,e")
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(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
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; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
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"TARGET_FPU && TARGET_V9"
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"@
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fabsd\\t%0, %0
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#"
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[(set_attr "type" "fpmove")
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(set_attr "length" "1,2")])
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(define_split
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[(set (match_operand:TF 0 "register_operand" "=e,e")
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(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
|
||||
"TARGET_FPU
|
||||
&& TARGET_V9
|
||||
&& GET_CODE (operands[0]) == REG
|
||||
&& GET_CODE (operands[1]) == REG
|
||||
&& REGNO (operands[0]) != REGNO (operands[1])
|
||||
&& reload_completed"
|
||||
[(set (match_dup 2) (abs:DF (match_dup 3)))
|
||||
(set (match_dup 4) (match_dup 5))]
|
||||
"operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
|
||||
operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
|
||||
operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
|
||||
operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);")
|
||||
|
||||
(define_expand "absdf2"
|
||||
[(set (match_operand:DF 0 "register_operand" "")
|
||||
(abs:DF (match_operand:DF 1 "register_operand" "")))]
|
||||
"TARGET_FPU"
|
||||
"")
|
||||
|
||||
(define_insn "*absdf2_notv9"
|
||||
[(set (match_operand:DF 0 "register_operand" "=e,e")
|
||||
(abs:DF (match_operand:DF 1 "register_operand" "0,e")))]
|
||||
"TARGET_FPU"
|
||||
"*
|
||||
{
|
||||
if (TARGET_V9)
|
||||
return \"fabsd %1,%0\";
|
||||
else if (which_alternative == 0)
|
||||
return \"fabss %0,%0\";
|
||||
else
|
||||
return \"fabss %1,%0\;fmovs %R1,%R0\";
|
||||
}"
|
||||
"TARGET_FPU && ! TARGET_V9"
|
||||
"@
|
||||
fabss\\t%0, %0
|
||||
#"
|
||||
[(set_attr "type" "fpmove")
|
||||
(set_attr_alternative "length"
|
||||
[(const_int 1)
|
||||
(if_then_else (eq_attr "isa" "v9") (const_int 1) (const_int 2))])])
|
||||
(set_attr "length" "1,2")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:DF 0 "register_operand" "=e,e")
|
||||
(abs:DF (match_operand:DF 1 "register_operand" "0,e")))]
|
||||
"TARGET_FPU
|
||||
&& ! TARGET_V9
|
||||
&& GET_CODE (operands[0]) == REG
|
||||
&& GET_CODE (operands[1]) == REG
|
||||
&& REGNO (operands[0]) != REGNO (operands[1])
|
||||
&& reload_completed"
|
||||
[(set (match_dup 2) (abs:SF (match_dup 3)))
|
||||
(set (match_dup 4) (match_dup 5))]
|
||||
"operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
|
||||
operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
|
||||
operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
|
||||
operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);")
|
||||
|
||||
(define_insn "*absdf2_v9"
|
||||
[(set (match_operand:DF 0 "register_operand" "=e")
|
||||
(abs:DF (match_operand:DF 1 "register_operand" "e")))]
|
||||
"TARGET_FPU && TARGET_V9"
|
||||
"fabsd\\t%0, %0"
|
||||
[(set_attr "type" "fpmove")
|
||||
(set_attr "length" "1")])
|
||||
|
||||
(define_insn "abssf2"
|
||||
[(set (match_operand:SF 0 "register_operand" "=f")
|
||||
|
|
|
|||
Loading…
Reference in New Issue