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(aux_truncdfsf2): New pattern. 

(movsf): Use it instead of invalid SUBREG and truncdfsf2.

From-SVN: r9902
This commit is contained in:
Richard Kenner 1995-06-08 17:42:08 -04:00
parent 27f3162f4b
commit 455350f417
1 changed files with 12 additions and 4 deletions
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16
gcc/config/rs6000/rs6000.md
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@ -2712,6 +2712,13 @@
"frsp %0,%1"
[(set_attr "type" "fp")])
(define_insn "aux_truncdfsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))]
"! TARGET_POWERPC && TARGET_HARD_FLOAT"
"frsp %0,%1"
[(set_attr "type" "fp")])
(define_insn "negsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
@ -4082,11 +4089,12 @@
/* If operands[1] is a register, it may have double-precision data
in it, so truncate it to single precision. We need not do
this for POWERPC. */
if (! TARGET_POWERPC && GET_CODE (operands[1]) == REG)
if (! TARGET_POWERPC && TARGET_HARD_FLOAT
&& GET_CODE (operands[1]) == REG)
{
rtx newreg = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
emit_insn (gen_truncdfsf2 (newreg,
gen_rtx (SUBREG, DFmode, operands[1], 0)));
rtx newreg
= reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
operands[1] = newreg;
}