s390.c (legitimate_reload_constant_p): Accept floating- point zero operands that fit into a single GPR.
2010-09-09 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
* config/s390/s390.c (legitimate_reload_constant_p): Accept floating-
point zero operands that fit into a single GPR.
(s390_preferred_reload_class): Ensure we only return general-purpose
register classes.
* config/s390/s390.md ("*mov<mode>_64dfp"): Use lghi to load
floating-point zero operands into GPRs.
("*mov<mode>_64"): Likewise.
("mov<mode>"): Likewise using lhi.
From-SVN: r164076
This commit is contained in:
Ulrich Weigand
Andreas Krebbel
parent
98635b04ce
commit
45e5214c6f
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@ -1,3 +1,14 @@
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2010-09-09 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
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* config/s390/s390.c (legitimate_reload_constant_p): Accept floating-
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point zero operands that fit into a single GPR.
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(s390_preferred_reload_class): Ensure we only return general-purpose
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register classes.
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* config/s390/s390.md ("*mov<mode>_64dfp"): Use lghi to load
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floating-point zero operands into GPRs.
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("*mov<mode>_64"): Likewise.
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("mov<mode>"): Likewise using lhi.
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2010-09-09 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
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* config/s390/s390.c (s390_symref_operand_p): Return false for
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@ -2815,6 +2815,12 @@ legitimate_reload_constant_p (rtx op)
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&& larl_operand (op, VOIDmode))
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return true;
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/* Accept floating-point zero operands that fit into a single GPR. */
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if (GET_CODE (op) == CONST_DOUBLE
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&& s390_float_const_zero_p (op)
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&& GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
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return true;
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/* Accept double-word operands that can be split. */
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if (GET_CODE (op) == CONST_INT
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&& trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
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@ -2838,13 +2844,16 @@ s390_preferred_reload_class (rtx op, enum reg_class rclass)
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{
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switch (GET_CODE (op))
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{
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/* Constants we cannot reload must be forced into the
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literal pool. */
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/* Constants we cannot reload into general registers
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must be forced into the literal pool. */
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case CONST_DOUBLE:
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case CONST_INT:
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if (legitimate_reload_constant_p (op))
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return rclass;
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if (reg_class_subset_p (GENERAL_REGS, rclass)
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&& legitimate_reload_constant_p (op))
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return GENERAL_REGS;
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else if (reg_class_subset_p (ADDR_REGS, rclass)
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&& legitimate_reload_constant_p (op))
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return ADDR_REGS;
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else
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return NO_REGS;
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@ -2042,9 +2042,9 @@
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(define_insn "*mov<mode>_64dfp"
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[(set (match_operand:DD_DF 0 "nonimmediate_operand"
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"=f,f,d,f,f,R,T,d, d,RT")
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"=f,f,d,f,f,R,T,d,d, d,RT")
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(match_operand:DD_DF 1 "general_operand"
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" f,d,f,R,T,f,f,d,RT, d"))]
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" f,d,f,R,T,f,f,G,d,RT, d"))]
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"TARGET_DFP"
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"@
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ldr\t%0,%1
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@ -2054,18 +2054,19 @@
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ldy\t%0,%1
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std\t%1,%0
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stdy\t%1,%0
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lghi\t%0,0
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lgr\t%0,%1
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lg\t%0,%1
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stg\t%1,%0"
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[(set_attr "op_type" "RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY")
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[(set_attr "op_type" "RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
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(set_attr "type" "floaddf,floaddf,floaddf,floaddf,floaddf,
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fstoredf,fstoredf,lr,load,store")
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(set_attr "z10prop" "*,*,*,*,*,*,*,z10_fr_E1,z10_fwd_A3,z10_rec")
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fstoredf,fstoredf,*,lr,load,store")
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(set_attr "z10prop" "*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
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])
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(define_insn "*mov<mode>_64"
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[(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,R,T,d, d,RT")
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(match_operand:DD_DF 1 "general_operand" "f,R,T,f,f,d,RT, d"))]
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[(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d, d,RT")
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(match_operand:DD_DF 1 "general_operand" "f,R,T,f,f,G,d,RT, d"))]
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"TARGET_ZARCH"
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"@
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ldr\t%0,%1
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@ -2073,13 +2074,14 @@
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ldy\t%0,%1
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std\t%1,%0
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stdy\t%1,%0
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lghi\t%0,0
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lgr\t%0,%1
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lg\t%0,%1
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stg\t%1,%0"
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[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY")
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[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
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(set_attr "type" "fload<mode>,fload<mode>,fload<mode>,
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fstore<mode>,fstore<mode>,lr,load,store")
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(set_attr "z10prop" "*,*,*,*,*,z10_fr_E1,z10_fwd_A3,z10_rec")])
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fstore<mode>,fstore<mode>,*,lr,load,store")
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(set_attr "z10prop" "*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")])
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(define_insn "*mov<mode>_31"
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[(set (match_operand:DD_DF 0 "nonimmediate_operand"
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@ -2150,9 +2152,9 @@
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(define_insn "mov<mode>"
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[(set (match_operand:SD_SF 0 "nonimmediate_operand"
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"=f,f,f,R,T,d,d,d,R,T")
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"=f,f,f,R,T,d,d,d,d,R,T")
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(match_operand:SD_SF 1 "general_operand"
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" f,R,T,f,f,d,R,T,d,d"))]
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" f,R,T,f,f,G,d,R,T,d,d"))]
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""
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"@
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ler\t%0,%1
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@ -2160,15 +2162,16 @@
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ley\t%0,%1
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ste\t%1,%0
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stey\t%1,%0
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lhi\t%0,0
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lr\t%0,%1
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l\t%0,%1
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ly\t%0,%1
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st\t%1,%0
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sty\t%1,%0"
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[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY")
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[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
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(set_attr "type" "fload<mode>,fload<mode>,fload<mode>,
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fstore<mode>,fstore<mode>,lr,load,load,store,store")
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(set_attr "z10prop" "*,*,*,*,*,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")])
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fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
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(set_attr "z10prop" "*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")])
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;
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; movcc instruction pattern
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