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s390.c (legitimate_reload_constant_p): Accept floating- point zero operands that fit into a single GPR. 

2010-09-09  Ulrich Weigand  <Ulrich.Weigand@de.ibm.com>

	* config/s390/s390.c (legitimate_reload_constant_p): Accept floating-
	point zero operands that fit into a single GPR.
	(s390_preferred_reload_class): Ensure we only return general-purpose
	register classes.
	* config/s390/s390.md ("*mov<mode>_64dfp"): Use lghi to load
	floating-point zero operands into GPRs.
	("*mov<mode>_64"): Likewise.
	("mov<mode>"): Likewise using lhi.

From-SVN: r164076
This commit is contained in:
Ulrich Weigand 2010-09-09 11:30:15 +00:00 committed by Andreas Krebbel
parent 98635b04ce
commit 45e5214c6f
3 changed files with 43 additions and 20 deletions
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11
gcc/ChangeLog
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@ -1,3 +1,14 @@
2010-09-09 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
* config/s390/s390.c (legitimate_reload_constant_p): Accept floating-
point zero operands that fit into a single GPR.
(s390_preferred_reload_class): Ensure we only return general-purpose
register classes.
* config/s390/s390.md ("*mov<mode>_64dfp"): Use lghi to load
floating-point zero operands into GPRs.
("*mov<mode>_64"): Likewise.
("mov<mode>"): Likewise using lhi.
2010-09-09 Ulrich Weigand <Ulrich.Weigand@de.ibm.com> 2010-09-09 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
* config/s390/s390.c (s390_symref_operand_p): Return false for * config/s390/s390.c (s390_symref_operand_p): Return false for

19
gcc/config/s390/s390.c
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@ -2815,6 +2815,12 @@ legitimate_reload_constant_p (rtx op)
&& larl_operand (op, VOIDmode)) && larl_operand (op, VOIDmode))
return true; return true;
/* Accept floating-point zero operands that fit into a single GPR. */
if (GET_CODE (op) == CONST_DOUBLE
&& s390_float_const_zero_p (op)
&& GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
return true;
/* Accept double-word operands that can be split. */ /* Accept double-word operands that can be split. */
if (GET_CODE (op) == CONST_INT if (GET_CODE (op) == CONST_INT
&& trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op)) && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
@ -2838,13 +2844,16 @@ s390_preferred_reload_class (rtx op, enum reg_class rclass)
{ {
switch (GET_CODE (op)) switch (GET_CODE (op))
{ {
/* Constants we cannot reload must be forced into the /* Constants we cannot reload into general registers
literal pool. */ must be forced into the literal pool. */
case CONST_DOUBLE: case CONST_DOUBLE:
case CONST_INT: case CONST_INT:
if (legitimate_reload_constant_p (op)) if (reg_class_subset_p (GENERAL_REGS, rclass)
return rclass; && legitimate_reload_constant_p (op))
return GENERAL_REGS;
else if (reg_class_subset_p (ADDR_REGS, rclass)
&& legitimate_reload_constant_p (op))
return ADDR_REGS;
else else
return NO_REGS; return NO_REGS;

33
gcc/config/s390/s390.md
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@ -2042,9 +2042,9 @@
(define_insn "*mov<mode>_64dfp" (define_insn "*mov<mode>_64dfp"
[(set (match_operand:DD_DF 0 "nonimmediate_operand" [(set (match_operand:DD_DF 0 "nonimmediate_operand"
"=f,f,d,f,f,R,T,d, d,RT") "=f,f,d,f,f,R,T,d,d, d,RT")
(match_operand:DD_DF 1 "general_operand" (match_operand:DD_DF 1 "general_operand"
" f,d,f,R,T,f,f,d,RT, d"))] " f,d,f,R,T,f,f,G,d,RT, d"))]
"TARGET_DFP" "TARGET_DFP"
"@ "@
ldr\t%0,%1 ldr\t%0,%1
@ -2054,18 +2054,19 @@
ldy\t%0,%1 ldy\t%0,%1
std\t%1,%0 std\t%1,%0
stdy\t%1,%0 stdy\t%1,%0
lghi\t%0,0
lgr\t%0,%1 lgr\t%0,%1
lg\t%0,%1 lg\t%0,%1
stg\t%1,%0" stg\t%1,%0"
[(set_attr "op_type" "RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY") [(set_attr "op_type" "RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
(set_attr "type" "floaddf,floaddf,floaddf,floaddf,floaddf, (set_attr "type" "floaddf,floaddf,floaddf,floaddf,floaddf,
fstoredf,fstoredf,lr,load,store") fstoredf,fstoredf,*,lr,load,store")
(set_attr "z10prop" "*,*,*,*,*,*,*,z10_fr_E1,z10_fwd_A3,z10_rec") (set_attr "z10prop" "*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
]) ])
(define_insn "*mov<mode>_64" (define_insn "*mov<mode>_64"
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,R,T,d, d,RT") [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d, d,RT")
(match_operand:DD_DF 1 "general_operand" "f,R,T,f,f,d,RT, d"))] (match_operand:DD_DF 1 "general_operand" "f,R,T,f,f,G,d,RT, d"))]
"TARGET_ZARCH" "TARGET_ZARCH"
"@ "@
ldr\t%0,%1 ldr\t%0,%1
@ -2073,13 +2074,14 @@
ldy\t%0,%1 ldy\t%0,%1
std\t%1,%0 std\t%1,%0
stdy\t%1,%0 stdy\t%1,%0
lghi\t%0,0
lgr\t%0,%1 lgr\t%0,%1
lg\t%0,%1 lg\t%0,%1
stg\t%1,%0" stg\t%1,%0"
[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY") [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
(set_attr "type" "fload<mode>,fload<mode>,fload<mode>, (set_attr "type" "fload<mode>,fload<mode>,fload<mode>,
fstore<mode>,fstore<mode>,lr,load,store") fstore<mode>,fstore<mode>,*,lr,load,store")
(set_attr "z10prop" "*,*,*,*,*,z10_fr_E1,z10_fwd_A3,z10_rec")]) (set_attr "z10prop" "*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")])
(define_insn "*mov<mode>_31" (define_insn "*mov<mode>_31"
[(set (match_operand:DD_DF 0 "nonimmediate_operand" [(set (match_operand:DD_DF 0 "nonimmediate_operand"
@ -2150,9 +2152,9 @@
(define_insn "mov<mode>" (define_insn "mov<mode>"
[(set (match_operand:SD_SF 0 "nonimmediate_operand" [(set (match_operand:SD_SF 0 "nonimmediate_operand"
"=f,f,f,R,T,d,d,d,R,T") "=f,f,f,R,T,d,d,d,d,R,T")
(match_operand:SD_SF 1 "general_operand" (match_operand:SD_SF 1 "general_operand"
" f,R,T,f,f,d,R,T,d,d"))] " f,R,T,f,f,G,d,R,T,d,d"))]
"" ""
"@ "@
ler\t%0,%1 ler\t%0,%1
@ -2160,15 +2162,16 @@
ley\t%0,%1 ley\t%0,%1
ste\t%1,%0 ste\t%1,%0
stey\t%1,%0 stey\t%1,%0
lhi\t%0,0
lr\t%0,%1 lr\t%0,%1
l\t%0,%1 l\t%0,%1
ly\t%0,%1 ly\t%0,%1
st\t%1,%0 st\t%1,%0
sty\t%1,%0" sty\t%1,%0"
[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY") [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
(set_attr "type" "fload<mode>,fload<mode>,fload<mode>, (set_attr "type" "fload<mode>,fload<mode>,fload<mode>,
fstore<mode>,fstore<mode>,lr,load,load,store,store") fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
(set_attr "z10prop" "*,*,*,*,*,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")]) (set_attr "z10prop" "*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")])
; ;
; movcc instruction pattern ; movcc instruction pattern