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re PR target/64180 (PowerPC carry bit improvements)

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PR target/64180
	* config/rs6000/rs6000.md (*add<mode>3_internal1): Rename to
	"*add<mode>3".
	(*add<mode>3_internal2, *add<mode>3_internal3, and (their splitters):
	Delete.
	(*add<mode>3_dot, *add<mode>3_dot2): New.
	(*add<mode>3_imm_dot, *add<mode>3_imm_dot2): New.

From-SVN: r218593
This commit is contained in:
Segher Boessenkool 2014-12-10 19:33:26 +01:00 committed by Segher Boessenkool
parent d262c86cc9
commit 46121d60c5
2 changed files with 96 additions and 57 deletions
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10
gcc/ChangeLog
View File

@ -1,3 +1,13 @@
2014-12-10 Segher Boessenkool <segher@kernel.crashing.org>
PR target/64180
* config/rs6000/rs6000.md (*add<mode>3_internal1): Rename to
"*add<mode>3".
(*add<mode>3_internal2, *add<mode>3_internal3, and (their splitters):
Delete.
(*add<mode>3_dot, *add<mode>3_dot2): New.
(*add<mode>3_imm_dot, *add<mode>3_imm_dot2): New.
2014-12-10 Segher Boessenkool <segher@kernel.crashing.org>
PR target/64180

143
gcc/config/rs6000/rs6000.md
View File

@ -1491,7 +1491,7 @@
}
})
(define_insn "*add<mode>3_internal1"
(define_insn "*add<mode>3"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r")
(plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b")
(match_operand:GPR 2 "add_operand" "r,I,L")))]
@ -1510,70 +1510,99 @@
"addis %0,%1,ha16(%2)"
[(set_attr "type" "add")])
(define_insn "*add<mode>3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
(match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
(define_insn_and_split "*add<mode>3_dot"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
(match_operand:GPR 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:P 3 "=r,r,r,r"))]
""
"@
add. %3,%1,%2
addic. %3,%1,%2
#
#"
[(set_attr "type" "add,compare,compare,compare")
(set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
(compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
(match_operand:GPR 2 "reg_or_short_operand" ""))
(const_int 0)))
(clobber (match_scratch:GPR 3 ""))]
"reload_completed"
[(set (match_dup 3)
(plus:GPR (match_dup 1)
(match_dup 2)))
(set (match_dup 0)
(compare:CC (match_dup 3)
(const_int 0)))]
"")
(define_insn "*add<mode>3_internal3"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
(compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
(match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
(const_int 0)))
(set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
(plus:P (match_dup 1)
(match_dup 2)))]
""
(clobber (match_scratch:GPR 0 "=r,r"))]
"<MODE>mode == Pmode"
"@
add. %0,%1,%2
addic. %0,%1,%2
#
#"
[(set_attr "type" "add,compare,compare,compare")
(set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
(compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
(match_operand:P 2 "reg_or_short_operand" ""))
(const_int 0)))
(set (match_operand:P 0 "gpc_reg_operand" "")
(plus:P (match_dup 1) (match_dup 2)))]
"reload_completed"
"&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
[(set (match_dup 0)
(plus:P (match_dup 1)
(match_dup 2)))
(plus:GPR (match_dup 1)
(match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
""
[(set_attr "type" "add")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_insn_and_split "*add<mode>3_dot2"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
(match_operand:GPR 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
(plus:GPR (match_dup 1)
(match_dup 2)))]
"<MODE>mode == Pmode"
"@
add. %0,%1,%2
#"
"&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
[(set (match_dup 0)
(plus:GPR (match_dup 1)
(match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
""
[(set_attr "type" "add")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_insn_and_split "*add<mode>3_imm_dot"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
(match_operand:GPR 2 "short_cint_operand" "I,I"))
(const_int 0)))
(clobber (match_scratch:GPR 0 "=r,r"))
(clobber (reg:GPR CA_REGNO))]
"<MODE>mode == Pmode"
"@
addic. %0,%1,%2
#"
"&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
[(set (match_dup 0)
(plus:GPR (match_dup 1)
(match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
""
[(set_attr "type" "add")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_insn_and_split "*add<mode>3_imm_dot2"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
(compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
(match_operand:GPR 2 "short_cint_operand" "I,I"))
(const_int 0)))
(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
(plus:GPR (match_dup 1)
(match_dup 2)))
(clobber (reg:GPR CA_REGNO))]
"<MODE>mode == Pmode"
"@
addic. %0,%1,%2
#"
"&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
[(set (match_dup 0)
(plus:GPR (match_dup 1)
(match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
""
[(set_attr "type" "add")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
;; Split an add that we can't do in one insn into two insns, each of which
;; does one 16-bit part. This is used by combine. Note that the low-order