Modulo-scheduling improvements. Patch 2 of 2
Co-Authored-By: Andrey Belevantsev <abel@ispras.ru> Co-Authored-By: Revital Eres <eres@il.ibm.com> Co-Authored-By: Vladimir Yanovsky <yanov@il.ibm.com> From-SVN: r127848
This commit is contained in:
Mircea Namolaru
Revital Eres
parent
7368348cb7
commit
46dc0789fe
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@ -1,3 +1,31 @@
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2007-08-28 Mircea Namolaru <namolaru@il.ibm.com>
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Vladimir Yanovsky <yanov@il.ibm.com>
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Revital Eres <eres@il.ibm.com>
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Andrey Belevantsev <abel@ispras.ru>
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* config/spu/spu.md: Recognize doloop pattern when -fmodulo-sched
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is set.
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* modulo-sched.c: Add documentation regarding do-loop.
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(doloop_register_get): Change number of arguments to support
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the new do-loop pattern and check whether COUNT_REG has no other
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occurences in the loop besides in the control part.
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(duplicate_insns_of_cycles): Do not duplicate the insn which
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changes count_reg as it is already adjusted.
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(generate_prolog_epilog): New argument to support the new
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do-loop pattern. Change the subtract instruction to use
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expand_simple_binop. Call duplicate_insns_of_cycles with new
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argument.
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(sms_schedule): Call doloop_register_get and
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generate_prolog_epilog with new argument. Do not handle loops
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with single sets insns with subreg in their lhs.
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* loop-doloop.c (doloop_optimize): Support for another do-loop
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pattern.
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(doloop_condition_get): Gets an instruction instead of a pattern
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and change the return condition when the do-loop pattern is
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not parallel.
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* ddg.c (create_ddg_dep_from_intra_loop_link): Handle only reg
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deps when considering to not create edges.
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2007-08-27 Alexandre Oliva <aoliva@redhat.com>
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* doc/extend.texi (gnu_inline funtion attribute): Document C++
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@ -3887,6 +3887,48 @@ selb\t%0,%4,%0,%3"
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[(set_attr "type" "br")])
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;; Define the subtract-one-and-jump insns so loop.c
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;; knows what to generate.
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(define_expand "doloop_end"
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[(use (match_operand 0 "" "")) ; loop pseudo
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(use (match_operand 1 "" "")) ; iterations; zero if unknown
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(use (match_operand 2 "" "")) ; max iterations
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(use (match_operand 3 "" "")) ; loop level
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(use (match_operand 4 "" ""))] ; label
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""
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"
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{
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/* Currently SMS relies on the do-loop pattern to recognize loops
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where (1) the control part comprises of all insns defining and/or
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using a certain 'count' register and (2) the loop count can be
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adjusted by modifying this register prior to the loop.
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. ??? The possible introduction of a new block to initialize the
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new IV can potentially effects branch optimizations. */
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if (optimize > 0 && flag_modulo_sched)
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{
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rtx s0;
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rtx bcomp;
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rtx loc_ref;
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/* Only use this on innermost loops. */
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if (INTVAL (operands[3]) > 1)
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FAIL;
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if (GET_MODE (operands[0]) != SImode)
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FAIL;
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s0 = operands [0];
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emit_move_insn (s0, gen_rtx_PLUS (SImode, s0, GEN_INT (-1)));
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bcomp = gen_rtx_NE(SImode, s0, const0_rtx);
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loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [4]);
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emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
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gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
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loc_ref, pc_rtx)));
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DONE;
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}
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}")
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;; convert between any two modes, avoiding any GCC assumptions
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(define_expand "spu_convert"
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[(set (match_operand 0 "spu_reg_operand" "")
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10
gcc/ddg.c
10
gcc/ddg.c
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@ -176,13 +176,17 @@ create_ddg_dep_from_intra_loop_link (ddg_ptr g, ddg_node_ptr src_node,
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rtx set;
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set = single_set (dest_node->insn);
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if (set)
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/* TODO: Handle registers that REG_P is not true for them, i.e.
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subregs and special registers. */
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if (set && REG_P (SET_DEST (set)))
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{
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int regno = REGNO (SET_DEST (set));
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struct df_ref *first_def =
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df_bb_regno_first_def_find (g->bb, regno);
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struct df_ref *first_def;
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struct df_rd_bb_info *bb_info = DF_RD_BB_INFO (g->bb);
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first_def = df_bb_regno_first_def_find (g->bb, regno);
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gcc_assert (first_def);
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if (bitmap_bit_p (bb_info->gen, first_def->id))
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return;
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}
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@ -69,35 +69,59 @@ along with GCC; see the file COPYING3. If not see
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if it is not a decrement and branch jump insn. */
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rtx
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doloop_condition_get (rtx pattern)
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doloop_condition_get (rtx doloop_pat)
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{
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rtx cmp;
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rtx inc;
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rtx reg;
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rtx inc_src;
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rtx condition;
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rtx pattern;
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/* The canonical doloop pattern we expect is:
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/* The canonical doloop pattern we expect has one of the following
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forms:
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(parallel [(set (pc) (if_then_else (condition)
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(label_ref (label))
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(pc)))
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(set (reg) (plus (reg) (const_int -1)))
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(additional clobbers and uses)])
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1) (parallel [(set (pc) (if_then_else (condition)
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(label_ref (label))
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(pc)))
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(set (reg) (plus (reg) (const_int -1)))
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(additional clobbers and uses)])
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Some targets (IA-64) wrap the set of the loop counter in
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an if_then_else too.
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The branch must be the first entry of the parallel (also required
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by jump.c), and the second entry of the parallel must be a set of
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the loop counter register. Some targets (IA-64) wrap the set of
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the loop counter in an if_then_else too.
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In summary, the branch must be the first entry of the
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parallel (also required by jump.c), and the second
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entry of the parallel must be a set of the loop counter
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register. */
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2) (set (reg) (plus (reg) (const_int -1))
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(set (pc) (if_then_else (reg != 0)
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(label_ref (label))
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(pc))). */
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pattern = PATTERN (doloop_pat);
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if (GET_CODE (pattern) != PARALLEL)
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return 0;
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{
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rtx cond;
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cmp = XVECEXP (pattern, 0, 0);
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inc = XVECEXP (pattern, 0, 1);
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/* We expect the decrement to immediately precede the branch. */
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if ((PREV_INSN (doloop_pat) == NULL_RTX)
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|| !INSN_P (PREV_INSN (doloop_pat)))
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return 0;
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cmp = pattern;
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inc = PATTERN (PREV_INSN (doloop_pat));
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/* We expect the condition to be of the form (reg != 0) */
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cond = XEXP (SET_SRC (cmp), 0);
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if (GET_CODE (cond) != NE || XEXP (cond, 1) != const0_rtx)
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return 0;
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}
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else
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{
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cmp = XVECEXP (pattern, 0, 0);
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inc = XVECEXP (pattern, 0, 1);
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}
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/* Check for (set (reg) (something)). */
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if (GET_CODE (inc) != SET)
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@ -139,7 +163,29 @@ doloop_condition_get (rtx pattern)
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if ((XEXP (condition, 0) == reg)
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|| (GET_CODE (XEXP (condition, 0)) == PLUS
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&& XEXP (XEXP (condition, 0), 0) == reg))
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{
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if (GET_CODE (pattern) != PARALLEL)
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/* The second form we expect:
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(set (reg) (plus (reg) (const_int -1))
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(set (pc) (if_then_else (reg != 0)
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(label_ref (label))
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(pc))).
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is equivalent to the following:
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(parallel [(set (pc) (if_then_else (reg != 1)
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(label_ref (label))
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(pc)))
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(set (reg) (plus (reg) (const_int -1)))
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(additional clobbers and uses)])
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So we return that form instead.
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*/
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condition = gen_rtx_fmt_ee (NE, VOIDmode, inc_src, const1_rtx);
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return condition;
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}
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/* ??? If a machine uses a funny comparison, we could return a
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canonicalized form here. */
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@ -597,9 +643,7 @@ doloop_optimize (struct loop *loop)
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{
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while (NEXT_INSN (doloop_pat) != NULL_RTX)
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doloop_pat = NEXT_INSN (doloop_pat);
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if (JUMP_P (doloop_pat))
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doloop_pat = PATTERN (doloop_pat);
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else
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if (!JUMP_P (doloop_pat))
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doloop_pat = NULL_RTX;
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}
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@ -82,8 +82,21 @@ along with GCC; see the file COPYING3. If not see
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perform modulo variable expansion for live ranges that span more than
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II cycles (i.e. use register copies to prevent a def from overwriting
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itself before reaching the use).
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*/
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SMS works with countable loops (1) whose control part can be easily
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decoupled from the rest of the loop and (2) whose loop count can
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be easily adjusted. This is because we peel a constant number of
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iterations into a prologue and epilogue for which we want to avoid
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emitting the control part, and a kernel which is to iterate that
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constant number of iterations less than the original loop. So the
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control part should be a set of insns clearly identified and having
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its own iv, not otherwise used in the loop (at-least for now), which
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initializes a register before the loop to the number of iterations.
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Currently SMS relies on the do-loop pattern to recognize such loops,
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where (1) the control part comprises of all insns defining and/or
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using a certain 'count' register and (2) the loop count can be
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adjusted by modifying this register prior to the loop.
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TODO: Rely on cfgloop analysis instead. */
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/* This page defines partial-schedule structures and functions for
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modulo scheduling. */
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@ -182,10 +195,11 @@ static int sms_order_nodes (ddg_ptr, int, int * result);
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static void set_node_sched_params (ddg_ptr);
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static partial_schedule_ptr sms_schedule_by_order (ddg_ptr, int, int, int *);
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static void permute_partial_schedule (partial_schedule_ptr ps, rtx last);
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static void generate_prolog_epilog (partial_schedule_ptr ,struct loop * loop, rtx);
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static void generate_prolog_epilog (partial_schedule_ptr, struct loop *loop,
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rtx, rtx);
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static void duplicate_insns_of_cycles (partial_schedule_ptr ps,
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int from_stage, int to_stage,
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int is_prolog);
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int is_prolog, rtx count_reg);
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#define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap)
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#define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time)
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@ -261,20 +275,22 @@ static struct sched_info sms_sched_info =
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};
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/* Return the register decremented and tested in INSN,
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or zero if it is not a decrement-and-branch insn. */
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/* Given HEAD and TAIL which are the first and last insns in a loop;
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return the register which controls the loop. Return zero if it has
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more than one occurrence in the loop besides the control part or the
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do-loop pattern is not of the form we expect. */
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static rtx
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doloop_register_get (rtx insn ATTRIBUTE_UNUSED)
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doloop_register_get (rtx head ATTRIBUTE_UNUSED, rtx tail ATTRIBUTE_UNUSED)
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{
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#ifdef HAVE_doloop_end
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rtx pattern, reg, condition;
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rtx reg, condition, insn;
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bool found = false;
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if (! JUMP_P (insn))
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if (!JUMP_P (tail))
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return NULL_RTX;
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pattern = PATTERN (insn);
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condition = doloop_condition_get (pattern);
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/* TODO: Free SMS's dependence on doloop_condition_get. */
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condition = doloop_condition_get (tail);
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if (! condition)
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return NULL_RTX;
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@ -286,6 +302,29 @@ doloop_register_get (rtx insn ATTRIBUTE_UNUSED)
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else
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gcc_unreachable ();
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/* Check that the COUNT_REG has no other occurrences in the loop
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until the decrement. We assume the control part consists of
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either a single (parallel) branch-on-count or a (non-parallel)
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branch immediately preceded by a single (decrement) insn. */
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for (insn = head; insn != PREV_INSN (tail); insn = NEXT_INSN (insn))
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if ((found = reg_mentioned_p (reg, insn)) == true)
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break;
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if (found)
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{
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if (dump_file)
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fprintf (dump_file, "SMS count_reg found outside control\n");
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return NULL_RTX;
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}
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/* One last check in case the do-loop pattern is parallel. */
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if (GET_CODE (PATTERN (tail)) == PARALLEL)
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if (reg_mentioned_p (reg, PREV_INSN (tail)))
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{
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if (dump_file)
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fprintf (dump_file, "SMS count_reg found outside control\n");
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return NULL_RTX;
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}
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return reg;
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#else
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return NULL_RTX;
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@ -583,7 +622,7 @@ permute_partial_schedule (partial_schedule_ptr ps, rtx last)
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static void
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duplicate_insns_of_cycles (partial_schedule_ptr ps, int from_stage,
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int to_stage, int for_prolog)
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int to_stage, int for_prolog, rtx count_reg)
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{
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int row;
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ps_insn_ptr ps_ij;
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@ -595,6 +634,13 @@ duplicate_insns_of_cycles (partial_schedule_ptr ps, int from_stage,
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int j, i_reg_moves;
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rtx reg_move = NULL_RTX;
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/* Do not duplicate any insn which refers to count_reg as it
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belongs to the control part.
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TODO: This should be done by analyzing the control part of
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the loop. */
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if (reg_mentioned_p (count_reg, u_node->insn))
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continue;
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if (for_prolog)
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{
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/* SCHED_STAGE (u_node) >= from_stage == 0. Generate increasing
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@ -643,23 +689,35 @@ duplicate_insns_of_cycles (partial_schedule_ptr ps, int from_stage,
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/* Generate the instructions (including reg_moves) for prolog & epilog. */
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static void
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generate_prolog_epilog (partial_schedule_ptr ps, struct loop * loop, rtx count_reg)
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generate_prolog_epilog (partial_schedule_ptr ps, struct loop *loop,
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rtx count_reg, rtx count_init)
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{
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int i;
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int last_stage = PS_STAGE_COUNT (ps) - 1;
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edge e;
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/* Generate the prolog, inserting its insns on the loop-entry edge. */
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start_sequence ();
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if (count_reg)
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/* Generate a subtract instruction at the beginning of the prolog to
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adjust the loop count by STAGE_COUNT. */
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emit_insn (gen_sub2_insn (count_reg, GEN_INT (last_stage)));
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if (!count_init)
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{
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/* Generate instructions at the beginning of the prolog to
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adjust the loop count by STAGE_COUNT. If loop count is constant
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(count_init), this constant is adjusted by STAGE_COUNT in
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generate_prolog_epilog function. */
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rtx sub_reg = NULL_RTX;
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sub_reg = expand_simple_binop (GET_MODE (count_reg), MINUS,
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count_reg, GEN_INT (last_stage),
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count_reg, 1, OPTAB_DIRECT);
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gcc_assert (REG_P (sub_reg));
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if (REGNO (sub_reg) != REGNO (count_reg))
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emit_move_insn (count_reg, sub_reg);
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}
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for (i = 0; i < last_stage; i++)
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duplicate_insns_of_cycles (ps, 0, i, 1);
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duplicate_insns_of_cycles (ps, 0, i, 1, count_reg);
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/* Put the prolog on the entry edge. */
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e = loop_preheader_edge (loop);
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split_edge_and_insert (e, get_insns ());
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@ -670,8 +728,8 @@ generate_prolog_epilog (partial_schedule_ptr ps, struct loop * loop, rtx count_r
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start_sequence ();
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for (i = 0; i < last_stage; i++)
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duplicate_insns_of_cycles (ps, i + 1, last_stage, 0);
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duplicate_insns_of_cycles (ps, i + 1, last_stage, 0, count_reg);
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/* Put the epilogue on the exit edge. */
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gcc_assert (single_exit (loop));
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e = single_exit (loop);
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@ -907,20 +965,27 @@ sms_schedule (void)
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}
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/* Make sure this is a doloop. */
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if ( !(count_reg = doloop_register_get (tail)))
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if ( !(count_reg = doloop_register_get (head, tail)))
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continue;
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/* Don't handle BBs with calls or barriers, or !single_set insns,
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or auto-increment insns (to avoid creating invalid reg-moves
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for the auto-increment insns).
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??? Should handle auto-increment insns. */
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for (insn = head; insn != NEXT_INSN (tail); insn = NEXT_INSN (insn))
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if (CALL_P (insn)
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|| BARRIER_P (insn)
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|| (INSN_P (insn) && !JUMP_P (insn)
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&& !single_set (insn) && GET_CODE (PATTERN (insn)) != USE)
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|| (FIND_REG_INC_NOTE (insn, NULL_RTX) != 0))
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break;
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||||
??? Should handle auto-increment insns.
|
||||
??? Should handle insns defining subregs. */
|
||||
for (insn = head; insn != NEXT_INSN (tail); insn = NEXT_INSN (insn))
|
||||
{
|
||||
rtx set;
|
||||
|
||||
if (CALL_P (insn)
|
||||
|| BARRIER_P (insn)
|
||||
|| (INSN_P (insn) && !JUMP_P (insn)
|
||||
&& !single_set (insn) && GET_CODE (PATTERN (insn)) != USE)
|
||||
|| (FIND_REG_INC_NOTE (insn, NULL_RTX) != 0)
|
||||
|| (INSN_P (insn) && (set = single_set (insn))
|
||||
&& GET_CODE (SET_DEST (set)) == SUBREG))
|
||||
break;
|
||||
}
|
||||
|
||||
if (insn != NEXT_INSN (tail))
|
||||
{
|
||||
|
|
@ -932,8 +997,11 @@ sms_schedule (void)
|
|||
fprintf (dump_file, "SMS loop-with-barrier\n");
|
||||
else if (FIND_REG_INC_NOTE (insn, NULL_RTX) != 0)
|
||||
fprintf (dump_file, "SMS reg inc\n");
|
||||
else
|
||||
fprintf (dump_file, "SMS loop-with-not-single-set\n");
|
||||
else if ((INSN_P (insn) && !JUMP_P (insn)
|
||||
&& !single_set (insn) && GET_CODE (PATTERN (insn)) != USE))
|
||||
fprintf (dump_file, "SMS loop-with-not-single-set\n");
|
||||
else
|
||||
fprintf (dump_file, "SMS loop with subreg in lhs\n");
|
||||
print_rtl_single (dump_file, insn);
|
||||
}
|
||||
|
||||
|
|
@ -998,7 +1066,7 @@ sms_schedule (void)
|
|||
/* In case of th loop have doloop register it gets special
|
||||
handling. */
|
||||
count_init = NULL_RTX;
|
||||
if ((count_reg = doloop_register_get (tail)))
|
||||
if ((count_reg = doloop_register_get (head, tail)))
|
||||
{
|
||||
basic_block pre_header;
|
||||
|
||||
|
|
@ -1072,7 +1140,10 @@ sms_schedule (void)
|
|||
the closing_branch was scheduled and should appear in the last (ii-1)
|
||||
row. Otherwise, we are free to schedule the branch, and we let nodes
|
||||
that were scheduled at the first PS_MIN_CYCLE cycle appear in the first
|
||||
row; this should reduce stage_count to minimum. */
|
||||
row; this should reduce stage_count to minimum.
|
||||
TODO: Revisit the issue of scheduling the insns of the
|
||||
control part relative to the branch when the control part
|
||||
has more than one insn. */
|
||||
normalize_sched_times (ps);
|
||||
rotate_partial_schedule (ps, PS_MIN_CYCLE (ps));
|
||||
set_columns_for_ps (ps);
|
||||
|
|
@ -1111,11 +1182,8 @@ sms_schedule (void)
|
|||
if (dump_file)
|
||||
print_node_sched_params (dump_file, g->num_nodes, g);
|
||||
/* Generate prolog and epilog. */
|
||||
if (count_reg && !count_init)
|
||||
generate_prolog_epilog (ps, loop, count_reg);
|
||||
else
|
||||
generate_prolog_epilog (ps, loop, NULL_RTX);
|
||||
|
||||
generate_prolog_epilog (ps, loop, count_reg, count_init);
|
||||
|
||||
free_undo_replace_buff (reg_move_replaces);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,10 @@
|
|||
2007-08-28 Mircea Namolaru <namolaru@il.ibm.com>
|
||||
Vladimir Yanovsky <yanov@il.ibm.com>
|
||||
Revital Eres <eres@il.ibm.com>
|
||||
Andrey Belevantsev <abel@ispras.ru>
|
||||
|
||||
* gcc.dg/sms-1.c: New test.
|
||||
|
||||
2007-08-27 Alexandre Oliva <aoliva@redhat.com>
|
||||
|
||||
* g++.dg/ext/gnu-inline-common.h: New.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,38 @@
|
|||
/* The same test as loop-3c.c. It failed on ia64
|
||||
due to not handling of subreg in the lhs that is fixed. */
|
||||
/* { dg-do run } */
|
||||
/* { dg-options "-O2 -fmodulo-sched -fmodulo-sched-allow-regmoves -w" } */
|
||||
|
||||
|
||||
#include <limits.h>
|
||||
|
||||
void * a[255];
|
||||
|
||||
f (m)
|
||||
{
|
||||
int i;
|
||||
int sh = 0x100;
|
||||
i = m;
|
||||
do
|
||||
{
|
||||
a[sh >>= 1] = ((unsigned)i << 3) + (char*)a;
|
||||
i += 4;
|
||||
}
|
||||
while (i < INT_MAX/2 + 1 + 4 * 4);
|
||||
}
|
||||
|
||||
main ()
|
||||
{
|
||||
a[0x10] = 0;
|
||||
a[0x08] = 0;
|
||||
f (INT_MAX/2 + INT_MAX/4 + 2);
|
||||
if (a[0x10] || a[0x08])
|
||||
abort ();
|
||||
a[0x10] = 0;
|
||||
a[0x08] = 0;
|
||||
f (INT_MAX/2 + 1);
|
||||
if (! a[0x10] || a[0x08])
|
||||
abort ();
|
||||
exit (0);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue