[AArch64] [3/4 Fix vtbx1]Implement bsl intrinsics using builtins
gcc/ * config/aarch64/aarch64-builtins.c (aarch64_types_bsl_p_qualifiers): New. (aarch64_types_bsl_s_qualifiers): Likewise. (aarch64_types_bsl_u_qualifiers): Likewise. (TYPES_BSL_P): Likewise. (TYPES_BSL_S): Likewise. (TYPES_BSL_U): Likewise. (BUILTIN_VALLDIF): Likewise. (BUILTIN_VDQQH): Likewise. * config/aarch64/aarch64-simd-builtins.def (simd_bsl): New. * config/aarch64/aarch64-simd.md (aarch64_simd_bsl<mode>_internal): Handle more modes. (aarch64_simd_bsl<mode>): Likewise. * config/aarch64/arm_neon.h (vbsl<q>_<fpsu><8,16,32,64): Implement using builtins. * config/aarch64/iterators.md (VALLDIF): New. (Vbtype): Handle more modes. From-SVN: r205385
This commit is contained in:
James Greenhalgh
James Greenhalgh
parent
6db1ec948e
commit
46e778c4f5
@ -1,3 +1,23 @@
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2013-11-26 James Greenhalgh <james.greenhalgh@arm.com>
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* config/aarch64/aarch64-builtins.c
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(aarch64_types_bsl_p_qualifiers): New.
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(aarch64_types_bsl_s_qualifiers): Likewise.
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(aarch64_types_bsl_u_qualifiers): Likewise.
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(TYPES_BSL_P): Likewise.
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(TYPES_BSL_S): Likewise.
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(TYPES_BSL_U): Likewise.
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(BUILTIN_VALLDIF): Likewise.
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(BUILTIN_VDQQH): Likewise.
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* config/aarch64/aarch64-simd-builtins.def (simd_bsl): New.
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* config/aarch64/aarch64-simd.md
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(aarch64_simd_bsl<mode>_internal): Handle more modes.
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(aarch64_simd_bsl<mode>): Likewise.
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* config/aarch64/arm_neon.h
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(vbsl<q>_<fpsu><8,16,32,64): Implement using builtins.
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* config/aarch64/iterators.md (VALLDIF): New.
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(Vbtype): Handle more modes.
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2013-11-26 James Greenhalgh <james.greenhalgh@arm.com>
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* config/aarch64/aarch64-builtins.c
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@ -181,6 +181,22 @@ aarch64_types_load1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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#define TYPES_LOAD1 (aarch64_types_load1_qualifiers)
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#define TYPES_LOADSTRUCT (aarch64_types_load1_qualifiers)
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static enum aarch64_type_qualifiers
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aarch64_types_bsl_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_poly, qualifier_unsigned,
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qualifier_poly, qualifier_poly };
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#define TYPES_BSL_P (aarch64_types_bsl_p_qualifiers)
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static enum aarch64_type_qualifiers
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aarch64_types_bsl_s_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_none, qualifier_unsigned,
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qualifier_none, qualifier_none };
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#define TYPES_BSL_S (aarch64_types_bsl_s_qualifiers)
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static enum aarch64_type_qualifiers
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aarch64_types_bsl_u_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_unsigned, qualifier_unsigned,
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qualifier_unsigned, qualifier_unsigned };
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#define TYPES_BSL_U (aarch64_types_bsl_u_qualifiers)
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/* The first argument (return type) of a store should be void type,
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which we represent with qualifier_void. Their first operand will be
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a DImode pointer to the location to store to, so we must use
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@ -255,6 +271,9 @@ aarch64_types_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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#define BUILTIN_VALLDI(T, N, MAP) \
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VAR11 (T, N, MAP, v8qi, v16qi, v4hi, v8hi, v2si, \
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v4si, v2di, v2sf, v4sf, v2df, di)
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#define BUILTIN_VALLDIF(T, N, MAP) \
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VAR12 (T, N, MAP, v8qi, v16qi, v4hi, v8hi, v2si, \
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v4si, v2di, v2sf, v4sf, v2df, di, df)
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#define BUILTIN_VB(T, N, MAP) \
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VAR2 (T, N, MAP, v8qi, v16qi)
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#define BUILTIN_VD(T, N, MAP) \
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@ -279,6 +298,8 @@ aarch64_types_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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VAR6 (T, N, MAP, v8qi, v16qi, v4hi, v8hi, v2si, v4si)
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#define BUILTIN_VDQV(T, N, MAP) \
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VAR5 (T, N, MAP, v8qi, v16qi, v4hi, v8hi, v4si)
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#define BUILTIN_VDQQH(T, N, MAP) \
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VAR4 (T, N, MAP, v8qi, v16qi, v4hi, v8hi)
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#define BUILTIN_VDQ_BHSI(T, N, MAP) \
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VAR6 (T, N, MAP, v8qi, v16qi, v4hi, v8hi, v2si, v4si)
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#define BUILTIN_VDQ_I(T, N, MAP) \
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@ -362,3 +362,8 @@
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/* Implemented by fma<mode>4. */
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BUILTIN_VDQF (TERNOP, fma, 4)
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/* Implemented by aarch64_simd_bsl<mode>. */
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BUILTIN_VDQQH (BSL_P, simd_bsl, 0)
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BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0)
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BUILTIN_VALLDIF (BSL_S, simd_bsl, 0)
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@ -1662,15 +1662,15 @@
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;; bif op0, op1, mask
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(define_insn "aarch64_simd_bsl<mode>_internal"
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[(set (match_operand:VALL 0 "register_operand" "=w,w,w")
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(ior:VALL
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(and:VALL
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[(set (match_operand:VALLDIF 0 "register_operand" "=w,w,w")
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(ior:VALLDIF
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(and:VALLDIF
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(match_operand:<V_cmp_result> 1 "register_operand" " 0,w,w")
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(match_operand:VALL 2 "register_operand" " w,w,0"))
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(and:VALL
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(match_operand:VALLDIF 2 "register_operand" " w,w,0"))
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(and:VALLDIF
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(not:<V_cmp_result>
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(match_dup:<V_cmp_result> 1))
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(match_operand:VALL 3 "register_operand" " w,0,w"))
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(match_operand:VALLDIF 3 "register_operand" " w,0,w"))
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))]
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"TARGET_SIMD"
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"@
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@ -1681,10 +1681,10 @@
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)
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(define_expand "aarch64_simd_bsl<mode>"
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[(match_operand:VALL 0 "register_operand")
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[(match_operand:VALLDIF 0 "register_operand")
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(match_operand:<V_cmp_result> 1 "register_operand")
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(match_operand:VALL 2 "register_operand")
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(match_operand:VALL 3 "register_operand")]
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(match_operand:VALLDIF 2 "register_operand")
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(match_operand:VALLDIF 3 "register_operand")]
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"TARGET_SIMD"
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{
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/* We can't alias operands together if they have different modes. */
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@ -4839,259 +4839,6 @@ vaddlvq_u32 (uint32x4_t a)
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return result;
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}
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__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
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vbsl_f32 (uint32x2_t a, float32x2_t b, float32x2_t c)
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{
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float32x2_t result;
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__asm__ ("bsl %0.8b, %2.8b, %3.8b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
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vbsl_p8 (uint8x8_t a, poly8x8_t b, poly8x8_t c)
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{
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poly8x8_t result;
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__asm__ ("bsl %0.8b, %2.8b, %3.8b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
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vbsl_p16 (uint16x4_t a, poly16x4_t b, poly16x4_t c)
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{
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poly16x4_t result;
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__asm__ ("bsl %0.8b, %2.8b, %3.8b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
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vbsl_s8 (uint8x8_t a, int8x8_t b, int8x8_t c)
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{
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int8x8_t result;
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__asm__ ("bsl %0.8b, %2.8b, %3.8b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
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vbsl_s16 (uint16x4_t a, int16x4_t b, int16x4_t c)
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{
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int16x4_t result;
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__asm__ ("bsl %0.8b, %2.8b, %3.8b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
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vbsl_s32 (uint32x2_t a, int32x2_t b, int32x2_t c)
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{
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int32x2_t result;
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__asm__ ("bsl %0.8b, %2.8b, %3.8b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
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vbsl_s64 (uint64x1_t a, int64x1_t b, int64x1_t c)
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{
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int64x1_t result;
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__asm__ ("bsl %0.8b, %2.8b, %3.8b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
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vbsl_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)
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{
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uint8x8_t result;
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__asm__ ("bsl %0.8b, %2.8b, %3.8b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
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vbsl_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)
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{
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uint16x4_t result;
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__asm__ ("bsl %0.8b, %2.8b, %3.8b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
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vbsl_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)
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{
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uint32x2_t result;
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__asm__ ("bsl %0.8b, %2.8b, %3.8b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
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vbsl_u64 (uint64x1_t a, uint64x1_t b, uint64x1_t c)
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{
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uint64x1_t result;
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__asm__ ("bsl %0.8b, %2.8b, %3.8b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
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vbslq_f32 (uint32x4_t a, float32x4_t b, float32x4_t c)
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{
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float32x4_t result;
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__asm__ ("bsl %0.16b, %2.16b, %3.16b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
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vbslq_f64 (uint64x2_t a, float64x2_t b, float64x2_t c)
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{
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float64x2_t result;
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__asm__ ("bsl %0.16b, %2.16b, %3.16b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
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vbslq_p8 (uint8x16_t a, poly8x16_t b, poly8x16_t c)
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{
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poly8x16_t result;
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__asm__ ("bsl %0.16b, %2.16b, %3.16b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
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vbslq_p16 (uint16x8_t a, poly16x8_t b, poly16x8_t c)
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{
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poly16x8_t result;
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__asm__ ("bsl %0.16b, %2.16b, %3.16b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
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vbslq_s8 (uint8x16_t a, int8x16_t b, int8x16_t c)
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{
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int8x16_t result;
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__asm__ ("bsl %0.16b, %2.16b, %3.16b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
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vbslq_s16 (uint16x8_t a, int16x8_t b, int16x8_t c)
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{
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int16x8_t result;
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__asm__ ("bsl %0.16b, %2.16b, %3.16b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
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vbslq_s32 (uint32x4_t a, int32x4_t b, int32x4_t c)
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{
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int32x4_t result;
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__asm__ ("bsl %0.16b, %2.16b, %3.16b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
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vbslq_s64 (uint64x2_t a, int64x2_t b, int64x2_t c)
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{
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int64x2_t result;
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__asm__ ("bsl %0.16b, %2.16b, %3.16b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
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vbslq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)
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{
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uint8x16_t result;
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__asm__ ("bsl %0.16b, %2.16b, %3.16b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
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vbslq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)
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{
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uint16x8_t result;
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__asm__ ("bsl %0.16b, %2.16b, %3.16b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
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vbslq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
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{
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uint32x4_t result;
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__asm__ ("bsl %0.16b, %2.16b, %3.16b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
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vbslq_u64 (uint64x2_t a, uint64x2_t b, uint64x2_t c)
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{
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uint64x2_t result;
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__asm__ ("bsl %0.16b, %2.16b, %3.16b"
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: "=w"(result)
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: "0"(a), "w"(b), "w"(c)
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: /* No clobbers */);
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return result;
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||||
}
|
||||
|
||||
__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
|
||||
vcls_s8 (int8x8_t a)
|
||||
{
|
||||
@ -15793,6 +15540,146 @@ vaddvq_f64 (float64x2_t __a)
|
||||
return vgetq_lane_f64 (__t, __LANE0 (2));
|
||||
}
|
||||
|
||||
/* vbsl */
|
||||
|
||||
__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
|
||||
vbsl_f32 (uint32x2_t __a, float32x2_t __b, float32x2_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bslv2sf_suss (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
|
||||
vbsl_p8 (uint8x8_t __a, poly8x8_t __b, poly8x8_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bslv8qi_pupp (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
|
||||
vbsl_p16 (uint16x4_t __a, poly16x4_t __b, poly16x4_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bslv4hi_pupp (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
|
||||
vbsl_s8 (uint8x8_t __a, int8x8_t __b, int8x8_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bslv8qi_suss (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
|
||||
vbsl_s16 (uint16x4_t __a, int16x4_t __b, int16x4_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bslv4hi_suss (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
|
||||
vbsl_s32 (uint32x2_t __a, int32x2_t __b, int32x2_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bslv2si_suss (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
|
||||
vbsl_s64 (uint64x1_t __a, int64x1_t __b, int64x1_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bsldi_suss (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
|
||||
vbsl_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bslv8qi_uuuu (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
|
||||
vbsl_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bslv4hi_uuuu (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
|
||||
vbsl_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bslv2si_uuuu (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
|
||||
vbsl_u64 (uint64x1_t __a, uint64x1_t __b, uint64x1_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bsldi_uuuu (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
|
||||
vbslq_f32 (uint32x4_t __a, float32x4_t __b, float32x4_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bslv4sf_suss (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
|
||||
vbslq_f64 (uint64x2_t __a, float64x2_t __b, float64x2_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bslv2df_suss (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
|
||||
vbslq_p8 (uint8x16_t __a, poly8x16_t __b, poly8x16_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bslv16qi_pupp (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
|
||||
vbslq_p16 (uint16x8_t __a, poly16x8_t __b, poly16x8_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bslv8hi_pupp (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
|
||||
vbslq_s8 (uint8x16_t __a, int8x16_t __b, int8x16_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bslv16qi_suss (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
|
||||
vbslq_s16 (uint16x8_t __a, int16x8_t __b, int16x8_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bslv8hi_suss (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
|
||||
vbslq_s32 (uint32x4_t __a, int32x4_t __b, int32x4_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bslv4si_suss (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
|
||||
vbslq_s64 (uint64x2_t __a, int64x2_t __b, int64x2_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bslv2di_suss (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
|
||||
vbslq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bslv16qi_uuuu (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
|
||||
vbslq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bslv8hi_uuuu (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
|
||||
vbslq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bslv4si_uuuu (__a, __b, __c);
|
||||
}
|
||||
|
||||
__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
|
||||
vbslq_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c)
|
||||
{
|
||||
return __builtin_aarch64_simd_bslv2di_uuuu (__a, __b, __c);
|
||||
}
|
||||
|
||||
/* vcage */
|
||||
|
||||
__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
|
||||
|
||||
@ -107,6 +107,10 @@
|
||||
;; All vector modes and DI.
|
||||
(define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
|
||||
|
||||
;; All vector modes and DI and DF.
|
||||
(define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI
|
||||
V2DI V2SF V4SF V2DF DI DF])
|
||||
|
||||
;; Vector modes for Integer reduction across lanes.
|
||||
(define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
|
||||
|
||||
@ -363,7 +367,8 @@
|
||||
(V4HI "8b") (V8HI "16b")
|
||||
(V2SI "8b") (V4SI "16b")
|
||||
(V2DI "16b") (V2SF "8b")
|
||||
(V4SF "16b") (V2DF "16b")])
|
||||
(V4SF "16b") (V2DF "16b")
|
||||
(DI "8b") (DF "8b")])
|
||||
|
||||
;; Define element mode for each vector mode.
|
||||
(define_mode_attr VEL [(V8QI "QI") (V16QI "QI")
|
||||
|
||||
Loading…
Reference in New Issue
Block a user