predicates.md (cc_operand): Delete predicate.
* config/bfin/predicates.md (cc_operand): Delete predicate. All uses replaced with register_operand. * config/bfin/bfin.c (bfin_register_move_cost): Moving CC to any non-DREG is expensive. * config/bfin/bfin.h (FIXED_REGISTERS): CC isn't fixed. * config/bfin/bfin.md (movbi): Fix constraints and template for moves involving memory. From-SVN: r111336
This commit is contained in:
Bernd Schmidt
Bernd Schmidt
parent
ee2312f34f
commit
4729dc926f
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@ -1,3 +1,13 @@
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2006-02-21 Bernd Schmidt <bernd.schmidt@analog.com>
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* config/bfin/predicates.md (cc_operand): Delete predicate. All uses
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replaced with register_operand.
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* config/bfin/bfin.c (bfin_register_move_cost): Moving CC to any
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non-DREG is expensive.
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* config/bfin/bfin.h (FIXED_REGISTERS): CC isn't fixed.
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* config/bfin/bfin.md (movbi): Fix constraints and template for moves
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involving memory.
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2006-02-21 Joseph S. Myers <joseph@codesourcery.com>
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* doc/install.texi2html: Use set -e.
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@ -1,5 +1,5 @@
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/* The Blackfin code generation auxiliary output file.
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Copyright (C) 2005 Free Software Foundation, Inc.
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Copyright (C) 2005, 2006 Free Software Foundation, Inc.
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Contributed by Analog Devices.
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This file is part of GCC.
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@ -1685,6 +1685,11 @@ int
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bfin_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
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enum reg_class class1, enum reg_class class2)
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{
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/* These need secondary reloads, so they're more expensive. */
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if ((class1 == CCREGS && class2 != DREGS)
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|| (class1 != DREGS && class2 == CCREGS))
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return 4;
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/* If optimizing for size, always prefer reg-reg over reg-memory moves. */
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if (optimize_size)
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return 2;
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@ -1788,6 +1793,7 @@ bfin_secondary_reload (bool in_p, rtx x, enum reg_class class,
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return DREGS;
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if (x_class == CCREGS && class != DREGS)
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return DREGS;
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/* All registers other than AREGS can load arbitrary constants. The only
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case that remains is MEM. */
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if (code == MEM)
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@ -1,5 +1,5 @@
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/* Definitions for the Blackfin port.
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Copyright (C) 2005 Free Software Foundation, Inc.
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Copyright (C) 2005, 2006 Free Software Foundation, Inc.
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Contributed by Analog Devices.
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This file is part of GCC.
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@ -256,7 +256,7 @@ extern const char *bfin_library_id_string;
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/*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
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0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
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/*a0 a1 cc rets/i/x/n/e astat seqstat usp argp */ \
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0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
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0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
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}
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/* 1 for registers not available across function calls.
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@ -1,5 +1,5 @@
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;;- Machine description for Blackfin for GNU compiler
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;; Copyright 2005 Free Software Foundation, Inc.
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;; Copyright 2005, 2006 Free Software Foundation, Inc.
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;; Contributed by Analog Devices.
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;; This file is part of GCC.
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@ -239,7 +239,7 @@
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(define_insn "*movsicc_insn1"
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[(set (match_operand:SI 0 "register_operand" "=da,da,da")
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(if_then_else:SI
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(eq:BI (match_operand:BI 3 "cc_operand" "C,C,C")
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(eq:BI (match_operand:BI 3 "register_operand" "C,C,C")
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(const_int 0))
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(match_operand:SI 1 "register_operand" "da,0,da")
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(match_operand:SI 2 "register_operand" "0,da,da")))]
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@ -254,7 +254,7 @@
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(define_insn "*movsicc_insn2"
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[(set (match_operand:SI 0 "register_operand" "=da,da,da")
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(if_then_else:SI
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(ne:BI (match_operand:BI 3 "cc_operand" "C,C,C")
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(ne:BI (match_operand:BI 3 "register_operand" "C,C,C")
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(const_int 0))
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(match_operand:SI 1 "register_operand" "0,da,da")
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(match_operand:SI 2 "register_operand" "da,0,da")))]
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@ -344,15 +344,15 @@
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})
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(define_insn "movbi"
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[(set (match_operand:BI 0 "nonimmediate_operand" "=x,x,d,mr,C,d,C")
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(match_operand:BI 1 "general_operand" "x,xKs3,mr,d,d,C,P0"))]
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[(set (match_operand:BI 0 "nonimmediate_operand" "=x,x,d,md,C,d,C")
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(match_operand:BI 1 "general_operand" "x,xKs3,md,d,d,C,P0"))]
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""
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"@
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%0 = %1;
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%0 = %1 (X);
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%0 = %1;
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%0 = %1;
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%0 = B %1 (Z);
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B %0 = %1;
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CC = %1;
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%0 = CC;
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R0 = R0 | R0; CC = AC0;"
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@ -967,7 +967,7 @@
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;; Bit test instructions
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(define_insn "*not_bittst"
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[(set (match_operand:BI 0 "cc_operand" "=C")
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[(set (match_operand:BI 0 "register_operand" "=C")
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(eq:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
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(const_int 1)
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(match_operand:SI 2 "immediate_operand" "Ku5"))
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@ -977,7 +977,7 @@
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[(set_attr "type" "alu0")])
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(define_insn "*bittst"
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[(set (match_operand:BI 0 "cc_operand" "=C")
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[(set (match_operand:BI 0 "register_operand" "=C")
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(ne:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
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(const_int 1)
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(match_operand:SI 2 "immediate_operand" "Ku5"))
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@ -1530,7 +1530,7 @@
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})
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(define_insn "compare_eq"
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[(set (match_operand:BI 0 "cc_operand" "=C,C")
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[(set (match_operand:BI 0 "register_operand" "=C,C")
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(eq:BI (match_operand:SI 1 "register_operand" "d,a")
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(match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
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""
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@ -1538,7 +1538,7 @@
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[(set_attr "type" "compare")])
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(define_insn "compare_ne"
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[(set (match_operand:BI 0 "cc_operand" "=C,C")
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[(set (match_operand:BI 0 "register_operand" "=C,C")
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(ne:BI (match_operand:SI 1 "register_operand" "d,a")
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(match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
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"0"
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@ -1546,7 +1546,7 @@
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[(set_attr "type" "compare")])
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(define_insn "compare_lt"
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[(set (match_operand:BI 0 "cc_operand" "=C,C")
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[(set (match_operand:BI 0 "register_operand" "=C,C")
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(lt:BI (match_operand:SI 1 "register_operand" "d,a")
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(match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
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""
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@ -1554,7 +1554,7 @@
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[(set_attr "type" "compare")])
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(define_insn "compare_le"
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[(set (match_operand:BI 0 "cc_operand" "=C,C")
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[(set (match_operand:BI 0 "register_operand" "=C,C")
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(le:BI (match_operand:SI 1 "register_operand" "d,a")
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(match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
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""
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@ -1562,7 +1562,7 @@
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[(set_attr "type" "compare")])
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(define_insn "compare_leu"
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[(set (match_operand:BI 0 "cc_operand" "=C,C")
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[(set (match_operand:BI 0 "register_operand" "=C,C")
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(leu:BI (match_operand:SI 1 "register_operand" "d,a")
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(match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))]
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""
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@ -1570,7 +1570,7 @@
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[(set_attr "type" "compare")])
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(define_insn "compare_ltu"
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[(set (match_operand:BI 0 "cc_operand" "=C,C")
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[(set (match_operand:BI 0 "register_operand" "=C,C")
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(ltu:BI (match_operand:SI 1 "register_operand" "d,a")
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(match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))]
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""
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@ -1735,7 +1735,7 @@
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[(set (pc)
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(if_then_else
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(match_operator 0 "bfin_cbranch_operator"
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[(match_operand:BI 1 "cc_operand" "C")
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[(match_operand:BI 1 "register_operand" "C")
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(match_operand:BI 2 "immediate_operand" "P0")])
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(label_ref (match_operand 3 "" ""))
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(pc)))]
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@ -1753,7 +1753,7 @@
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[(set (pc)
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(if_then_else
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(match_operator 0 "bfin_cbranch_operator"
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[(match_operand:BI 1 "cc_operand" "C")
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[(match_operand:BI 1 "register_operand" "C")
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(match_operand:BI 2 "immediate_operand" "P0")])
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(label_ref (match_operand 3 "" ""))
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(pc)))
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@ -1769,7 +1769,7 @@
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[(set (pc)
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(if_then_else
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(match_operator 0 "bfin_cbranch_operator"
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[(match_operand:BI 1 "cc_operand" "C")
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[(match_operand:BI 1 "register_operand" "C")
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(match_operand:BI 2 "immediate_operand" "P0")])
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(label_ref (match_operand 3 "" ""))
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(pc)))
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@ -1845,7 +1845,7 @@
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;;;;;;;;;;;;;;;;;;;; CC2dreg ;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_insn "movsibi"
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[(set (match_operand:BI 0 "cc_operand" "=C")
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[(set (match_operand:BI 0 "register_operand" "=C")
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(ne:BI (match_operand:SI 1 "register_operand" "d")
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(const_int 0)))]
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""
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@ -1854,15 +1854,15 @@
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(define_insn "movbisi"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(ne:SI (match_operand:BI 1 "cc_operand" "C")
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(ne:SI (match_operand:BI 1 "register_operand" "C")
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(const_int 0)))]
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""
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"%0 = CC;"
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[(set_attr "length" "2")])
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(define_insn ""
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[(set (match_operand:BI 0 "cc_operand" "=C")
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(eq:BI (match_operand:BI 1 "cc_operand" " 0")
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[(set (match_operand:BI 0 "register_operand" "=C")
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(eq:BI (match_operand:BI 1 "register_operand" " 0")
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(const_int 0)))]
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""
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"%0 = ! %0;" /* NOT CC;" */
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@ -1,4 +1,6 @@
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;; Predicate definitions for the Blackfin.
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;; Copyright (C) 2005, 2006 Free Software Foundation, Inc.
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;; Contributed by Analog Devices.
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;;
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;; This file is part of GCC.
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;;
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@ -65,11 +67,6 @@
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return 1;
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})
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;; Return nonzero if OP is the CC register.
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(define_predicate "cc_operand"
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(and (match_code "reg")
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(match_test "REGNO (op) == REG_CC && GET_MODE (op) == BImode")))
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;; Return nonzero if OP is a register or a 7 bit signed constant.
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(define_predicate "reg_or_7bit_operand"
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(ior (match_operand 0 "register_operand")
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