re PR target/49781 ([x32] Unnecessary lea in x32 mode)
PR target/49781 * config/i386/i386.c (ix86_decompose_address): Allow zero-extended SImode addresses. (ix86_print_operand_address): Handle zero-extended addresses. (memory_address_length): Add length of addr32 prefix for zero-extended addresses. (ix86_secondary_reload): Handle moves to/from double-word general registers from/to zero-extended addresses. * config/i386/predicates.md (lea_address_operand): Reject zero-extended operands. From-SVN: r177566
This commit is contained in:
Uros Bizjak
parent
d7cfa3145f
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473b30ce95
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@ -1,8 +1,20 @@
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2011-08-07 Uros Bizjak <ubizjak@gmail.com>
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PR target/49781
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* config/i386/i386.c (ix86_decompose_address): Allow zero-extended
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SImode addresses.
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(ix86_print_operand_address): Handle zero-extended addresses.
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(memory_address_length): Add length of addr32 prefix for
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zero-extended addresses.
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(ix86_secondary_reload): Handle moves to/from double-word general
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registers from/to zero-extended addresses.
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* config/i386/predicates.md (lea_address_operand): Reject
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zero-extended operands.
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2011-08-08 H.J. Lu <hongjiu.lu@intel.com>
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PR other/48007
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* config.gcc (libgcc_tm_file): Add i386/value-unwind.h for
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Linux/x86.
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* config.gcc (libgcc_tm_file): Add i386/value-unwind.h for Linux/x86.
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* system.h (REG_VALUE_IN_UNWIND_CONTEXT): Poisoned.
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(ASSUME_EXTENDED_UNWIND_CONTEXT): Likewise.
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@ -43,10 +55,8 @@
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* config/sparc/driver-sparc.c: New file.
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* config/sparc/x-sparc: New file.
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* config.host: Use driver-sparc.o, sparc/x-sparc on
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sparc*-*-solaris2*.
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* config/sparc/sparc.opt (native): New value for enum
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processor_type.
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* config.host: Use driver-sparc.o, sparc/x-sparc on sparc*-*-solaris2*.
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* config/sparc/sparc.opt (native): New value for enum processor_type.
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* config/sparc/sparc-opts.h (PROCESSOR_NATIVE): Declare.
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* config/sparc/sparc.c (sparc_option_override): Abort if
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PROCESSOR_NATIVE gets here.
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@ -93,7 +103,7 @@
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(TARGET_INSTANTIATE_DECLS): New define.
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2011-08-06 Paolo Bonzini <bonzini@gnu.org>
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Mikael Morin <mikael.morin@sfr.fr>
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Mikael Morin <mikael.morin@sfr.fr>
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* Makefile.in (INCLUDES_FOR_TARGET): New.
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(LIBGCC2_CFLAGS): Use it.
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@ -11142,6 +11142,14 @@ ix86_decompose_address (rtx addr, struct ix86_address *out)
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int retval = 1;
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enum ix86_address_seg seg = SEG_DEFAULT;
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/* Allow zero-extended SImode addresses,
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they will be emitted with addr32 prefix. */
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if (TARGET_64BIT
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&& GET_CODE (addr) == ZERO_EXTEND
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&& GET_MODE (addr) == DImode
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&& GET_MODE (XEXP (addr, 0)) == SImode)
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addr = XEXP (addr, 0);
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if (REG_P (addr))
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base = addr;
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else if (GET_CODE (addr) == SUBREG)
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@ -14159,8 +14167,12 @@ ix86_print_operand_address (FILE *file, rtx addr)
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}
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else
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{
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/* Print DImode registers on 64bit targets to avoid addr32 prefixes. */
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int code = TARGET_64BIT ? 'q' : 0;
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int code = 0;
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/* Print SImode registers for zero-extended addresses to force
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addr32 prefix. Otherwise print DImode registers to avoid it. */
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if (TARGET_64BIT)
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code = (GET_CODE (addr) == ZERO_EXTEND) ? 'l' : 'q';
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if (ASSEMBLER_DIALECT == ASM_ATT)
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{
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@ -21772,7 +21784,8 @@ assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
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}
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/* Calculate the length of the memory address in the instruction
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encoding. Does not include the one-byte modrm, opcode, or prefix. */
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encoding. Includes addr32 prefix, does not include the one-byte modrm,
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opcode, or other prefixes. */
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int
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memory_address_length (rtx addr)
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@ -21799,7 +21812,9 @@ memory_address_length (rtx addr)
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base = parts.base;
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index = parts.index;
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disp = parts.disp;
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len = 0;
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/* Add length of addr32 prefix. */
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len = (GET_CODE (addr) == ZERO_EXTEND);
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/* Rule of thumb:
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- esp as the base always wants an index,
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@ -28233,6 +28248,15 @@ ix86_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
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enum machine_mode mode,
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secondary_reload_info *sri ATTRIBUTE_UNUSED)
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{
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/* Double-word spills from general registers to non-offsettable memory
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references (zero-extended addresses) go through XMM register. */
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if (TARGET_64BIT
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&& MEM_P (x)
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&& GET_MODE_SIZE (mode) > UNITS_PER_WORD
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&& rclass == GENERAL_REGS
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&& !offsettable_memref_p (x))
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return SSE_REGS;
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/* QImode spills from non-QI registers require
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intermediate register on 32bit targets. */
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if (!TARGET_64BIT
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@ -801,6 +801,10 @@
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struct ix86_address parts;
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int ok;
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/* LEA handles zero-extend by itself. */
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if (GET_CODE (op) == ZERO_EXTEND)
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return false;
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ok = ix86_decompose_address (op, &parts);
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gcc_assert (ok);
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return parts.seg == SEG_DEFAULT;
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