sh.h (FIRST_GENERAL_REG, [...]): New.
* config/sh/sh.h (FIRST_GENERAL_REG, LAST_GENERAL_REG): New. Moved most register-number #defines... * config/sh/sh.md (define_constants): ... here. Use macros to refer to registers and unspecs. * config/sh/sh.c: Likewise. From-SVN: r37683
This commit is contained in:
parent
27ddcd48c1
commit
4773afa487
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@ -1,3 +1,11 @@
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Thu Nov 23 02:09:09 2000 Alexandre Oliva <aoliva@redhat.com>
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* config/sh/sh.h (FIRST_GENERAL_REG, LAST_GENERAL_REG): New.
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Moved most register-number #defines...
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* config/sh/sh.md (define_constants): ... here. Use macros to
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refer to registers and unspecs.
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* config/sh/sh.c: Likewise.
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Thu Nov 23 01:01:32 2000 J"orn Rennecke <amylaar@redhat.com>
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Thu Nov 23 01:01:32 2000 J"orn Rennecke <amylaar@redhat.com>
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* Makefile.in (HOST_CFLAGS): Add -DGENERATOR_FILE.
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* Makefile.in (HOST_CFLAGS): Add -DGENERATOR_FILE.
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@ -598,7 +598,7 @@ from_compare (operands, code)
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}
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}
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else
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else
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insn = gen_rtx_SET (VOIDmode,
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insn = gen_rtx_SET (VOIDmode,
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gen_rtx_REG (SImode, 18),
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gen_rtx_REG (SImode, T_REG),
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gen_rtx (code, SImode, sh_compare_op0,
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gen_rtx (code, SImode, sh_compare_op0,
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sh_compare_op1));
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sh_compare_op1));
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if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
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if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
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@ -1596,7 +1596,7 @@ gen_shl_and (dest, left_rtx, mask_rtx, source)
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(match_operand:SI 2 "const_int_operand" "n")
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(match_operand:SI 2 "const_int_operand" "n")
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(match_operand:SI 3 "const_int_operand" "n")
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(match_operand:SI 3 "const_int_operand" "n")
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(const_int 0)))
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(const_int 0)))
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(clobber (reg:SI 18))]
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(clobber (reg:SI T_REG))]
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LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
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LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
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return 0 for simple left / right shift combination.
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return 0 for simple left / right shift combination.
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return 1 for left shift / 8 bit sign extend / left shift.
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return 1 for left shift / 8 bit sign extend / left shift.
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@ -2097,7 +2097,7 @@ mova_p (insn)
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return (GET_CODE (insn) == INSN
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return (GET_CODE (insn) == INSN
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&& GET_CODE (PATTERN (insn)) == SET
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&& GET_CODE (PATTERN (insn)) == SET
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&& GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
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&& GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
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&& XINT (SET_SRC (PATTERN (insn)), 1) == 1);
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&& XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA);
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}
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}
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/* Find the last barrier from insn FROM which is close enough to hold the
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/* Find the last barrier from insn FROM which is close enough to hold the
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@ -2786,7 +2786,7 @@ barrier_align (barrier_or_label)
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if (GET_CODE (pat) == ADDR_DIFF_VEC)
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if (GET_CODE (pat) == ADDR_DIFF_VEC)
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return 2;
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return 2;
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if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == 1)
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if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
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/* This is a barrier in front of a constant table. */
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/* This is a barrier in front of a constant table. */
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return 0;
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return 0;
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@ -3282,7 +3282,7 @@ machine_dependent_reorg (first)
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/* This is a mova needing a label. Create it. */
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/* This is a mova needing a label. Create it. */
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else if (GET_CODE (src) == CONST
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else if (GET_CODE (src) == CONST
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&& GET_CODE (XEXP (src, 0)) == UNSPEC
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&& GET_CODE (XEXP (src, 0)) == UNSPEC
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&& XINT (XEXP (src, 0), 1) == 1
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&& XINT (XEXP (src, 0), 1) == UNSPEC_MOVA
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&& GET_CODE (XVECEXP (XEXP (src, 0),
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&& GET_CODE (XVECEXP (XEXP (src, 0),
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0, 0)) == CONST)
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0, 0)) == CONST)
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{
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{
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@ -3290,7 +3290,8 @@ machine_dependent_reorg (first)
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0, 0), mode, 0);
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0, 0), mode, 0);
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newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
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newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
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newsrc = gen_rtx_UNSPEC (VOIDmode,
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newsrc = gen_rtx_UNSPEC (VOIDmode,
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gen_rtvec (1, newsrc), 1);
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gen_rtvec (1, newsrc),
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UNSPEC_MOVA);
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}
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}
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else
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else
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{
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{
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@ -5000,7 +5001,7 @@ get_fpscr_rtx ()
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if (! fpscr_rtx)
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if (! fpscr_rtx)
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{
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{
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fpscr_rtx = gen_rtx (REG, PSImode, 48);
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fpscr_rtx = gen_rtx (REG, PSImode, FPSCR_REG);
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REG_USERVAR_P (fpscr_rtx) = 1;
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REG_USERVAR_P (fpscr_rtx) = 1;
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ggc_add_rtx_root (&fpscr_rtx, 1);
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ggc_add_rtx_root (&fpscr_rtx, 1);
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mark_user_reg (fpscr_rtx);
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mark_user_reg (fpscr_rtx);
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@ -5276,7 +5277,10 @@ nonpic_symbol_mentioned_p (x)
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return 1;
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return 1;
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if (GET_CODE (x) == UNSPEC
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if (GET_CODE (x) == UNSPEC
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&& (XINT (x, 1) >= 6 && XINT (x, 1) <= 9))
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&& (XINT (x, 1) == UNSPEC_PIC
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|| XINT (x, 1) == UNSPEC_GOT
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|| XINT (x, 1) == UNSPEC_GOTOFF
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|| XINT (x, 1) == UNSPEC_PLT))
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return 0;
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return 0;
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fmt = GET_RTX_FORMAT (GET_CODE (x));
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fmt = GET_RTX_FORMAT (GET_CODE (x));
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@ -432,20 +432,18 @@ do { \
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All registers that the compiler knows about must be given numbers,
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All registers that the compiler knows about must be given numbers,
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even those that are not normally considered general registers. */
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even those that are not normally considered general registers. */
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#define AP_REG 16
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/* There are many other relevant definitions in sh.md's md_constants. */
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#define PR_REG 17
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#define T_REG 18
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#define FIRST_GENERAL_REG R0_REG
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#define GBR_REG 19
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#define LAST_GENERAL_REG (FIRST_GENERAL_REG + 15)
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#define MACH_REG 20
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#define FIRST_FP_REG DR0_REG
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#define MACL_REG 21
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#define LAST_FP_REG (FIRST_FP_REG + 15)
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#define SPECIAL_REG(REGNO) ((REGNO) >= 18 && (REGNO) <= 21)
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#define FIRST_XD_REG XD0_REG
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#define FPUL_REG 22
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#define LAST_XD_REG (FIRST_XD_REG + 7)
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#define RAP_REG 23
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#define FIRST_FP_REG 24
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#define SPECIAL_REG(REGNO) \
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#define LAST_FP_REG 39
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((REGNO) == GBR_REG || (REGNO) == T_REG \
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#define FIRST_XD_REG 40
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|| (REGNO) == MACH_REG || (REGNO) == MACL_REG)
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#define LAST_XD_REG 47
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#define FPSCR_REG 48
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#define FIRST_PSEUDO_REGISTER 49
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#define FIRST_PSEUDO_REGISTER 49
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/* #define PC_REGNUM 15*/
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/* #define PC_REGNUM 15*/
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/* Register to use for pushing function arguments. */
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/* Register to use for pushing function arguments. */
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#define STACK_POINTER_REGNUM 15
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#define STACK_POINTER_REGNUM SP_REG
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/* Base register for access to local variables of the function. */
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/* Base register for access to local variables of the function. */
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#define FRAME_POINTER_REGNUM 14
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#define FRAME_POINTER_REGNUM FP_REG
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/* Fake register that holds the address on the stack of the
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/* Fake register that holds the address on the stack of the
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current function's return address. */
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current function's return address. */
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#define RETURN_ADDRESS_POINTER_REGNUM 23
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#define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
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/* Register to hold the addressing base for position independent
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/* Register to hold the addressing base for position independent
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code access to data items. */
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code access to data items. */
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#define PIC_OFFSET_TABLE_REGNUM 12
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#define PIC_OFFSET_TABLE_REGNUM PIC_REG
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#define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
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#define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
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@ -831,7 +829,7 @@ extern enum reg_class reg_class_from_letter[];
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|| system_reg_operand (X, VOIDmode))))) \
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|| system_reg_operand (X, VOIDmode))))) \
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? GENERAL_REGS \
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? GENERAL_REGS \
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: (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
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: (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
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&& GET_CODE (X) == REG && REGNO (X) > 15 \
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&& GET_CODE (X) == REG && REGNO (X) > SP_REG \
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&& (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
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&& (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
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? GENERAL_REGS : NO_REGS)
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? GENERAL_REGS : NO_REGS)
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@ -886,8 +884,8 @@ extern enum reg_class reg_class_from_letter[];
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? 8 \
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? 8 \
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: 4)
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: 4)
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#define FIRST_PARM_REG 4
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#define FIRST_PARM_REG (FIRST_GENERAL_REG + 4)
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#define FIRST_RET_REG 0
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#define FIRST_RET_REG FIRST_GENERAL_REG
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#define FIRST_FP_PARM_REG (FIRST_FP_REG + 4)
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#define FIRST_FP_PARM_REG (FIRST_FP_REG + 4)
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#define FIRST_FP_RET_REG FIRST_FP_REG
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#define FIRST_FP_RET_REG FIRST_FP_REG
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@ -1269,7 +1267,7 @@ extern int current_function_anonymous_args;
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#define REGNO_OK_FOR_BASE_P(REGNO) \
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#define REGNO_OK_FOR_BASE_P(REGNO) \
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((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG)
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((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG)
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#define REGNO_OK_FOR_INDEX_P(REGNO) \
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#define REGNO_OK_FOR_INDEX_P(REGNO) \
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((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0)
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((REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
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/* Maximum number of registers that can appear in a valid memory
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/* Maximum number of registers that can appear in a valid memory
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address. */
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address. */
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@ -1299,17 +1297,17 @@ extern int current_function_anonymous_args;
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/* Nonzero if X is a hard reg that can be used as a base reg
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/* Nonzero if X is a hard reg that can be used as a base reg
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or if it is a pseudo reg. */
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or if it is a pseudo reg. */
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#define REG_OK_FOR_BASE_P(X) \
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#define REG_OK_FOR_BASE_P(X) \
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(REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
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(REGNO (X) <= AP_REG || REGNO (X) >= FIRST_PSEUDO_REGISTER)
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/* Nonzero if X is a hard reg that can be used as an index
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/* Nonzero if X is a hard reg that can be used as an index
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or if it is a pseudo reg. */
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or if it is a pseudo reg. */
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#define REG_OK_FOR_INDEX_P(X) \
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#define REG_OK_FOR_INDEX_P(X) \
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(REGNO (X) == 0 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
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(REGNO (X) == R0_REG || REGNO (X) >= FIRST_PSEUDO_REGISTER)
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/* Nonzero if X/OFFSET is a hard reg that can be used as an index
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/* Nonzero if X/OFFSET is a hard reg that can be used as an index
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or if X is a pseudo reg. */
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or if X is a pseudo reg. */
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#define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
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#define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
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((REGNO (X) == 0 && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
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((REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
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#else
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#else
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