re PR target/21723 (ICE while building libgfortran)
PR target/21723 * pa.md: Remove fcpy alternative from movhi and movqi patterns. * pa32-regs.h (HARD_REGNO_NREGS): Return two floating point registers for complex modes when generating code for PA 1.0. (VALID_FP_MODE_P): New macro. (HARD_REGNO_MODE_OK): Use VALID_FP_MODE_P. Use non-overlapping register sets for all general and floating point modes. Align wide floating point modes to even register boundaries to comply with architectural requirements. (CLASS_MAX_NREGS): Update to align with change to HARD_REGNO_NREGS. * pa64-regs.h (HARD_REGNO_NREGS): Update comment and formatting. (VALID_FP_MODE_P): New macro. (HARD_REGNO_MODE_OK): Use VALID_FP_MODE_P. Use non-overlapping register sets for all general and floating point modes. Align wide floating point modes to even register boundaries to comply with architectural requirements. From-SVN: r101613
This commit is contained in:
John David Anglin
John David Anglin
parent
f94ac7b644
commit
47971fa72d
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@ -1,3 +1,22 @@
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2005-07-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
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PR target/21723
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* pa.md: Remove fcpy alternative from movhi and movqi patterns.
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* pa32-regs.h (HARD_REGNO_NREGS): Return two floating point registers
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for complex modes when generating code for PA 1.0.
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(VALID_FP_MODE_P): New macro.
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(HARD_REGNO_MODE_OK): Use VALID_FP_MODE_P. Use non-overlapping register
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sets for all general and floating point modes. Align wide floating
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point modes to even register boundaries to comply with architectural
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requirements.
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(CLASS_MAX_NREGS): Update to align with change to HARD_REGNO_NREGS.
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* pa64-regs.h (HARD_REGNO_NREGS): Update comment and formatting.
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(VALID_FP_MODE_P): New macro.
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(HARD_REGNO_MODE_OK): Use VALID_FP_MODE_P. Use non-overlapping register
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sets for all general and floating point modes. Align wide floating
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point modes to even register boundaries to comply with architectural
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requirements.
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2005-07-04 Diego Novillo <dnovillo@redhat.com>
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* tree-dump.c (dump_files): Initialize dump number for .cgraph
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@ -2896,9 +2896,9 @@
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(define_insn ""
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[(set (match_operand:HI 0 "move_dest_operand"
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"=r,r,r,r,r,Q,!*q,!r,!*f")
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"=r,r,r,r,r,Q,!*q,!r")
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(match_operand:HI 1 "move_src_operand"
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"r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
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"r,J,N,K,RQ,rM,!rM,!*q"))]
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"register_operand (operands[0], HImode)
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|| reg_or_0_operand (operands[1], HImode)"
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"@
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@ -2909,11 +2909,10 @@
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ldh%M1 %1,%0
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sth%M0 %r1,%0
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mtsar %r1
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{mfctl|mfctl,w} %sar,%0
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fcpy,sgl %f1,%0"
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[(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu")
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{mfctl|mfctl,w} %sar,%0"
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[(set_attr "type" "move,move,move,shift,load,store,move,move")
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(set_attr "pa_combine_type" "addmove")
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(set_attr "length" "4,4,4,4,4,4,4,4,4")])
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(set_attr "length" "4,4,4,4,4,4,4,4")])
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(define_insn ""
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[(set (match_operand:HI 0 "register_operand" "=r")
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@ -3021,9 +3020,9 @@
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(define_insn ""
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[(set (match_operand:QI 0 "move_dest_operand"
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"=r,r,r,r,r,Q,!*q,!r,!*f")
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"=r,r,r,r,r,Q,!*q,!r")
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(match_operand:QI 1 "move_src_operand"
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"r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
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"r,J,N,K,RQ,rM,!rM,!*q"))]
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"register_operand (operands[0], QImode)
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|| reg_or_0_operand (operands[1], QImode)"
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"@
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@ -3034,11 +3033,10 @@
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ldb%M1 %1,%0
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stb%M0 %r1,%0
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mtsar %r1
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{mfctl|mfctl,w} %%sar,%0
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fcpy,sgl %f1,%0"
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[(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu")
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{mfctl|mfctl,w} %%sar,%0"
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[(set_attr "type" "move,move,move,shift,load,store,move,move")
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(set_attr "pa_combine_type" "addmove")
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(set_attr "length" "4,4,4,4,4,4,4,4,4")])
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(set_attr "length" "4,4,4,4,4,4,4,4")])
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(define_insn ""
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[(set (match_operand:QI 0 "register_operand" "=r")
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@ -156,32 +156,69 @@
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This is ordinarily the length in words of a value of mode MODE
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but can be less for certain modes in special long registers.
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On the HP-PA, ordinary registers hold 32 bits worth;
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The floating point registers are 64 bits wide. Snake fp regs are 32
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bits wide */
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On the HP-PA, general registers are 32 bits wide. The floating
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point registers are 64 bits wide. Snake fp regs are treated as
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32 bits wide since the left and right parts are independently
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accessible. */
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#define HARD_REGNO_NREGS(REGNO, MODE) \
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(FP_REGNO_P (REGNO) \
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? (!TARGET_PA_11 ? 1 : (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \
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: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
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? (!TARGET_PA_11 \
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? COMPLEX_MODE_P (MODE) ? 2 : 1 \
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: (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \
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: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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/* There are no instructions that use DImode in PA 1.0, so we only
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allow it in PA 1.1 and later. */
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#define VALID_FP_MODE_P(MODE) \
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((MODE) == SFmode || (MODE) == DFmode \
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|| (MODE) == SCmode || (MODE) == DCmode \
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|| (MODE) == SImode || (TARGET_PA_11 && (MODE) == DImode))
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/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
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On the HP-PA, the cpu registers can hold any mode. For DImode, we
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choose a set of general register that includes the incoming arguments
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and the return value. We specify a set with no overlaps so that we don't
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have to specify that the destination register in patterns using this mode
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is an early clobber. */
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On the HP-PA, the cpu registers can hold any mode that fits in 32 bits.
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For the 64-bit modes, we choose a set of non-overlapping general registers
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that includes the incoming arguments and the return value. We specify a
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set with no overlaps so that we don't have to specify that the destination
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register is an early clobber in patterns using this mode. Except for the
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return value, the starting registers are odd. For 128 and 256 bit modes,
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we similarly specify non-overlapping sets of cpu registers. However,
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there aren't any patterns defined for modes larger than 64 bits at the
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moment.
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We limit the modes allowed in the floating point registers to the
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set of modes used in the machine definition. In addition, we allow
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the complex modes SCmode and DCmode. The real and imaginary parts
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of complex modes are allocated to separate registers. This might
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allow patterns to be defined in the future to operate on these values.
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The PA 2.0 architecture specifies that quad-precision floating-point
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values should start on an even floating point register. Thus, we
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choose non-overlapping sets of registers starting on even register
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boundaries for large modes. However, there is currently no support
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in the machine definition for modes larger than 64 bits. TFmode is
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supported under HP-UX using libcalls. Since TFmode values are passed
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by reference, they never need to be loaded into the floating-point
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registers. */
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#define HARD_REGNO_MODE_OK(REGNO, MODE) \
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((REGNO) == 0 ? (MODE) == CCmode || (MODE) == CCFPmode \
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/* On 1.0 machines, don't allow wide non-fp modes in fp regs. */ \
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: !TARGET_PA_11 && FP_REGNO_P (REGNO) \
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? GET_MODE_SIZE (MODE) <= 4 || GET_MODE_CLASS (MODE) == MODE_FLOAT \
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? (VALID_FP_MODE_P (MODE) \
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&& (GET_MODE_SIZE (MODE) <= 8 \
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|| (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 3) == 0))) \
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: FP_REGNO_P (REGNO) \
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? GET_MODE_SIZE (MODE) <= 4 || ((REGNO) & 1) == 0 \
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? (VALID_FP_MODE_P (MODE) \
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&& (GET_MODE_SIZE (MODE) <= 4 \
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|| (GET_MODE_SIZE (MODE) == 8 && ((REGNO) & 1) == 0) \
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|| (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 3) == 0) \
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|| (GET_MODE_SIZE (MODE) == 32 && ((REGNO) & 7) == 0))) \
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: (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \
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|| (GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD \
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&& ((((REGNO) & 1) == 1 && (REGNO) <= 25) || (REGNO) == 28)) \
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|| (GET_MODE_SIZE (MODE) == 4 * UNITS_PER_WORD \
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&& (((REGNO) & 3) == 3 && (REGNO) <= 23))))
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&& ((REGNO) & 3) == 3 && (REGNO) <= 23) \
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|| (GET_MODE_SIZE (MODE) == 8 * UNITS_PER_WORD \
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&& ((REGNO) & 7) == 3 && (REGNO) <= 19)))
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/* How to renumber registers for dbx and gdb.
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@ -276,7 +313,9 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
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needed to represent mode MODE in a register of class CLASS. */
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#define CLASS_MAX_NREGS(CLASS, MODE) \
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((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS \
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? (!TARGET_PA_11 ? 1 : (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \
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? (!TARGET_PA_11 \
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? COMPLEX_MODE_P (MODE) ? 2 : 1 \
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: (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \
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: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
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/* 1 if N is a possible register number for function argument passing. */
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@ -145,11 +145,19 @@ Boston, MA 02110-1301, USA. */
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This is ordinarily the length in words of a value of mode MODE
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but can be less for certain modes in special long registers.
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For PA64, GPRs and FPRs hold 64 bits worth (we ignore the 32bit
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addressability of the FPRs). i.e., we pretend each register holds
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precisely WORD_SIZE bits. */
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For PA64, GPRs and FPRs hold 64 bits worth. We ignore the 32-bit
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addressability of the FPRs and pretend each register holds precisely
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WORD_SIZE bits. Note that SCmode values are placed in a single FPR.
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Thus, any patterns defined to operate on these values would have to
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use the 32-bit addressability of the FPR registers. */
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#define HARD_REGNO_NREGS(REGNO, MODE) \
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((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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/* These are the valid FP modes. */
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#define VALID_FP_MODE_P(MODE) \
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((MODE) == SFmode || (MODE) == DFmode \
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|| (MODE) == SCmode || (MODE) == DCmode \
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|| (MODE) == SImode || (MODE) == DImode)
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/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
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On the HP-PA, the cpu registers can hold any mode. We
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@ -158,8 +166,16 @@ Boston, MA 02110-1301, USA. */
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((REGNO) == 0 \
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? (MODE) == CCmode || (MODE) == CCFPmode \
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/* Make wide modes be in aligned registers. */ \
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: FP_REGNO_P (REGNO) \
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? (VALID_FP_MODE_P (MODE) \
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&& (GET_MODE_SIZE (MODE) <= 8 \
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|| (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 1) == 0) \
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|| (GET_MODE_SIZE (MODE) == 32 && ((REGNO) & 3) == 0))) \
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: (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \
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|| (GET_MODE_SIZE (MODE) <= 2 * UNITS_PER_WORD && ((REGNO) & 1) == 0)))
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|| (GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD \
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&& ((((REGNO) & 1) == 1 && (REGNO) <= 25) || (REGNO) == 28)) \
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|| (GET_MODE_SIZE (MODE) == 4 * UNITS_PER_WORD \
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&& ((REGNO) & 3) == 3 && (REGNO) <= 23)))
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/* How to renumber registers for dbx and gdb.
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